Bug 1655848: vendor in new Cranelift to fix fuzzbug. r=jseward
authorChris Fallin <cfallin@mozilla.com>
Mon, 03 Aug 2020 16:53:46 +0000
changeset 3102968 e0ac26d4e4a5634cc38ee21f489a61bef7d82570
parent 3102967 ea03df7a155432fc9cd0b4155c59a7a5dd97e6de
child 3102969 969bad59a907ad4c93f5e4622d61e1a484f368d7
push id578529
push userreviewbot
push dateTue, 04 Aug 2020 02:36:56 +0000
treeherdertry@538c88f9f9fe [default view] [failures only]
reviewersjseward
bugs1655848
milestone81.0a1
Bug 1655848: vendor in new Cranelift to fix fuzzbug. r=jseward This patch vendors in the latest version of Cranelift, rev 026fb8d388964c7c1bace7019c4fe0d63c584560. This includes a fix for bug 1655848 (from GitHub PR #2081), as well as several other miscellaneous changes. Differential Revision: https://phabricator.services.mozilla.com/D85773
.cargo/config.in
Cargo.lock
Cargo.toml
third_party/rust/cranelift-codegen/.cargo-checksum.json
third_party/rust/cranelift-codegen/src/isa/aarch64/abi.rs
third_party/rust/cranelift-codegen/src/isa/x64/abi.rs
third_party/rust/cranelift-codegen/src/isa/x64/inst/args.rs
third_party/rust/cranelift-codegen/src/isa/x64/inst/emit.rs
third_party/rust/cranelift-codegen/src/isa/x64/inst/mod.rs
third_party/rust/cranelift-codegen/src/isa/x64/lower.rs
third_party/rust/cranelift-codegen/src/machinst/abi.rs
third_party/rust/cranelift-codegen/src/machinst/lower.rs
third_party/rust/cranelift-wasm/.cargo-checksum.json
third_party/rust/cranelift-wasm/src/environ/dummy.rs
third_party/rust/cranelift-wasm/src/environ/spec.rs
third_party/rust/cranelift-wasm/src/module_translator.rs
third_party/rust/cranelift-wasm/src/sections_translator.rs
--- a/.cargo/config.in
+++ b/.cargo/config.in
@@ -55,17 +55,17 @@ rev = "bce6358eb1026c13d2f1c6d365af37afe
 [source."https://github.com/djg/cubeb-pulse-rs"]
 git = "https://github.com/djg/cubeb-pulse-rs"
 replace-with = "vendored-sources"
 rev = "3224e2dee65c0726c448484d4c3c43956b9330ec"
 
 [source."https://github.com/bytecodealliance/wasmtime"]
 git = "https://github.com/bytecodealliance/wasmtime"
 replace-with = "vendored-sources"
-rev = "dd098656111396afa58e90084a705744e836bf10"
+rev = "026fb8d388964c7c1bace7019c4fe0d63c584560"
 
 [source."https://github.com/badboy/failure"]
 git = "https://github.com/badboy/failure"
 replace-with = "vendored-sources"
 rev = "64af847bc5fdcb6d2438bec8a6030812a80519a5"
 
 [source."https://github.com/PLSysSec/rlbox_lucet_sandbox/"]
 git = "https://github.com/PLSysSec/rlbox_lucet_sandbox/"
--- a/Cargo.lock
+++ b/Cargo.lock
@@ -748,77 +748,77 @@ source = "registry+https://github.com/ru
 checksum = "49726015ab0ca765144fcca61e4a7a543a16b795a777fa53f554da2fffff9a94"
 dependencies = [
  "cose",
 ]
 
 [[package]]
 name = "cranelift-bforest"
 version = "0.66.0"
-source = "git+https://github.com/bytecodealliance/wasmtime?rev=dd098656111396afa58e90084a705744e836bf10#dd098656111396afa58e90084a705744e836bf10"
+source = "git+https://github.com/bytecodealliance/wasmtime?rev=026fb8d388964c7c1bace7019c4fe0d63c584560#026fb8d388964c7c1bace7019c4fe0d63c584560"
 dependencies = [
  "cranelift-entity 0.66.0",
 ]
 
 [[package]]
 name = "cranelift-codegen"
 version = "0.66.0"
-source = "git+https://github.com/bytecodealliance/wasmtime?rev=dd098656111396afa58e90084a705744e836bf10#dd098656111396afa58e90084a705744e836bf10"
+source = "git+https://github.com/bytecodealliance/wasmtime?rev=026fb8d388964c7c1bace7019c4fe0d63c584560#026fb8d388964c7c1bace7019c4fe0d63c584560"
 dependencies = [
  "byteorder",
  "cranelift-bforest",
  "cranelift-codegen-meta",
  "cranelift-codegen-shared",
  "cranelift-entity 0.66.0",
  "log",
  "regalloc",
  "smallvec",
  "target-lexicon 0.10.0",
  "thiserror",
 ]
 
 [[package]]
 name = "cranelift-codegen-meta"
 version = "0.66.0"
-source = "git+https://github.com/bytecodealliance/wasmtime?rev=dd098656111396afa58e90084a705744e836bf10#dd098656111396afa58e90084a705744e836bf10"
+source = "git+https://github.com/bytecodealliance/wasmtime?rev=026fb8d388964c7c1bace7019c4fe0d63c584560#026fb8d388964c7c1bace7019c4fe0d63c584560"
 dependencies = [
  "cranelift-codegen-shared",
  "cranelift-entity 0.66.0",
 ]
 
 [[package]]
 name = "cranelift-codegen-shared"
 version = "0.66.0"
-source = "git+https://github.com/bytecodealliance/wasmtime?rev=dd098656111396afa58e90084a705744e836bf10#dd098656111396afa58e90084a705744e836bf10"
+source = "git+https://github.com/bytecodealliance/wasmtime?rev=026fb8d388964c7c1bace7019c4fe0d63c584560#026fb8d388964c7c1bace7019c4fe0d63c584560"
 
 [[package]]
 name = "cranelift-entity"
 version = "0.41.0"
 source = "git+https://github.com/PLSysSec/lucet_sandbox_compiler?rev=6594bb9dfab7e67eb6eb2fefbc66ab7c491ce730#6594bb9dfab7e67eb6eb2fefbc66ab7c491ce730"
 
 [[package]]
 name = "cranelift-entity"
 version = "0.66.0"
-source = "git+https://github.com/bytecodealliance/wasmtime?rev=dd098656111396afa58e90084a705744e836bf10#dd098656111396afa58e90084a705744e836bf10"
+source = "git+https://github.com/bytecodealliance/wasmtime?rev=026fb8d388964c7c1bace7019c4fe0d63c584560#026fb8d388964c7c1bace7019c4fe0d63c584560"
 
 [[package]]
 name = "cranelift-frontend"
 version = "0.66.0"
-source = "git+https://github.com/bytecodealliance/wasmtime?rev=dd098656111396afa58e90084a705744e836bf10#dd098656111396afa58e90084a705744e836bf10"
+source = "git+https://github.com/bytecodealliance/wasmtime?rev=026fb8d388964c7c1bace7019c4fe0d63c584560#026fb8d388964c7c1bace7019c4fe0d63c584560"
 dependencies = [
  "cranelift-codegen",
  "log",
  "smallvec",
  "target-lexicon 0.10.0",
 ]
 
 [[package]]
 name = "cranelift-wasm"
 version = "0.66.0"
-source = "git+https://github.com/bytecodealliance/wasmtime?rev=dd098656111396afa58e90084a705744e836bf10#dd098656111396afa58e90084a705744e836bf10"
+source = "git+https://github.com/bytecodealliance/wasmtime?rev=026fb8d388964c7c1bace7019c4fe0d63c584560#026fb8d388964c7c1bace7019c4fe0d63c584560"
 dependencies = [
  "cranelift-codegen",
  "cranelift-entity 0.66.0",
  "cranelift-frontend",
  "log",
  "thiserror",
  "wasmparser 0.59.0",
 ]
--- a/Cargo.toml
+++ b/Cargo.toml
@@ -70,13 +70,13 @@ rlbox_lucet_sandbox = { git = "https://g
 nix = { git = "https://github.com/shravanrn/nix/", branch = "r0.13.1", rev="4af6c367603869a30fddb5ffb0aba2b9477ba92e" }
 spirv_cross = { git = "https://github.com/kvark/spirv_cross", branch = "wgpu3", rev = "20191ad2f370afd6d247edcb9ff9da32d3bedb9c" }
 # failure's backtrace feature might break our builds, see bug 1608157.
 failure = { git = "https://github.com/badboy/failure", rev = "64af847bc5fdcb6d2438bec8a6030812a80519a5" }
 failure_derive = { git = "https://github.com/badboy/failure", rev = "64af847bc5fdcb6d2438bec8a6030812a80519a5" }
 
 [patch.crates-io.cranelift-codegen]
 git = "https://github.com/bytecodealliance/wasmtime"
-rev = "dd098656111396afa58e90084a705744e836bf10"
+rev = "026fb8d388964c7c1bace7019c4fe0d63c584560"
 
 [patch.crates-io.cranelift-wasm]
 git = "https://github.com/bytecodealliance/wasmtime"
-rev = "dd098656111396afa58e90084a705744e836bf10"
+rev = "026fb8d388964c7c1bace7019c4fe0d63c584560"
--- a/third_party/rust/cranelift-codegen/.cargo-checksum.json
+++ b/third_party/rust/cranelift-codegen/.cargo-checksum.json
@@ -1,1 +1,1 @@
-{"files":{"Cargo.toml":"04bab37553829e4392c9d030df9b82a5518cee020c6987ba36d3a6c7830188b4","LICENSE":"268872b9816f90fd8e85db5a28d33f8150ebb8dd016653fb39ef1f94f2686bc5","README.md":"e5127227a7db4a8aa92fa6613ed71801025790e696bb41b0323fb7f3c6f7495a","build.rs":"afe67e345d21f9a137ecad473bb595a8b4983d5d435ca0505c91021954c215a7","src/abi.rs":"8922d75a807798945c64ee135f7f22c58e97d8412c6d5b6bf6c4e75c6823d308","src/binemit/memorysink.rs":"378cf70ad5114a8a056d642b0c2d42b4285fe6902855a43085e30575a67d8a4d","src/binemit/mod.rs":"38ec613f6dd8e4f4ffd05d5ce6c0a65d38f4d5c8ef3f44f69e5e68441e8c729a","src/binemit/relaxation.rs":"0547f1a33ea176b281d6f09d1bd7a253dcba895785008e61c114861f1a86307f","src/binemit/shrink.rs":"552d64dff3b044bca77f39891d0e39ee619f6ec0669bf9917132c97becea79b0","src/binemit/stackmap.rs":"106e022548c7dbd35c2f6bc2f8bc5131fc0550c7063daa9702f1151ef3f16108","src/bitset.rs":"ff667c19a63a6a9bcf06f99a46b6db839323f5d3d5cc5e7b00f1ab77d331fc77","src/cfg_printer.rs":"a4cd85ecb2c403b29dc3fc6c60ee7f97b6ed602e8ba88ec87accb988d009271e","src/constant_hash.rs":"8f53afb38891fbdab8553c7a89e61f0ce30947a22fb24ae84523c9a1ab025c3f","src/context.rs":"f3a82a9fb74706dd4e5f328f7f86e798c56071d1e0884c31ddfbdcef2a28f6dc","src/cursor.rs":"eaa0e4ea65bec30aa79e2fb62e89c713b1adec6eeddd5592237d7fcce47c5fa7","src/dbg.rs":"1898d94cff0975815eb348651702e95c8f2f63886501d3b7043ee75668480472","src/dce.rs":"b98545dbf5c8d0c4a33b2ec6cd905d6371fe843481ad608ff59b4a009fc9be19","src/divconst_magic_numbers.rs":"e7f8f46f3a25ed7155890e9d76c10f5dde9dc5bbcebb623c8166fa415abdd959","src/dominator_tree.rs":"b3a5c7837150390a78ade90807965dfcb8768a7e3ae9ee02f2e4a1ad8f3bafa9","src/flowgraph.rs":"71490e2f7a1ea905758a258b2bebe77f125302f446f9839dd60003fdafaef5fe","src/fx.rs":"8a5d07487906d8316a179e826fcd817a92a4860686256a6fd9d78ba47c63f330","src/inst_predicates.rs":"4c776b22b541d29ff6699dec19b2f7d9b14448b1c0a0a3dbf4aaf64d5fc6f5c2","src/ir/builder.rs":"3425957b118a0c40847ef7f473543baef5a24f0c7d8af198955180c8f297ee5a","src/ir/constant.rs":"9c42014b7182a89bc2387e13d3956bbbd98025f32a3abeb5d253d2ba56ad279c","src/ir/dfg.rs":"e803858c6cef60cec09a82d686a73715d0eb142ac96742023cd6112dcf87073a","src/ir/entities.rs":"f0b49b9c351b94703d6c878b564e53a30010c142c47effaf603ec4ade784686b","src/ir/extfunc.rs":"7fd50239108ac9891ceb8a3104878a143cc86a0904dabba0813c609b90d86f9a","src/ir/extname.rs":"977b2e380094e99cfdd080112bda709ca61a6d942e1e4c2015d39eaf3ea80f4c","src/ir/function.rs":"3034e03ac2e6bcf300b91c9df03e144550ff6c91ef76b105c48ccbc7a752401b","src/ir/globalvalue.rs":"2f3a54cc2ade91439536b02c46ce790c3634a386a4cc4d27d7da7ad929b8bb90","src/ir/heap.rs":"a59d3e5901412b53c0b53a8cdf10765ff5921de9c410ae9acea226c89827df3c","src/ir/immediates.rs":"2f5366e9cd9f7731fdf4d9038bdd3c9976ea6dce38626ede289b37580407da16","src/ir/instructions.rs":"29fc7629ed25421bdfcd9571bf9e227764b3100738c996e4dd2abd24c2c18d90","src/ir/jumptable.rs":"184fa640957e8b0e451dc594e4b348f9aff5fb5b54ab3d856ab19df25f4f3322","src/ir/layout.rs":"2956643a822e67a0c1196f8d3c81af11d0c0122b2d97427ce3ed0c57bb633cbf","src/ir/libcall.rs":"7c9255bdef9a16937d817a3bfd542be4c2734eea3c8b8a870ff411eac2efaad8","src/ir/memflags.rs":"dbcf3798ab66dc764b73fb7f139a621c54cc6bcc683f1f70a33ed7e8c3486bfd","src/ir/mod.rs":"5329068e89f79fe230f0530b14652c35b07ab8d8f4070742a7dde4a3d5dab531","src/ir/progpoint.rs":"a985a7fccde1e985ca24bf2344f16faa4cda7cffb30cb56bf27fabbb5727bc62","src/ir/sourceloc.rs":"67c66adace734645ddf311ecb22e975f20756e07c91e10f698a830cfc2cd08aa","src/ir/stackslot.rs":"f158471dd1f90ffc64465ad406db6ef8d9d2366ce5575ec0451ccb9ac76656ed","src/ir/table.rs":"dcc3b663a989b2b084402b08dc9a0e928dbd052e194a46a1886cc6f0cf1a5f2c","src/ir/trapcode.rs":"71c1f66c3202c966ad58a03bf0d58a236b1bdcc80e48e690925e7332e9299351","src/ir/types.rs":"dfd9470aa4325adc252eb7ebb2951a5b98d22d0dc31be482419f5cbbb74bf86d","src/ir/valueloc.rs":"628f292ee6b8375e07f360edaf3609b522fd4d7bea131fb8ad3cab237927e7ab","src/isa/aarch64/abi.rs":"440febb641645d6f7513ec78770c1aaaa3e5aefd0427988ead0c0b85b5cdbe33","src/isa/aarch64/inst/args.rs":"d8b74e8c8a2d834915ff52e152b5c97dc7c60ed00c9ee1d9a28acb292d3f684c","src/isa/aarch64/inst/emit.rs":"9b52f2d332b81137a267aaecb2844078586f0c429f0825f615496af1efc7076d","src/isa/aarch64/inst/emit_tests.rs":"008c279c066cf0a86c33939a27faffdf40512828f03ad8052c6814f51eaa13f6","src/isa/aarch64/inst/imms.rs":"ca353eabfdae7c1bdc35919b39ff8a88c8fb598fed3df629e258847c544dd535","src/isa/aarch64/inst/mod.rs":"3f88cb6fcaf46c5fe053c3ce812d45897d69389069b71d68be6894e8a9bf0576","src/isa/aarch64/inst/regs.rs":"2e3f52d48b5963a85a275823ee1fd8bc5debf8ee310c4e8cddc77d04f4da45ea","src/isa/aarch64/lower.rs":"2d5489c249d2af9d0d72ee590cbcb80592892dbbcfff424c48875c0a6abb6264","src/isa/aarch64/lower_inst.rs":"aee7afd17c441ae990afd51480b39432be9abfd62598ccde546013484d5e0b75","src/isa/aarch64/mod.rs":"1943690939e630dd6fc79631cd4f43368df7fa70e4247198c5eb2a7a67fcf54b","src/isa/arm32/abi.rs":"59abc42d75445f7f3335b035655083772e98e413ee58a72fc4e224620327b5ea","src/isa/arm32/binemit.rs":"eecd7296c27d2520db8e86dd462833ecf06afd33548b03ae676c02454cdd13c2","src/isa/arm32/enc_tables.rs":"e94b12af802de59484cab1124d2ac8a88d08433f6e1a476724ed0403f4b5967f","src/isa/arm32/mod.rs":"63a47a6def4eecc4527a1bd1207b4f08d533a5e17e79eda245ebc62e3c862185","src/isa/arm32/registers.rs":"100033c78e2a891ad90a2765137bd678f1d11ae4ba61974d1083106fa1324037","src/isa/arm32/settings.rs":"2314460f885c24f9571d640f9737a8e0b7d20ca02bcda1127f878fd3891c0529","src/isa/call_conv.rs":"45c510bbd16af9ba207f8f2c1591f32edf57ecbfc3673a8e9e76ccffcf88ccae","src/isa/constraints.rs":"296f473a95146a743ecb73d8d5908675be02e37607efd287f55322549dc25763","src/isa/enc_tables.rs":"382e714f9500afc292c563cb66d4c963d6787e58f197b1db242db7a099c22b9a","src/isa/encoding.rs":"22e21fdb8e15859c69e4f836bb61e1a82cd6838d093ce5fe641a90f16fb65c9e","src/isa/mod.rs":"572d6216f0e188b275d9f31f7930d40fa2b539a939c6ba459b3d8d3e1b10844b","src/isa/registers.rs":"61840d736b1943c3e54ac324db6f7de4f76170800f047dde267dcc9aa2d53e6a","src/isa/riscv/abi.rs":"aa60b701efcef417ee1262a95398343578dc1a30decc8e11044b74d41654ec51","src/isa/riscv/binemit.rs":"264d223da311d4482ebf2f55438b665c67b163058251bc78173c76ba983a31ef","src/isa/riscv/enc_tables.rs":"8491f2082b24c7dedeb7c36cfd913bf9aeaa0a4c8fc754166e9285f4ae002f40","src/isa/riscv/mod.rs":"03ee02848dbc3325a5ef38e66c05be571c380fbe4ca520b4f87c7572db228beb","src/isa/riscv/registers.rs":"6275ec3ef19195d16556c1856cb23095f25a80c31d6b429eaa749d549515a6d3","src/isa/riscv/settings.rs":"e3c063add822ca366e845f5a19d25b56635e828b157a37d29aca5355650e6a66","src/isa/stack.rs":"c391216fb8ee6566e3b14aa4bd83ba85aef2bd23422a9dca2c8c6f47016372e2","src/isa/test_utils.rs":"df889e5a4fe6d1069ca87a34ba6260e077de9b0839db5e5c5780f18983aaeeef","src/isa/unwind.rs":"dab61943d7ca89e099604df2a36dba3b8a661fcf7c10dc13e1257ff8f4890bb3","src/isa/unwind/systemv.rs":"f93c36a366470a54ce2af229eea5ef7c299d28b34093dd656f3c5ad87ea94386","src/isa/unwind/winx64.rs":"2b2cbf0803c7967ecb0159ec2c649b45070f9d79a4f2e425ba51e6017b8167a3","src/isa/x64/abi.rs":"e88088b1a66175a09062d7e2b7d0176ce295a67ecd3c9b09a31ac2f334cab062","src/isa/x64/inst/args.rs":"53a2fd64bc5738f4b43a68dac61e9de3123a6f5aa4fadfa21bdaede75b989eaf","src/isa/x64/inst/emit.rs":"1fc1f720f378687471560f2e747e8217523a7cb97f21351ab2a66a89bb505be7","src/isa/x64/inst/emit_tests.rs":"c154da3f178ca2b1396ea960c5e987c6b11b268bf2d9ee254b6b0565aaa31280","src/isa/x64/inst/mod.rs":"1d339fc04470cc0fc7ff18d7f4fde23ff4021e9ad99e5c4afc77827f25704634","src/isa/x64/inst/regs.rs":"87400ce16de570db0399522a991b10b579e533bb8d97763285a4590115e39428","src/isa/x64/lower.rs":"9199ccaff155597fc5e7ed77478f916fff766b92a959318fa32d145e928a6b18","src/isa/x64/mod.rs":"e6d762ec6d1e4d8dd94e43254a79df37419d9bfa64149efabfc8218c0a90c594","src/isa/x64/settings.rs":"8e318036aab3e2c94edfcbf87137325e5423c1c04e14a3fac9e3cc73cebfa6e1","src/isa/x86/abi.rs":"9b6f259585e9e048aa2fc3ecc6b4415ef2c465cd94f93617fdeba85598583759","src/isa/x86/binemit.rs":"fb5051471cd9c860455a0c1d74aec7d919d4c7229ada10222631c3694f9a091f","src/isa/x86/enc_tables.rs":"f8e9453eaa7b69b72a373741150db5c951415e7a3ad5c8f5319edadd1aa5cad0","src/isa/x86/mod.rs":"d22ab9590f1c93ac1b60ef8b264c3dc596a0a3d979914b711378b167fece15be","src/isa/x86/registers.rs":"1abbc1aa24c6fc4c7e610b6e840eab29046b821de08cf57fc05e2c2f665479c0","src/isa/x86/settings.rs":"d3e403db3507830f79bcc976c17340b57052cf1b50877fcf1a79549f2a054458","src/isa/x86/unwind.rs":"2fb77f98437c425b3c6438a9e964501568579ca47f74c1a7eba47ab59c7a5046","src/isa/x86/unwind/systemv.rs":"3b6a2534c2c560433646150549194d2af0b290a389760197fd4789e557b07bb5","src/isa/x86/unwind/winx64.rs":"a932f79615536c0cd313cde0f9bdf982815ba9700cc977526657085b24e59b06","src/iterators.rs":"d399a80bc65b97f7d650978e19086dcc1d280ac96d60628eac3d17eb363b0d71","src/legalizer/boundary.rs":"bd1480dde632dcaa777189f28e82a1736b4adb7173a23313970367f409d441cb","src/legalizer/call.rs":"be6074c64c1a00e5e81159dd94c8401fef62205b22c15e07e0c56cf922554d00","src/legalizer/globalvalue.rs":"a5d09ee41a04ba991d7f5d2d8d8c30a209748d38501a005e0ea568df2663cbb5","src/legalizer/heap.rs":"a6026d44c9ce31e0a21413c50581985dad1584700fde9dbab0b2cefafa5c9d14","src/legalizer/libcall.rs":"4f187c04acb41696bbb80abf0efc4a24b939205619fc6cc40aa8cff86ae1d84b","src/legalizer/mod.rs":"27f6c0d4d5938e096bbcd1777d6c07da50d0b7e9741559662f71c842bc6a850e","src/legalizer/split.rs":"697f08886dbf35fcc69eccc7b597986a58cc73ca7d3cf5d581fffc658a0dad33","src/legalizer/table.rs":"c36d03525312e3191aba8ee00c26a87c1ea200f9a9a0370f0cc84eeacff71786","src/lib.rs":"baac4bced5536908fd80a14a12b9b89bba9c3ea799d939949abdfaa0a8a46ea2","src/licm.rs":"75e94228c37a7d32cc9b0d51644439f9b1837768df67fd3de08ee43b8cdf8123","src/loop_analysis.rs":"4f23c08df9bc95195d68e9721a3a040c6192276ad33894c1225647034f01b23d","src/machinst/abi.rs":"2f2b743748cdbc8cfc85619bbb52471ae748b4d484e646f7972b6b28be0cc3d6","src/machinst/adapter.rs":"caf5fcde25b0f41b49d108e3da72f6d9e5dfa97e24d5171698cf9eba1d283399","src/machinst/blockorder.rs":"04387238c1855051a44f8faffb76983514251a031af7d1837224551b8f574b60","src/machinst/buffer.rs":"c50f9b009438dbc5feec51e1cc7c3f0455465c3f3d935cd2d72890a97b8b0bbc","src/machinst/compile.rs":"5a5de197ed2b3490c49fee1e3dbd0a9c03ee041f8c6ad1e9074c7485ed109e94","src/machinst/lower.rs":"e3734e521e52428850c4d7e7ba8e49caf4e27404232acf8d063bee114717d32a","src/machinst/mod.rs":"d6b6d2a87d338741684998fdc6b9848c79c3a94c23629c2031f460a1e267a52e","src/machinst/pretty_print.rs":"6076d9ae0ec48ada9e674ad46c25f48e502adb6b8049c6e1edbcb3b68bd37f87","src/machinst/vcode.rs":"288ec8cfe054134f22a0dbecf295947b3d389d81a830e9fde93cb29f862f8302","src/nan_canonicalization.rs":"dd853d0b1c1b5274513e9fb24b8beb8db877aca8fdfea5ceccbd1a80309c8842","src/partition_slice.rs":"861e778f887ea5d0841d730963565690fd8c298edddf08848d0d215ae5125eba","src/peepmatic.rs":"78b5fc63ea64356fb4ffc76a3df4663999e36ad1cbfed853609a401072900caf","src/postopt.rs":"ab74e2811909805d467d470da5e66879328c8f47db263422efedf3f1c449d8b2","src/predicates.rs":"d4fa993d8b3036ac9e19d1c1d8880ab5b33030fff0a38d65e2a24b9f9d3956c9","src/preopt.peepmatic":"8b6a6c0f4bf6dcf06df1cc30c467ac39e285ccd85f13f4bc76496f5fd6268a51","src/preopt.serialized":"a7a0968f221417caf91edf9ab9d1a993b8e1aaef009e9f26f477a64b5351de75","src/print_errors.rs":"075b74520f47070b839b43714f55a46a7cc2697b9b0f24a7162d481b7e46b7d2","src/redundant_reload_remover.rs":"2c72cc013f33e1257425592ef4ee2b9437ab3dc84d9759589c15fd217bde83a2","src/regalloc/affinity.rs":"ec5d688c24043a8aa72efcfbfddc14497cd9bab288c9d339e5c0150cdade2b1d","src/regalloc/branch_splitting.rs":"32e34197f84e30cff758f4db611a9c70dd587dd8d094729c34aa00303538c0d0","src/regalloc/coalescing.rs":"154842e7f380f2626c698283dbc5e0d5e7f0cc5d22b938e90312d17b71a8bb72","src/regalloc/coloring.rs":"ded1d8e531c38412fb19fe746fed65a6b6598819a29cd76c9b4bd5c4d0d6011a","src/regalloc/context.rs":"d85f86a8a79e7c939c0e696d30632ae3856001de75411828fc57c0b5b93e63ef","src/regalloc/diversion.rs":"2e474940b0c38610ca231faba7c7c3cfadf401a2f24247b6f3730ac862fce21f","src/regalloc/live_value_tracker.rs":"845dc3f43cc6b795fea51bf293e7c6ab4961d59ab6ca2670fcab7a2a9bd996be","src/regalloc/liveness.rs":"0b027b8e4444a715af1b93d594a293d2fd430ad06940da05b06a4750535e9652","src/regalloc/liverange.rs":"2e98802e90868051b53ddc8555db0ea98aabc77df7789df2a92627650a43227e","src/regalloc/mod.rs":"50399d6569687a87bf1481304aca42506d946e34465e38ca8093e06485ab5fb6","src/regalloc/pressure.rs":"8408213afe07d4532da699f6604aff111c7061d71b585a84c5ec8db31582314c","src/regalloc/register_set.rs":"c740d10a061c4b8527ce319842b519d743e93e64db53851360f9ca2c099fd652","src/regalloc/reload.rs":"2132bd4cf45ce60b7799277d36bda35c05064ee1c60798388b8f55a0668fca47","src/regalloc/safepoint.rs":"8695ff4bd3ef88f4476a24206163c3a17b2b99ecfccd23c9f1f4bc9dbae9e046","src/regalloc/solver.rs":"5ad745ce9075ae8ca742602411f260036df4598695a4f5f0905bd91efe2c69c9","src/regalloc/spilling.rs":"3b75be8be6568a091dd8a1fd174b099859c6e9969c03bd765b5fb50f52fcccb5","src/regalloc/virtregs.rs":"a01b5d3cb1753e344c6663dd73de00dd452d442990f89477610b22c86c9afdfd","src/remove_constant_phis.rs":"0e6c2cdce9229bf9a9275d4895d772b90370ed6b7dfb690e63c245c2a9f6c94d","src/result.rs":"7164a1b35f26aeb9a6eda79f773f64ecb97b80b50f5b01ea5d34b64361160cbd","src/scoped_hash_map.rs":"c8d0071ce7e19438e9995b5fca1ea0fca81234811943b06b344331f9742c3718","src/settings.rs":"58a7fe17dfcb6f9e1831fec5044967c8a9bf58ed2c57dcbdc8533764443c3beb","src/simple_gvn.rs":"1de1d0c0e028833350eda7186243f255c9db97fe04f0e6fa688b8a710caa78be","src/simple_preopt.rs":"cac21be7637415f54be27af6135c1cc777352146b47bf25ac8e0b30cf5ab4d44","src/stack_layout.rs":"41d35401faa171d9823e9c6e26c1337f9e16c6b8ba613f0cd98c3c0032930496","src/timing.rs":"bbff7ca6f6ab8ce2f5d1ee0ce5785d19c0b03b6bf7bf65f8c9a2de7883f88506","src/topo_order.rs":"c092ee7a44e5f14962501eafd4478dfb855ce66af15d9c94a9b244ea30d6e991","src/unreachable_code.rs":"baea08a55b1e7eb2379fa2c4bb5ed4f5a536a35eafcb377f8ab79dc41d14d3d4","src/value_label.rs":"e464557e5bab579773929fcfca843e553af201174da1a73460d199446abc7fc7","src/verifier/cssa.rs":"2590b0ecbc134bbedac50915ed9c9e054c89f81e455c7bc0f37d4ddf57a38d05","src/verifier/flags.rs":"233a4c6fb42e32d92bcbef4ec094a26aa79bdd25cb478847236b6ce5d88d3d54","src/verifier/liveness.rs":"b6ab6dfb1390cea8091b71a6f2fd629ee356987b6a0714e8773d7b0eb7fa889f","src/verifier/locations.rs":"2b4e62e1bb79551725414b5a77425c00e9ad56ad766d6293db1eb261b64f51f9","src/verifier/mod.rs":"b0054edb93ce7afbca6658ec3f54a83add2b3e4ea5026153c12f4e00d482cba9","src/write.rs":"d045e8269cd306c76d45925296517908a9cec3a5b3c736511c87f7bcbe6cde4f"},"package":null}
\ No newline at end of file
+{"files":{"Cargo.toml":"04bab37553829e4392c9d030df9b82a5518cee020c6987ba36d3a6c7830188b4","LICENSE":"268872b9816f90fd8e85db5a28d33f8150ebb8dd016653fb39ef1f94f2686bc5","README.md":"e5127227a7db4a8aa92fa6613ed71801025790e696bb41b0323fb7f3c6f7495a","build.rs":"afe67e345d21f9a137ecad473bb595a8b4983d5d435ca0505c91021954c215a7","src/abi.rs":"8922d75a807798945c64ee135f7f22c58e97d8412c6d5b6bf6c4e75c6823d308","src/binemit/memorysink.rs":"378cf70ad5114a8a056d642b0c2d42b4285fe6902855a43085e30575a67d8a4d","src/binemit/mod.rs":"38ec613f6dd8e4f4ffd05d5ce6c0a65d38f4d5c8ef3f44f69e5e68441e8c729a","src/binemit/relaxation.rs":"0547f1a33ea176b281d6f09d1bd7a253dcba895785008e61c114861f1a86307f","src/binemit/shrink.rs":"552d64dff3b044bca77f39891d0e39ee619f6ec0669bf9917132c97becea79b0","src/binemit/stackmap.rs":"106e022548c7dbd35c2f6bc2f8bc5131fc0550c7063daa9702f1151ef3f16108","src/bitset.rs":"ff667c19a63a6a9bcf06f99a46b6db839323f5d3d5cc5e7b00f1ab77d331fc77","src/cfg_printer.rs":"a4cd85ecb2c403b29dc3fc6c60ee7f97b6ed602e8ba88ec87accb988d009271e","src/constant_hash.rs":"8f53afb38891fbdab8553c7a89e61f0ce30947a22fb24ae84523c9a1ab025c3f","src/context.rs":"f3a82a9fb74706dd4e5f328f7f86e798c56071d1e0884c31ddfbdcef2a28f6dc","src/cursor.rs":"eaa0e4ea65bec30aa79e2fb62e89c713b1adec6eeddd5592237d7fcce47c5fa7","src/dbg.rs":"1898d94cff0975815eb348651702e95c8f2f63886501d3b7043ee75668480472","src/dce.rs":"b98545dbf5c8d0c4a33b2ec6cd905d6371fe843481ad608ff59b4a009fc9be19","src/divconst_magic_numbers.rs":"e7f8f46f3a25ed7155890e9d76c10f5dde9dc5bbcebb623c8166fa415abdd959","src/dominator_tree.rs":"b3a5c7837150390a78ade90807965dfcb8768a7e3ae9ee02f2e4a1ad8f3bafa9","src/flowgraph.rs":"71490e2f7a1ea905758a258b2bebe77f125302f446f9839dd60003fdafaef5fe","src/fx.rs":"8a5d07487906d8316a179e826fcd817a92a4860686256a6fd9d78ba47c63f330","src/inst_predicates.rs":"4c776b22b541d29ff6699dec19b2f7d9b14448b1c0a0a3dbf4aaf64d5fc6f5c2","src/ir/builder.rs":"3425957b118a0c40847ef7f473543baef5a24f0c7d8af198955180c8f297ee5a","src/ir/constant.rs":"9c42014b7182a89bc2387e13d3956bbbd98025f32a3abeb5d253d2ba56ad279c","src/ir/dfg.rs":"e803858c6cef60cec09a82d686a73715d0eb142ac96742023cd6112dcf87073a","src/ir/entities.rs":"f0b49b9c351b94703d6c878b564e53a30010c142c47effaf603ec4ade784686b","src/ir/extfunc.rs":"7fd50239108ac9891ceb8a3104878a143cc86a0904dabba0813c609b90d86f9a","src/ir/extname.rs":"977b2e380094e99cfdd080112bda709ca61a6d942e1e4c2015d39eaf3ea80f4c","src/ir/function.rs":"3034e03ac2e6bcf300b91c9df03e144550ff6c91ef76b105c48ccbc7a752401b","src/ir/globalvalue.rs":"2f3a54cc2ade91439536b02c46ce790c3634a386a4cc4d27d7da7ad929b8bb90","src/ir/heap.rs":"a59d3e5901412b53c0b53a8cdf10765ff5921de9c410ae9acea226c89827df3c","src/ir/immediates.rs":"2f5366e9cd9f7731fdf4d9038bdd3c9976ea6dce38626ede289b37580407da16","src/ir/instructions.rs":"29fc7629ed25421bdfcd9571bf9e227764b3100738c996e4dd2abd24c2c18d90","src/ir/jumptable.rs":"184fa640957e8b0e451dc594e4b348f9aff5fb5b54ab3d856ab19df25f4f3322","src/ir/layout.rs":"2956643a822e67a0c1196f8d3c81af11d0c0122b2d97427ce3ed0c57bb633cbf","src/ir/libcall.rs":"7c9255bdef9a16937d817a3bfd542be4c2734eea3c8b8a870ff411eac2efaad8","src/ir/memflags.rs":"dbcf3798ab66dc764b73fb7f139a621c54cc6bcc683f1f70a33ed7e8c3486bfd","src/ir/mod.rs":"5329068e89f79fe230f0530b14652c35b07ab8d8f4070742a7dde4a3d5dab531","src/ir/progpoint.rs":"a985a7fccde1e985ca24bf2344f16faa4cda7cffb30cb56bf27fabbb5727bc62","src/ir/sourceloc.rs":"67c66adace734645ddf311ecb22e975f20756e07c91e10f698a830cfc2cd08aa","src/ir/stackslot.rs":"f158471dd1f90ffc64465ad406db6ef8d9d2366ce5575ec0451ccb9ac76656ed","src/ir/table.rs":"dcc3b663a989b2b084402b08dc9a0e928dbd052e194a46a1886cc6f0cf1a5f2c","src/ir/trapcode.rs":"71c1f66c3202c966ad58a03bf0d58a236b1bdcc80e48e690925e7332e9299351","src/ir/types.rs":"dfd9470aa4325adc252eb7ebb2951a5b98d22d0dc31be482419f5cbbb74bf86d","src/ir/valueloc.rs":"628f292ee6b8375e07f360edaf3609b522fd4d7bea131fb8ad3cab237927e7ab","src/isa/aarch64/abi.rs":"7e84b3090f9608e8e575d24501198800006f0b3b8033d62391a6367fd02ab171","src/isa/aarch64/inst/args.rs":"d8b74e8c8a2d834915ff52e152b5c97dc7c60ed00c9ee1d9a28acb292d3f684c","src/isa/aarch64/inst/emit.rs":"9b52f2d332b81137a267aaecb2844078586f0c429f0825f615496af1efc7076d","src/isa/aarch64/inst/emit_tests.rs":"008c279c066cf0a86c33939a27faffdf40512828f03ad8052c6814f51eaa13f6","src/isa/aarch64/inst/imms.rs":"ca353eabfdae7c1bdc35919b39ff8a88c8fb598fed3df629e258847c544dd535","src/isa/aarch64/inst/mod.rs":"3f88cb6fcaf46c5fe053c3ce812d45897d69389069b71d68be6894e8a9bf0576","src/isa/aarch64/inst/regs.rs":"2e3f52d48b5963a85a275823ee1fd8bc5debf8ee310c4e8cddc77d04f4da45ea","src/isa/aarch64/lower.rs":"2d5489c249d2af9d0d72ee590cbcb80592892dbbcfff424c48875c0a6abb6264","src/isa/aarch64/lower_inst.rs":"aee7afd17c441ae990afd51480b39432be9abfd62598ccde546013484d5e0b75","src/isa/aarch64/mod.rs":"1943690939e630dd6fc79631cd4f43368df7fa70e4247198c5eb2a7a67fcf54b","src/isa/arm32/abi.rs":"59abc42d75445f7f3335b035655083772e98e413ee58a72fc4e224620327b5ea","src/isa/arm32/binemit.rs":"eecd7296c27d2520db8e86dd462833ecf06afd33548b03ae676c02454cdd13c2","src/isa/arm32/enc_tables.rs":"e94b12af802de59484cab1124d2ac8a88d08433f6e1a476724ed0403f4b5967f","src/isa/arm32/mod.rs":"63a47a6def4eecc4527a1bd1207b4f08d533a5e17e79eda245ebc62e3c862185","src/isa/arm32/registers.rs":"100033c78e2a891ad90a2765137bd678f1d11ae4ba61974d1083106fa1324037","src/isa/arm32/settings.rs":"2314460f885c24f9571d640f9737a8e0b7d20ca02bcda1127f878fd3891c0529","src/isa/call_conv.rs":"45c510bbd16af9ba207f8f2c1591f32edf57ecbfc3673a8e9e76ccffcf88ccae","src/isa/constraints.rs":"296f473a95146a743ecb73d8d5908675be02e37607efd287f55322549dc25763","src/isa/enc_tables.rs":"382e714f9500afc292c563cb66d4c963d6787e58f197b1db242db7a099c22b9a","src/isa/encoding.rs":"22e21fdb8e15859c69e4f836bb61e1a82cd6838d093ce5fe641a90f16fb65c9e","src/isa/mod.rs":"572d6216f0e188b275d9f31f7930d40fa2b539a939c6ba459b3d8d3e1b10844b","src/isa/registers.rs":"61840d736b1943c3e54ac324db6f7de4f76170800f047dde267dcc9aa2d53e6a","src/isa/riscv/abi.rs":"aa60b701efcef417ee1262a95398343578dc1a30decc8e11044b74d41654ec51","src/isa/riscv/binemit.rs":"264d223da311d4482ebf2f55438b665c67b163058251bc78173c76ba983a31ef","src/isa/riscv/enc_tables.rs":"8491f2082b24c7dedeb7c36cfd913bf9aeaa0a4c8fc754166e9285f4ae002f40","src/isa/riscv/mod.rs":"03ee02848dbc3325a5ef38e66c05be571c380fbe4ca520b4f87c7572db228beb","src/isa/riscv/registers.rs":"6275ec3ef19195d16556c1856cb23095f25a80c31d6b429eaa749d549515a6d3","src/isa/riscv/settings.rs":"e3c063add822ca366e845f5a19d25b56635e828b157a37d29aca5355650e6a66","src/isa/stack.rs":"c391216fb8ee6566e3b14aa4bd83ba85aef2bd23422a9dca2c8c6f47016372e2","src/isa/test_utils.rs":"df889e5a4fe6d1069ca87a34ba6260e077de9b0839db5e5c5780f18983aaeeef","src/isa/unwind.rs":"dab61943d7ca89e099604df2a36dba3b8a661fcf7c10dc13e1257ff8f4890bb3","src/isa/unwind/systemv.rs":"f93c36a366470a54ce2af229eea5ef7c299d28b34093dd656f3c5ad87ea94386","src/isa/unwind/winx64.rs":"2b2cbf0803c7967ecb0159ec2c649b45070f9d79a4f2e425ba51e6017b8167a3","src/isa/x64/abi.rs":"93976291072d09d9c363468cce2d35b36363d33c5ddae0d8e6adb4064993e541","src/isa/x64/inst/args.rs":"b77b608f79656ff4af7f6e6f20d2c56798b38342e6cc0ce661fab4ecf8eab249","src/isa/x64/inst/emit.rs":"fcd1cceb0174ed950609da08be659cb75d39e8c317504b6f372a276ac4f12112","src/isa/x64/inst/emit_tests.rs":"c154da3f178ca2b1396ea960c5e987c6b11b268bf2d9ee254b6b0565aaa31280","src/isa/x64/inst/mod.rs":"5467890c4b66fb17db2fdd7684b802d9c733d19909a1df38aac1a1c3de2bab15","src/isa/x64/inst/regs.rs":"87400ce16de570db0399522a991b10b579e533bb8d97763285a4590115e39428","src/isa/x64/lower.rs":"37780ea7c50d1c34d1f4e7d9b1949a120d8b9604c3682d32205d1bf88fcfb88a","src/isa/x64/mod.rs":"e6d762ec6d1e4d8dd94e43254a79df37419d9bfa64149efabfc8218c0a90c594","src/isa/x64/settings.rs":"8e318036aab3e2c94edfcbf87137325e5423c1c04e14a3fac9e3cc73cebfa6e1","src/isa/x86/abi.rs":"9b6f259585e9e048aa2fc3ecc6b4415ef2c465cd94f93617fdeba85598583759","src/isa/x86/binemit.rs":"fb5051471cd9c860455a0c1d74aec7d919d4c7229ada10222631c3694f9a091f","src/isa/x86/enc_tables.rs":"f8e9453eaa7b69b72a373741150db5c951415e7a3ad5c8f5319edadd1aa5cad0","src/isa/x86/mod.rs":"d22ab9590f1c93ac1b60ef8b264c3dc596a0a3d979914b711378b167fece15be","src/isa/x86/registers.rs":"1abbc1aa24c6fc4c7e610b6e840eab29046b821de08cf57fc05e2c2f665479c0","src/isa/x86/settings.rs":"d3e403db3507830f79bcc976c17340b57052cf1b50877fcf1a79549f2a054458","src/isa/x86/unwind.rs":"2fb77f98437c425b3c6438a9e964501568579ca47f74c1a7eba47ab59c7a5046","src/isa/x86/unwind/systemv.rs":"3b6a2534c2c560433646150549194d2af0b290a389760197fd4789e557b07bb5","src/isa/x86/unwind/winx64.rs":"a932f79615536c0cd313cde0f9bdf982815ba9700cc977526657085b24e59b06","src/iterators.rs":"d399a80bc65b97f7d650978e19086dcc1d280ac96d60628eac3d17eb363b0d71","src/legalizer/boundary.rs":"bd1480dde632dcaa777189f28e82a1736b4adb7173a23313970367f409d441cb","src/legalizer/call.rs":"be6074c64c1a00e5e81159dd94c8401fef62205b22c15e07e0c56cf922554d00","src/legalizer/globalvalue.rs":"a5d09ee41a04ba991d7f5d2d8d8c30a209748d38501a005e0ea568df2663cbb5","src/legalizer/heap.rs":"a6026d44c9ce31e0a21413c50581985dad1584700fde9dbab0b2cefafa5c9d14","src/legalizer/libcall.rs":"4f187c04acb41696bbb80abf0efc4a24b939205619fc6cc40aa8cff86ae1d84b","src/legalizer/mod.rs":"27f6c0d4d5938e096bbcd1777d6c07da50d0b7e9741559662f71c842bc6a850e","src/legalizer/split.rs":"697f08886dbf35fcc69eccc7b597986a58cc73ca7d3cf5d581fffc658a0dad33","src/legalizer/table.rs":"c36d03525312e3191aba8ee00c26a87c1ea200f9a9a0370f0cc84eeacff71786","src/lib.rs":"baac4bced5536908fd80a14a12b9b89bba9c3ea799d939949abdfaa0a8a46ea2","src/licm.rs":"75e94228c37a7d32cc9b0d51644439f9b1837768df67fd3de08ee43b8cdf8123","src/loop_analysis.rs":"4f23c08df9bc95195d68e9721a3a040c6192276ad33894c1225647034f01b23d","src/machinst/abi.rs":"9183152cf9220ee8373b82e4d6af2148317a0a2c4a38670e1904a5c3391ce98e","src/machinst/adapter.rs":"caf5fcde25b0f41b49d108e3da72f6d9e5dfa97e24d5171698cf9eba1d283399","src/machinst/blockorder.rs":"04387238c1855051a44f8faffb76983514251a031af7d1837224551b8f574b60","src/machinst/buffer.rs":"c50f9b009438dbc5feec51e1cc7c3f0455465c3f3d935cd2d72890a97b8b0bbc","src/machinst/compile.rs":"5a5de197ed2b3490c49fee1e3dbd0a9c03ee041f8c6ad1e9074c7485ed109e94","src/machinst/lower.rs":"570a5c62b65b80b203cf95fdbf689f3e4b7185a058523b2cb7913d46c9f74bf3","src/machinst/mod.rs":"d6b6d2a87d338741684998fdc6b9848c79c3a94c23629c2031f460a1e267a52e","src/machinst/pretty_print.rs":"6076d9ae0ec48ada9e674ad46c25f48e502adb6b8049c6e1edbcb3b68bd37f87","src/machinst/vcode.rs":"288ec8cfe054134f22a0dbecf295947b3d389d81a830e9fde93cb29f862f8302","src/nan_canonicalization.rs":"dd853d0b1c1b5274513e9fb24b8beb8db877aca8fdfea5ceccbd1a80309c8842","src/partition_slice.rs":"861e778f887ea5d0841d730963565690fd8c298edddf08848d0d215ae5125eba","src/peepmatic.rs":"78b5fc63ea64356fb4ffc76a3df4663999e36ad1cbfed853609a401072900caf","src/postopt.rs":"ab74e2811909805d467d470da5e66879328c8f47db263422efedf3f1c449d8b2","src/predicates.rs":"d4fa993d8b3036ac9e19d1c1d8880ab5b33030fff0a38d65e2a24b9f9d3956c9","src/preopt.peepmatic":"8b6a6c0f4bf6dcf06df1cc30c467ac39e285ccd85f13f4bc76496f5fd6268a51","src/preopt.serialized":"a7a0968f221417caf91edf9ab9d1a993b8e1aaef009e9f26f477a64b5351de75","src/print_errors.rs":"075b74520f47070b839b43714f55a46a7cc2697b9b0f24a7162d481b7e46b7d2","src/redundant_reload_remover.rs":"2c72cc013f33e1257425592ef4ee2b9437ab3dc84d9759589c15fd217bde83a2","src/regalloc/affinity.rs":"ec5d688c24043a8aa72efcfbfddc14497cd9bab288c9d339e5c0150cdade2b1d","src/regalloc/branch_splitting.rs":"32e34197f84e30cff758f4db611a9c70dd587dd8d094729c34aa00303538c0d0","src/regalloc/coalescing.rs":"154842e7f380f2626c698283dbc5e0d5e7f0cc5d22b938e90312d17b71a8bb72","src/regalloc/coloring.rs":"ded1d8e531c38412fb19fe746fed65a6b6598819a29cd76c9b4bd5c4d0d6011a","src/regalloc/context.rs":"d85f86a8a79e7c939c0e696d30632ae3856001de75411828fc57c0b5b93e63ef","src/regalloc/diversion.rs":"2e474940b0c38610ca231faba7c7c3cfadf401a2f24247b6f3730ac862fce21f","src/regalloc/live_value_tracker.rs":"845dc3f43cc6b795fea51bf293e7c6ab4961d59ab6ca2670fcab7a2a9bd996be","src/regalloc/liveness.rs":"0b027b8e4444a715af1b93d594a293d2fd430ad06940da05b06a4750535e9652","src/regalloc/liverange.rs":"2e98802e90868051b53ddc8555db0ea98aabc77df7789df2a92627650a43227e","src/regalloc/mod.rs":"50399d6569687a87bf1481304aca42506d946e34465e38ca8093e06485ab5fb6","src/regalloc/pressure.rs":"8408213afe07d4532da699f6604aff111c7061d71b585a84c5ec8db31582314c","src/regalloc/register_set.rs":"c740d10a061c4b8527ce319842b519d743e93e64db53851360f9ca2c099fd652","src/regalloc/reload.rs":"2132bd4cf45ce60b7799277d36bda35c05064ee1c60798388b8f55a0668fca47","src/regalloc/safepoint.rs":"8695ff4bd3ef88f4476a24206163c3a17b2b99ecfccd23c9f1f4bc9dbae9e046","src/regalloc/solver.rs":"5ad745ce9075ae8ca742602411f260036df4598695a4f5f0905bd91efe2c69c9","src/regalloc/spilling.rs":"3b75be8be6568a091dd8a1fd174b099859c6e9969c03bd765b5fb50f52fcccb5","src/regalloc/virtregs.rs":"a01b5d3cb1753e344c6663dd73de00dd452d442990f89477610b22c86c9afdfd","src/remove_constant_phis.rs":"0e6c2cdce9229bf9a9275d4895d772b90370ed6b7dfb690e63c245c2a9f6c94d","src/result.rs":"7164a1b35f26aeb9a6eda79f773f64ecb97b80b50f5b01ea5d34b64361160cbd","src/scoped_hash_map.rs":"c8d0071ce7e19438e9995b5fca1ea0fca81234811943b06b344331f9742c3718","src/settings.rs":"58a7fe17dfcb6f9e1831fec5044967c8a9bf58ed2c57dcbdc8533764443c3beb","src/simple_gvn.rs":"1de1d0c0e028833350eda7186243f255c9db97fe04f0e6fa688b8a710caa78be","src/simple_preopt.rs":"cac21be7637415f54be27af6135c1cc777352146b47bf25ac8e0b30cf5ab4d44","src/stack_layout.rs":"41d35401faa171d9823e9c6e26c1337f9e16c6b8ba613f0cd98c3c0032930496","src/timing.rs":"bbff7ca6f6ab8ce2f5d1ee0ce5785d19c0b03b6bf7bf65f8c9a2de7883f88506","src/topo_order.rs":"c092ee7a44e5f14962501eafd4478dfb855ce66af15d9c94a9b244ea30d6e991","src/unreachable_code.rs":"baea08a55b1e7eb2379fa2c4bb5ed4f5a536a35eafcb377f8ab79dc41d14d3d4","src/value_label.rs":"e464557e5bab579773929fcfca843e553af201174da1a73460d199446abc7fc7","src/verifier/cssa.rs":"2590b0ecbc134bbedac50915ed9c9e054c89f81e455c7bc0f37d4ddf57a38d05","src/verifier/flags.rs":"233a4c6fb42e32d92bcbef4ec094a26aa79bdd25cb478847236b6ce5d88d3d54","src/verifier/liveness.rs":"b6ab6dfb1390cea8091b71a6f2fd629ee356987b6a0714e8773d7b0eb7fa889f","src/verifier/locations.rs":"2b4e62e1bb79551725414b5a77425c00e9ad56ad766d6293db1eb261b64f51f9","src/verifier/mod.rs":"b0054edb93ce7afbca6658ec3f54a83add2b3e4ea5026153c12f4e00d482cba9","src/write.rs":"d045e8269cd306c76d45925296517908a9cec3a5b3c736511c87f7bcbe6cde4f"},"package":null}
\ No newline at end of file
--- a/third_party/rust/cranelift-codegen/src/isa/aarch64/abi.rs
+++ b/third_party/rust/cranelift-codegen/src/isa/aarch64/abi.rs
@@ -108,19 +108,19 @@ use regalloc::{RealReg, Reg, RegClass, S
 
 use core::mem;
 use log::{debug, trace};
 
 /// A location for an argument or return value.
 #[derive(Clone, Copy, Debug)]
 enum ABIArg {
     /// In a real register.
-    Reg(RealReg, ir::Type),
+    Reg(RealReg, ir::Type, ir::ArgumentExtension),
     /// Arguments only: on stack, at given offset from SP at entry.
-    Stack(i64, ir::Type),
+    Stack(i64, ir::Type, ir::ArgumentExtension),
 }
 
 /// AArch64 ABI information shared between body (callee) and caller.
 struct ABISig {
     /// Argument locations (regs or stack slots). Stack offsets are relative to
     /// SP on entry to function.
     args: Vec<ABIArg>,
     /// Return-value locations. Stack offsets are relative to the return-area
@@ -182,23 +182,25 @@ static BALDRDASH_JIT_CALLEE_SAVED_FPU: &
 fn try_fill_baldrdash_reg(call_conv: isa::CallConv, param: &ir::AbiParam) -> Option<ABIArg> {
     if call_conv.extends_baldrdash() {
         match &param.purpose {
             &ir::ArgumentPurpose::VMContext => {
                 // This is SpiderMonkey's `WasmTlsReg`.
                 Some(ABIArg::Reg(
                     xreg(BALDRDASH_TLS_REG).to_real_reg(),
                     ir::types::I64,
+                    param.extension,
                 ))
             }
             &ir::ArgumentPurpose::SignatureId => {
                 // This is SpiderMonkey's `WasmTableCallSigReg`.
                 Some(ABIArg::Reg(
                     xreg(BALDRDASH_SIG_REG).to_real_reg(),
                     ir::types::I64,
+                    param.extension,
                 ))
             }
             _ => None,
         }
     } else {
         None
     }
 }
@@ -274,41 +276,57 @@ fn compute_arg_locs(
             assert!(intreg);
             ret.push(param);
         } else if *next_reg < max_reg_vals {
             let reg = if intreg {
                 xreg(*next_reg)
             } else {
                 vreg(*next_reg)
             };
-            ret.push(ABIArg::Reg(reg.to_real_reg(), param.value_type));
+            ret.push(ABIArg::Reg(
+                reg.to_real_reg(),
+                param.value_type,
+                param.extension,
+            ));
             *next_reg += 1;
         } else {
             // Compute size. Every arg takes a minimum slot of 8 bytes. (16-byte
             // stack alignment happens separately after all args.)
             let size = (ty_bits(param.value_type) / 8) as u64;
             let size = std::cmp::max(size, 8);
             // Align.
             debug_assert!(size.is_power_of_two());
             next_stack = (next_stack + size - 1) & !(size - 1);
-            ret.push(ABIArg::Stack(next_stack as i64, param.value_type));
+            ret.push(ABIArg::Stack(
+                next_stack as i64,
+                param.value_type,
+                param.extension,
+            ));
             next_stack += size;
         }
     }
 
     if args_or_rets == ArgsOrRets::Rets && is_baldrdash {
         ret.reverse();
     }
 
     let extra_arg = if add_ret_area_ptr {
         debug_assert!(args_or_rets == ArgsOrRets::Args);
         if next_xreg < max_reg_vals {
-            ret.push(ABIArg::Reg(xreg(next_xreg).to_real_reg(), I64));
+            ret.push(ABIArg::Reg(
+                xreg(next_xreg).to_real_reg(),
+                I64,
+                ir::ArgumentExtension::None,
+            ));
         } else {
-            ret.push(ABIArg::Stack(next_stack as i64, I64));
+            ret.push(ABIArg::Stack(
+                next_stack as i64,
+                I64,
+                ir::ArgumentExtension::None,
+            ));
             next_stack += 8;
         }
         Some(ret.len() - 1)
     } else {
         None
     };
 
     next_stack = (next_stack + 15) & !15;
@@ -486,17 +504,17 @@ fn gen_stack_limit(f: &ir::Function, abi
 
 fn get_special_purpose_param_register(
     f: &ir::Function,
     abi: &ABISig,
     purpose: ir::ArgumentPurpose,
 ) -> Option<Reg> {
     let idx = f.signature.special_param_index(purpose)?;
     match abi.args[idx] {
-        ABIArg::Reg(reg, _) => Some(reg.to_reg()),
+        ABIArg::Reg(reg, ..) => Some(reg.to_reg()),
         ABIArg::Stack(..) => None,
     }
 }
 
 impl AArch64ABIBody {
     /// Create a new body ABI instance.
     pub fn new(f: &ir::Function, flags: settings::Flags) -> CodegenResult<Self> {
         debug!("AArch64 ABI: func signature {:?}", f.signature);
@@ -861,27 +879,27 @@ impl ABIBody for AArch64ABIBody {
 
     fn flags(&self) -> &settings::Flags {
         &self.flags
     }
 
     fn liveins(&self) -> Set<RealReg> {
         let mut set: Set<RealReg> = Set::empty();
         for &arg in &self.sig.args {
-            if let ABIArg::Reg(r, _) = arg {
+            if let ABIArg::Reg(r, ..) = arg {
                 set.insert(r);
             }
         }
         set
     }
 
     fn liveouts(&self) -> Set<RealReg> {
         let mut set: Set<RealReg> = Set::empty();
         for &ret in &self.sig.rets {
-            if let ABIArg::Reg(r, _) = ret {
+            if let ABIArg::Reg(r, ..) = ret {
                 set.insert(r);
             }
         }
         set
     }
 
     fn num_args(&self) -> usize {
         self.sig.args.len()
@@ -892,18 +910,20 @@ impl ABIBody for AArch64ABIBody {
     }
 
     fn num_stackslots(&self) -> usize {
         self.stackslots.len()
     }
 
     fn gen_copy_arg_to_reg(&self, idx: usize, into_reg: Writable<Reg>) -> Inst {
         match &self.sig.args[idx] {
-            &ABIArg::Reg(r, ty) => Inst::gen_move(into_reg, r.to_reg(), ty),
-            &ABIArg::Stack(off, ty) => load_stack(
+            // Extension mode doesn't matter (we're copying out, not in; we
+            // ignore high bits by convention).
+            &ABIArg::Reg(r, ty, _) => Inst::gen_move(into_reg, r.to_reg(), ty),
+            &ABIArg::Stack(off, ty, _) => load_stack(
                 MemArg::FPOffset(self.fp_to_arg_offset() + off, ty),
                 into_reg,
                 ty,
             ),
         }
     }
 
     fn gen_retval_area_setup(&self) -> Option<Inst> {
@@ -916,25 +936,20 @@ impl ABIBody for AArch64ABIBody {
             );
             Some(inst)
         } else {
             trace!("gen_retval_area_setup: not needed");
             None
         }
     }
 
-    fn gen_copy_reg_to_retval(
-        &self,
-        idx: usize,
-        from_reg: Writable<Reg>,
-        ext: ArgumentExtension,
-    ) -> Vec<Inst> {
+    fn gen_copy_reg_to_retval(&self, idx: usize, from_reg: Writable<Reg>) -> Vec<Inst> {
         let mut ret = Vec::new();
         match &self.sig.rets[idx] {
-            &ABIArg::Reg(r, ty) => {
+            &ABIArg::Reg(r, ty, ext) => {
                 let from_bits = ty_bits(ty) as u8;
                 let dest_reg = Writable::from_reg(r.to_reg());
                 match (ext, from_bits) {
                     (ArgumentExtension::Uext, n) if n < 64 => {
                         ret.push(Inst::Extend {
                             rd: dest_reg,
                             rn: from_reg.to_reg(),
                             signed: false,
@@ -949,17 +964,17 @@ impl ABIBody for AArch64ABIBody {
                             signed: true,
                             from_bits,
                             to_bits: 64,
                         });
                     }
                     _ => ret.push(Inst::gen_move(dest_reg, from_reg.to_reg(), ty)),
                 };
             }
-            &ABIArg::Stack(off, ty) => {
+            &ABIArg::Stack(off, ty, ext) => {
                 let from_bits = ty_bits(ty) as u8;
                 // Trash the from_reg; it should be its last use.
                 match (ext, from_bits) {
                     (ArgumentExtension::Uext, n) if n < 64 => {
                         ret.push(Inst::Extend {
                             rd: from_reg,
                             rn: from_reg.to_reg(),
                             signed: false,
@@ -1359,26 +1374,26 @@ pub struct AArch64ABICall {
     opcode: ir::Opcode,
 }
 
 fn abisig_to_uses_and_defs(sig: &ABISig) -> (Vec<Reg>, Vec<Writable<Reg>>) {
     // Compute uses: all arg regs.
     let mut uses = Vec::new();
     for arg in &sig.args {
         match arg {
-            &ABIArg::Reg(reg, _) => uses.push(reg.to_reg()),
+            &ABIArg::Reg(reg, ..) => uses.push(reg.to_reg()),
             _ => {}
         }
     }
 
     // Compute defs: all retval regs, and all caller-save (clobbered) regs.
     let mut defs = get_caller_saves(sig.call_conv);
     for ret in &sig.rets {
         match ret {
-            &ABIArg::Reg(reg, _) => defs.push(Writable::from_reg(reg.to_reg())),
+            &ABIArg::Reg(reg, ..) => defs.push(Writable::from_reg(reg.to_reg())),
             _ => {}
         }
     }
 
     (uses, defs)
 }
 
 impl AArch64ABICall {
@@ -1464,36 +1479,75 @@ impl ABICall for AArch64ABICall {
 
     fn emit_copy_reg_to_arg<C: LowerCtx<I = Self::I>>(
         &self,
         ctx: &mut C,
         idx: usize,
         from_reg: Reg,
     ) {
         match &self.sig.args[idx] {
-            &ABIArg::Reg(reg, ty) => ctx.emit(Inst::gen_move(
-                Writable::from_reg(reg.to_reg()),
-                from_reg,
-                ty,
-            )),
-            &ABIArg::Stack(off, ty) => {
+            &ABIArg::Reg(reg, ty, ext)
+                if ext != ir::ArgumentExtension::None && ty_bits(ty) < 64 =>
+            {
+                assert_eq!(RegClass::I64, reg.get_class());
+                let signed = match ext {
+                    ir::ArgumentExtension::Uext => false,
+                    ir::ArgumentExtension::Sext => true,
+                    _ => unreachable!(),
+                };
+                ctx.emit(Inst::Extend {
+                    rd: Writable::from_reg(reg.to_reg()),
+                    rn: from_reg,
+                    signed,
+                    from_bits: ty_bits(ty) as u8,
+                    to_bits: 64,
+                });
+            }
+            &ABIArg::Reg(reg, ty, _) => {
+                ctx.emit(Inst::gen_move(
+                    Writable::from_reg(reg.to_reg()),
+                    from_reg,
+                    ty,
+                ));
+            }
+            &ABIArg::Stack(off, ty, ext) => {
+                if ext != ir::ArgumentExtension::None && ty_bits(ty) < 64 {
+                    assert_eq!(RegClass::I64, from_reg.get_class());
+                    let signed = match ext {
+                        ir::ArgumentExtension::Uext => false,
+                        ir::ArgumentExtension::Sext => true,
+                        _ => unreachable!(),
+                    };
+                    // Extend in place in the source register. Our convention is to
+                    // treat high bits as undefined for values in registers, so this
+                    // is safe, even for an argument that is nominally read-only.
+                    ctx.emit(Inst::Extend {
+                        rd: Writable::from_reg(from_reg),
+                        rn: from_reg,
+                        signed,
+                        from_bits: ty_bits(ty) as u8,
+                        to_bits: 64,
+                    });
+                }
                 ctx.emit(store_stack(MemArg::SPOffset(off, ty), from_reg, ty))
             }
         }
     }
 
     fn emit_copy_retval_to_reg<C: LowerCtx<I = Self::I>>(
         &self,
         ctx: &mut C,
         idx: usize,
         into_reg: Writable<Reg>,
     ) {
         match &self.sig.rets[idx] {
-            &ABIArg::Reg(reg, ty) => ctx.emit(Inst::gen_move(into_reg, reg.to_reg(), ty)),
-            &ABIArg::Stack(off, ty) => {
+            // Extension mode doesn't matter because we're copying out, not in,
+            // and we ignore high bits in our own registers by convention.
+            &ABIArg::Reg(reg, ty, _) => ctx.emit(Inst::gen_move(into_reg, reg.to_reg(), ty)),
+            &ABIArg::Stack(off, ty, _) => {
                 let ret_area_base = self.sig.stack_arg_space;
                 ctx.emit(load_stack(
                     MemArg::SPOffset(off + ret_area_base, ty),
                     into_reg,
                     ty,
                 ));
             }
         }
--- a/third_party/rust/cranelift-codegen/src/isa/x64/abi.rs
+++ b/third_party/rust/cranelift-codegen/src/isa/x64/abi.rs
@@ -18,18 +18,18 @@ use args::*;
 
 /// This is the limit for the size of argument and return-value areas on the
 /// stack. We place a reasonable limit here to avoid integer overflow issues
 /// with 32-bit arithmetic: for now, 128 MB.
 static STACK_ARG_RET_SIZE_LIMIT: u64 = 128 * 1024 * 1024;
 
 #[derive(Clone, Debug)]
 enum ABIArg {
-    Reg(RealReg, ir::Type),
-    Stack(i64, ir::Type),
+    Reg(RealReg, ir::Type, ir::ArgumentExtension),
+    Stack(i64, ir::Type, ir::ArgumentExtension),
 }
 
 /// X64 ABI information shared between body (callee) and caller.
 struct ABISig {
     /// Argument locations (regs or stack slots). Stack offsets are relative to
     /// SP on entry to function.
     args: Vec<ABIArg>,
     /// Return-value locations. Stack offsets are relative to the return-area
@@ -298,37 +298,37 @@ impl ABIBody for X64ABIBody {
     }
     fn num_stackslots(&self) -> usize {
         self.stack_slots.len()
     }
 
     fn liveins(&self) -> Set<RealReg> {
         let mut set: Set<RealReg> = Set::empty();
         for arg in &self.sig.args {
-            if let &ABIArg::Reg(r, _) = arg {
+            if let &ABIArg::Reg(r, ..) = arg {
                 set.insert(r);
             }
         }
         set
     }
 
     fn liveouts(&self) -> Set<RealReg> {
         let mut set: Set<RealReg> = Set::empty();
         for ret in &self.sig.rets {
-            if let &ABIArg::Reg(r, _) = ret {
+            if let &ABIArg::Reg(r, ..) = ret {
                 set.insert(r);
             }
         }
         set
     }
 
     fn gen_copy_arg_to_reg(&self, idx: usize, to_reg: Writable<Reg>) -> Inst {
         match &self.sig.args[idx] {
-            ABIArg::Reg(from_reg, ty) => Inst::gen_move(to_reg, from_reg.to_reg(), *ty),
-            &ABIArg::Stack(off, ty) => {
+            ABIArg::Reg(from_reg, ty, _) => Inst::gen_move(to_reg, from_reg.to_reg(), *ty),
+            &ABIArg::Stack(off, ty, _) => {
                 assert!(
                     self.fp_to_arg_offset() + off <= u32::max_value() as i64,
                     "large offset nyi"
                 );
                 load_stack(
                     Amode::imm_reg((self.fp_to_arg_offset() + off) as u32, regs::rbp()),
                     to_reg,
                     ty,
@@ -347,25 +347,20 @@ impl ABIBody for X64ABIBody {
             );
             Some(inst)
         } else {
             trace!("gen_retval_area_setup: not needed");
             None
         }
     }
 
-    fn gen_copy_reg_to_retval(
-        &self,
-        idx: usize,
-        from_reg: Writable<Reg>,
-        ext: ArgumentExtension,
-    ) -> Vec<Inst> {
+    fn gen_copy_reg_to_retval(&self, idx: usize, from_reg: Writable<Reg>) -> Vec<Inst> {
         let mut ret = Vec::new();
         match &self.sig.rets[idx] {
-            &ABIArg::Reg(r, ty) => {
+            &ABIArg::Reg(r, ty, ext) => {
                 let from_bits = ty.bits() as u8;
                 let ext_mode = match from_bits {
                     1 | 8 => Some(ExtMode::BQ),
                     16 => Some(ExtMode::WQ),
                     32 => Some(ExtMode::LQ),
                     64 | 128 => None,
                     _ => unreachable!(),
                 };
@@ -387,17 +382,17 @@ impl ABIBody for X64ABIBody {
                             dest_reg,
                             /* infallible load */ None,
                         ));
                     }
                     _ => ret.push(Inst::gen_move(dest_reg, from_reg.to_reg(), ty)),
                 };
             }
 
-            &ABIArg::Stack(off, ty) => {
+            &ABIArg::Stack(off, ty, ext) => {
                 let from_bits = ty.bits() as u8;
                 let ext_mode = match from_bits {
                     1 | 8 => Some(ExtMode::BQ),
                     16 => Some(ExtMode::WQ),
                     32 => Some(ExtMode::LQ),
                     64 => None,
                     _ => unreachable!(),
                 };
@@ -754,44 +749,52 @@ fn get_caller_saves(call_conv: CallConv)
     caller_saved
 }
 
 fn abisig_to_uses_and_defs(sig: &ABISig) -> (Vec<Reg>, Vec<Writable<Reg>>) {
     // Compute uses: all arg regs.
     let mut uses = Vec::new();
     for arg in &sig.args {
         match arg {
-            &ABIArg::Reg(reg, _) => uses.push(reg.to_reg()),
+            &ABIArg::Reg(reg, ..) => uses.push(reg.to_reg()),
             _ => {}
         }
     }
 
     // Compute defs: all retval regs, and all caller-save (clobbered) regs.
     let mut defs = get_caller_saves(sig.call_conv);
     for ret in &sig.rets {
         match ret {
-            &ABIArg::Reg(reg, _) => defs.push(Writable::from_reg(reg.to_reg())),
+            &ABIArg::Reg(reg, ..) => defs.push(Writable::from_reg(reg.to_reg())),
             _ => {}
         }
     }
 
     (uses, defs)
 }
 
 /// Try to fill a Baldrdash register, returning it if it was found.
 fn try_fill_baldrdash_reg(call_conv: CallConv, param: &ir::AbiParam) -> Option<ABIArg> {
     if call_conv.extends_baldrdash() {
         match &param.purpose {
             &ir::ArgumentPurpose::VMContext => {
                 // This is SpiderMonkey's `WasmTlsReg`.
-                Some(ABIArg::Reg(regs::r14().to_real_reg(), ir::types::I64))
+                Some(ABIArg::Reg(
+                    regs::r14().to_real_reg(),
+                    ir::types::I64,
+                    param.extension,
+                ))
             }
             &ir::ArgumentPurpose::SignatureId => {
                 // This is SpiderMonkey's `WasmTableCallSigReg`.
-                Some(ABIArg::Reg(regs::r10().to_real_reg(), ir::types::I64))
+                Some(ABIArg::Reg(
+                    regs::r10().to_real_reg(),
+                    ir::types::I64,
+                    param.extension,
+                ))
             }
             _ => None,
         }
     } else {
         None
     }
 }
 
@@ -868,41 +871,57 @@ fn compute_arg_locs(
                 .unwrap_or(true));
             (&mut next_vreg, candidate)
         };
 
         if let Some(param) = try_fill_baldrdash_reg(call_conv, param) {
             assert!(intreg);
             ret.push(param);
         } else if let Some(reg) = candidate {
-            ret.push(ABIArg::Reg(reg.to_real_reg(), param.value_type));
+            ret.push(ABIArg::Reg(
+                reg.to_real_reg(),
+                param.value_type,
+                param.extension,
+            ));
             *next_reg += 1;
         } else {
             // Compute size. Every arg takes a minimum slot of 8 bytes. (16-byte
             // stack alignment happens separately after all args.)
             let size = (param.value_type.bits() / 8) as u64;
             let size = std::cmp::max(size, 8);
             // Align.
             debug_assert!(size.is_power_of_two());
             next_stack = (next_stack + size - 1) & !(size - 1);
-            ret.push(ABIArg::Stack(next_stack as i64, param.value_type));
+            ret.push(ABIArg::Stack(
+                next_stack as i64,
+                param.value_type,
+                param.extension,
+            ));
             next_stack += size;
         }
     }
 
     if args_or_rets == ArgsOrRets::Rets && is_baldrdash {
         ret.reverse();
     }
 
     let extra_arg = if add_ret_area_ptr {
         debug_assert!(args_or_rets == ArgsOrRets::Args);
         if let Some(reg) = get_intreg_for_arg_systemv(&call_conv, next_gpr) {
-            ret.push(ABIArg::Reg(reg.to_real_reg(), ir::types::I64));
+            ret.push(ABIArg::Reg(
+                reg.to_real_reg(),
+                ir::types::I64,
+                ir::ArgumentExtension::None,
+            ));
         } else {
-            ret.push(ABIArg::Stack(next_stack as i64, ir::types::I64));
+            ret.push(ABIArg::Stack(
+                next_stack as i64,
+                ir::types::I64,
+                ir::ArgumentExtension::None,
+            ));
             next_stack += 8;
         }
         Some(ret.len() - 1)
     } else {
         None
     };
 
     next_stack = (next_stack + 15) & !15;
@@ -1121,22 +1140,84 @@ impl ABICall for X64ABICall {
 
     fn emit_copy_reg_to_arg<C: LowerCtx<I = Self::I>>(
         &self,
         ctx: &mut C,
         idx: usize,
         from_reg: Reg,
     ) {
         match &self.sig.args[idx] {
-            &ABIArg::Reg(reg, ty) => ctx.emit(Inst::gen_move(
+            &ABIArg::Reg(reg, ty, ext) if ext != ir::ArgumentExtension::None && ty.bits() < 64 => {
+                assert_eq!(RegClass::I64, reg.get_class());
+                let dest_reg = Writable::from_reg(reg.to_reg());
+                let ext_mode = match ty.bits() {
+                    1 | 8 => ExtMode::BQ,
+                    16 => ExtMode::WQ,
+                    32 => ExtMode::LQ,
+                    _ => unreachable!(),
+                };
+                match ext {
+                    ir::ArgumentExtension::Uext => {
+                        ctx.emit(Inst::movzx_rm_r(
+                            ext_mode,
+                            RegMem::reg(from_reg),
+                            dest_reg,
+                            /* infallible load */ None,
+                        ));
+                    }
+                    ir::ArgumentExtension::Sext => {
+                        ctx.emit(Inst::movsx_rm_r(
+                            ext_mode,
+                            RegMem::reg(from_reg),
+                            dest_reg,
+                            /* infallible load */ None,
+                        ));
+                    }
+                    _ => unreachable!(),
+                };
+            }
+            &ABIArg::Reg(reg, ty, _) => ctx.emit(Inst::gen_move(
                 Writable::from_reg(reg.to_reg()),
                 from_reg,
                 ty,
             )),
-            &ABIArg::Stack(off, ty) => {
+            &ABIArg::Stack(off, ty, ext) => {
+                if ext != ir::ArgumentExtension::None && ty.bits() < 64 {
+                    assert_eq!(RegClass::I64, from_reg.get_class());
+                    let dest_reg = Writable::from_reg(from_reg);
+                    let ext_mode = match ty.bits() {
+                        1 | 8 => ExtMode::BQ,
+                        16 => ExtMode::WQ,
+                        32 => ExtMode::LQ,
+                        _ => unreachable!(),
+                    };
+                    // Extend in place in the source register. Our convention is to
+                    // treat high bits as undefined for values in registers, so this
+                    // is safe, even for an argument that is nominally read-only.
+                    match ext {
+                        ir::ArgumentExtension::Uext => {
+                            ctx.emit(Inst::movzx_rm_r(
+                                ext_mode,
+                                RegMem::reg(from_reg),
+                                dest_reg,
+                                /* infallible load */ None,
+                            ));
+                        }
+                        ir::ArgumentExtension::Sext => {
+                            ctx.emit(Inst::movsx_rm_r(
+                                ext_mode,
+                                RegMem::reg(from_reg),
+                                dest_reg,
+                                /* infallible load */ None,
+                            ));
+                        }
+                        _ => unreachable!(),
+                    };
+                }
+
                 debug_assert!(off <= u32::max_value() as i64);
                 debug_assert!(off >= 0);
                 ctx.emit(store_stack(
                     Amode::imm_reg(off as u32, regs::rsp()),
                     from_reg,
                     ty,
                 ))
             }
@@ -1145,18 +1226,18 @@ impl ABICall for X64ABICall {
 
     fn emit_copy_retval_to_reg<C: LowerCtx<I = Self::I>>(
         &self,
         ctx: &mut C,
         idx: usize,
         into_reg: Writable<Reg>,
     ) {
         match &self.sig.rets[idx] {
-            &ABIArg::Reg(reg, ty) => ctx.emit(Inst::gen_move(into_reg, reg.to_reg(), ty)),
-            &ABIArg::Stack(off, ty) => {
+            &ABIArg::Reg(reg, ty, _) => ctx.emit(Inst::gen_move(into_reg, reg.to_reg(), ty)),
+            &ABIArg::Stack(off, ty, _) => {
                 let ret_area_base = self.sig.stack_arg_space;
                 let sp_offset = off + ret_area_base;
                 // TODO handle offsets bigger than u32::max
                 debug_assert!(sp_offset >= 0);
                 debug_assert!(sp_offset <= u32::max_value() as i64);
                 ctx.emit(load_stack(
                     Amode::imm_reg(sp_offset as u32, regs::rsp()),
                     into_reg,
--- a/third_party/rust/cranelift-codegen/src/isa/x64/inst/args.rs
+++ b/third_party/rust/cranelift-codegen/src/isa/x64/inst/args.rs
@@ -205,16 +205,23 @@ impl RegMemImm {
     /// Add the regs mentioned by `self` to `collector`.
     pub(crate) fn get_regs_as_uses(&self, collector: &mut RegUsageCollector) {
         match self {
             Self::Reg { reg } => collector.add_use(*reg),
             Self::Mem { addr } => addr.get_regs_as_uses(collector),
             Self::Imm { .. } => {}
         }
     }
+
+    pub(crate) fn to_reg(&self) -> Option<Reg> {
+        match self {
+            Self::Reg { reg } => Some(*reg),
+            _ => None,
+        }
+    }
 }
 
 impl ShowWithRRU for RegMemImm {
     fn show_rru(&self, mb_rru: Option<&RealRegUniverse>) -> String {
         self.show_rru_sized(mb_rru, 8)
     }
 
     fn show_rru_sized(&self, mb_rru: Option<&RealRegUniverse>, size: u8) -> String {
@@ -250,33 +257,39 @@ impl RegMem {
     }
     /// Add the regs mentioned by `self` to `collector`.
     pub(crate) fn get_regs_as_uses(&self, collector: &mut RegUsageCollector) {
         match self {
             RegMem::Reg { reg } => collector.add_use(*reg),
             RegMem::Mem { addr, .. } => addr.get_regs_as_uses(collector),
         }
     }
+    pub(crate) fn to_reg(&self) -> Option<Reg> {
+        match self {
+            RegMem::Reg { reg } => Some(*reg),
+            _ => None,
+        }
+    }
 }
 
 impl ShowWithRRU for RegMem {
     fn show_rru(&self, mb_rru: Option<&RealRegUniverse>) -> String {
         self.show_rru_sized(mb_rru, 8)
     }
 
     fn show_rru_sized(&self, mb_rru: Option<&RealRegUniverse>, size: u8) -> String {
         match self {
             RegMem::Reg { reg } => show_ireg_sized(*reg, mb_rru, size),
             RegMem::Mem { addr, .. } => addr.show_rru(mb_rru),
         }
     }
 }
 
 /// Some basic ALU operations.  TODO: maybe add Adc, Sbb.
-#[derive(Clone, PartialEq)]
+#[derive(Copy, Clone, PartialEq)]
 pub enum AluRmiROpcode {
     Add,
     Sub,
     And,
     Or,
     Xor,
     /// The signless, non-extending (N x N -> N, for N in {32,64}) variant.
     Mul,
--- a/third_party/rust/cranelift-codegen/src/isa/x64/inst/emit.rs
+++ b/third_party/rust/cranelift-codegen/src/isa/x64/inst/emit.rs
@@ -2039,18 +2039,17 @@ pub(crate) fn emit(
             //
             // ;; check for NaN
             // cmpss/cmpsd %src, %src
             // jnp not_nan
             // xor %dst, %dst
             //
             // ;; positive inputs get saturated to INT_MAX; negative ones to INT_MIN, which is
             // ;; already in %dst.
-            // mov 0, %tmp_gpr
-            // movd/movq %tmp_gpr, %tmp_xmm
+            // xorpd %tmp_xmm, %tmp_xmm
             // cmpss/cmpsd %src, %tmp_xmm
             // jnb done
             // mov/movaps $INT_MAX, %dst
             //
             // done:
             //
             // Then, for non-saturating conversions:
             //
@@ -2064,18 +2063,17 @@ pub(crate) fn emit(
             // movaps/mov $magic, %tmp_gpr
             // movq/movd %tmp_gpr, %tmp_xmm
             // cmpss/cmpsd %tmp_xmm, %src
             // jnb/jnbe $check_positive
             // ud2 trap IntegerOverflow
             //
             // ;; if positive, it was a real overflow
             // check_positive:
-            // mov 0, %tmp_gpr
-            // movd/movq %tmp_gpr, %tmp_xmm
+            // xorpd %tmp_xmm, %tmp_xmm
             // cmpss/cmpsd %src, %tmp_xmm
             // jnb done
             // ud2 trap IntegerOverflow
             //
             // done:
 
             let src = src.to_reg();
 
@@ -2115,21 +2113,20 @@ pub(crate) fn emit(
                 inst.emit(sink, flags, state);
 
                 let inst = Inst::jmp_known(BranchTarget::Label(done));
                 inst.emit(sink, flags, state);
 
                 sink.bind_label(not_nan);
 
                 // If the input was positive, saturate to INT_MAX.
-                // TODO use xorps/xorpd here
-                let inst = Inst::imm_r(false, 0, *tmp_gpr); // rely on sign-extension to get 0 on 64-bits
-                inst.emit(sink, flags, state);
+
+                // Zero out tmp_xmm.
                 let inst =
-                    Inst::gpr_to_xmm(cast_op, RegMem::reg(tmp_gpr.to_reg()), *src_size, *tmp_xmm);
+                    Inst::xmm_rm_r(SseOpcode::Xorpd, RegMem::reg(tmp_xmm.to_reg()), *tmp_xmm);
                 inst.emit(sink, flags, state);
 
                 let inst = Inst::xmm_cmp_rm_r(cmp_op, RegMem::reg(src), tmp_xmm.to_reg());
                 inst.emit(sink, flags, state);
 
                 // Jump if >= to done.
                 one_way_jmp(sink, CC::NB, done);
 
@@ -2189,22 +2186,19 @@ pub(crate) fn emit(
 
                 let inst = Inst::trap(*srcloc, TrapCode::IntegerOverflow);
                 inst.emit(sink, flags, state);
 
                 // If positive, it was a real overflow.
 
                 sink.bind_label(check_positive);
 
-                // TODO use xorpd
-                let inst = Inst::imm_r(false, 0, *tmp_gpr);
-                inst.emit(sink, flags, state);
-
+                // Zero out the tmp_xmm register.
                 let inst =
-                    Inst::gpr_to_xmm(cast_op, RegMem::reg(tmp_gpr.to_reg()), *src_size, *tmp_xmm);
+                    Inst::xmm_rm_r(SseOpcode::Xorpd, RegMem::reg(tmp_xmm.to_reg()), *tmp_xmm);
                 inst.emit(sink, flags, state);
 
                 let inst = Inst::xmm_cmp_rm_r(cmp_op, RegMem::reg(src), tmp_xmm.to_reg());
                 inst.emit(sink, flags, state);
 
                 one_way_jmp(sink, CC::NB, done); // jump over trap if 0 >= src
 
                 let inst = Inst::trap(*srcloc, TrapCode::IntegerOverflow);
--- a/third_party/rust/cranelift-codegen/src/isa/x64/inst/mod.rs
+++ b/third_party/rust/cranelift-codegen/src/isa/x64/inst/mod.rs
@@ -934,16 +934,50 @@ impl Inst {
         Inst::TrapIf {
             cc,
             trap_code,
             srcloc,
         }
     }
 }
 
+// Inst helpers.
+
+impl Inst {
+    /// In certain cases, instructions of this format can act as a definition of an XMM register,
+    /// producing a value that is independent of its initial value.
+    ///
+    /// For example, a vector equality comparison (`cmppd` or `cmpps`) that compares a register to
+    /// itself will generate all ones as a result, regardless of its value. From the register
+    /// allocator's point of view, we should (i) record the first register, which is normally a
+    /// mod, as a def instead; and (ii) not record the second register as a use, because it is the
+    /// same as the first register (already handled).
+    fn produces_const(&self) -> bool {
+        match self {
+            Self::Alu_RMI_R { op, src, dst, .. } => {
+                src.to_reg() == Some(dst.to_reg())
+                    && (*op == AluRmiROpcode::Xor || *op == AluRmiROpcode::Sub)
+            }
+
+            Self::XMM_RM_R { op, src, dst, .. } => {
+                src.to_reg() == Some(dst.to_reg())
+                    && (*op == SseOpcode::Xorps || *op == SseOpcode::Xorpd)
+            }
+
+            Self::XmmRmRImm { op, src, dst, imm } => {
+                src.to_reg() == Some(dst.to_reg())
+                    && (*op == SseOpcode::Cmppd || *op == SseOpcode::Cmpps)
+                    && *imm == FcmpImm::Equal.encode()
+            }
+
+            _ => false,
+        }
+    }
+}
+
 //=============================================================================
 // Instructions: printing
 
 impl ShowWithRRU for Inst {
     fn show_rru(&self, mb_rru: Option<&RealRegUniverse>) -> String {
         fn ljustify(s: String) -> String {
             let w = 7;
             if s.len() >= w {
@@ -1428,18 +1462,23 @@ impl fmt::Debug for Inst {
 
 fn x64_get_regs(inst: &Inst, collector: &mut RegUsageCollector) {
     // This is a bit subtle. If some register is in the modified set, then it may not be in either
     // the use or def sets. However, enforcing that directly is somewhat difficult. Instead,
     // regalloc.rs will "fix" this for us by removing the the modified set from the use and def
     // sets.
     match inst {
         Inst::Alu_RMI_R { src, dst, .. } => {
-            src.get_regs_as_uses(collector);
-            collector.add_mod(*dst);
+            if inst.produces_const() {
+                // No need to account for src, since src == dst.
+                collector.add_def(*dst);
+            } else {
+                src.get_regs_as_uses(collector);
+                collector.add_mod(*dst);
+            }
         }
         Inst::Div { divisor, .. } => {
             collector.add_mod(Writable::from_reg(regs::rax()));
             collector.add_mod(Writable::from_reg(regs::rdx()));
             divisor.get_regs_as_uses(collector);
         }
         Inst::MulHi { rhs, .. } => {
             collector.add_mod(Writable::from_reg(regs::rax()));
@@ -1461,36 +1500,27 @@ fn x64_get_regs(inst: &Inst, collector: 
             collector.add_use(regs::rax());
             collector.add_def(Writable::from_reg(regs::rdx()));
         }
         Inst::UnaryRmR { src, dst, .. } | Inst::XmmUnaryRmR { src, dst, .. } => {
             src.get_regs_as_uses(collector);
             collector.add_def(*dst);
         }
         Inst::XMM_RM_R { src, dst, .. } => {
-            src.get_regs_as_uses(collector);
-            collector.add_mod(*dst);
+            if inst.produces_const() {
+                // No need to account for src, since src == dst.
+                collector.add_def(*dst);
+            } else {
+                src.get_regs_as_uses(collector);
+                collector.add_mod(*dst);
+            }
         }
-        Inst::XmmRmRImm { src, dst, op, imm } => {
-            // In certain cases, instructions of this format can act as a definition of an XMM
-            // register, producing a value that is independent of its initial value. For example,
-            // a vector equality comparison (`cmppd` or `cmpps`) that compares a register to itself
-            // will generate all ones as a result, regardless of its value. From the register
-            // allocator's point of view, we should (i) record the first register, which is normally
-            // a mod, as a def instread; and (ii) not record the second register as a use, because
-            // it is the same as the first register (already handled). TODO Re-factored in #2071.
-            let is_def = if let RegMem::Reg { reg } = src {
-                (*op == SseOpcode::Cmppd || *op == SseOpcode::Cmpps)
-                    && *imm == FcmpImm::Equal.encode()
-                    && *reg == dst.to_reg()
-            } else {
-                false
-            };
-
-            if is_def {
+        Inst::XmmRmRImm { src, dst, .. } => {
+            if inst.produces_const() {
+                // No need to account for src, since src == dst.
                 collector.add_def(*dst);
             } else {
                 src.get_regs_as_uses(collector);
                 collector.add_mod(*dst);
             }
         }
         Inst::XmmLoadConstSeq { dst, .. } => collector.add_def(*dst),
         Inst::XmmMinMaxSeq { lhs, rhs_dst, .. } => {
@@ -1689,38 +1719,67 @@ impl Amode {
 impl RegMemImm {
     fn map_uses<RUM: RegUsageMapper>(&mut self, map: &RUM) {
         match self {
             RegMemImm::Reg { ref mut reg } => map_use(map, reg),
             RegMemImm::Mem { ref mut addr } => addr.map_uses(map),
             RegMemImm::Imm { .. } => {}
         }
     }
+
+    fn map_as_def<RUM: RegUsageMapper>(&mut self, mapper: &RUM) {
+        match self {
+            Self::Reg { reg } => {
+                let mut writable_src = Writable::from_reg(*reg);
+                map_def(mapper, &mut writable_src);
+                *self = Self::reg(writable_src.to_reg());
+            }
+            _ => panic!("unexpected RegMemImm kind in map_src_reg_as_def"),
+        }
+    }
 }
 
 impl RegMem {
     fn map_uses<RUM: RegUsageMapper>(&mut self, map: &RUM) {
         match self {
             RegMem::Reg { ref mut reg } => map_use(map, reg),
             RegMem::Mem { ref mut addr, .. } => addr.map_uses(map),
         }
     }
+
+    fn map_as_def<RUM: RegUsageMapper>(&mut self, mapper: &RUM) {
+        match self {
+            Self::Reg { reg } => {
+                let mut writable_src = Writable::from_reg(*reg);
+                map_def(mapper, &mut writable_src);
+                *self = Self::reg(writable_src.to_reg());
+            }
+            _ => panic!("unexpected RegMem kind in map_src_reg_as_def"),
+        }
+    }
 }
 
 fn x64_map_regs<RUM: RegUsageMapper>(inst: &mut Inst, mapper: &RUM) {
     // Note this must be carefully synchronized with x64_get_regs.
+    let produces_const = inst.produces_const();
+
     match inst {
         // ** Nop
         Inst::Alu_RMI_R {
             ref mut src,
             ref mut dst,
             ..
         } => {
-            src.map_uses(mapper);
-            map_mod(mapper, dst);
+            if produces_const {
+                src.map_as_def(mapper);
+                map_def(mapper, dst);
+            } else {
+                src.map_uses(mapper);
+                map_mod(mapper, dst);
+            }
         }
         Inst::Div { divisor, .. } => divisor.map_uses(mapper),
         Inst::MulHi { rhs, .. } => rhs.map_uses(mapper),
         Inst::CheckedDivOrRemSeq { divisor, tmp, .. } => {
             map_mod(mapper, divisor);
             if let Some(tmp) = tmp {
                 map_def(mapper, tmp)
             }
@@ -1737,49 +1796,38 @@ fn x64_map_regs<RUM: RegUsageMapper>(ins
             ..
         } => {
             src.map_uses(mapper);
             map_def(mapper, dst);
         }
         Inst::XmmRmRImm {
             ref mut src,
             ref mut dst,
-            ref op,
-            ref imm,
+            ..
         } => {
-            // In certain cases, instructions of this format can convert an XMM register into a
-            // define (e.g. an equality comparison); this extra logic is necessary to inform the
-            // registry allocator of a different register usage. TODO Re-factored in #2071.
-            if let RegMem::Reg { reg } = src {
-                if (*op == SseOpcode::Cmppd || *op == SseOpcode::Cmpps)
-                    && *imm == FcmpImm::Equal.encode()
-                    && *reg == dst.to_reg()
-                {
-                    let mut writable_src = Writable::from_reg(*reg);
-                    map_def(mapper, &mut writable_src);
-                    *reg = writable_src.to_reg();
-                    map_def(mapper, dst);
-                } else {
-                    // Otherwise, we map the instruction as usual.
-                    src.map_uses(mapper);
-                    map_mod(mapper, dst);
-                }
+            if produces_const {
+                src.map_as_def(mapper);
+                map_def(mapper, dst);
             } else {
-                // TODO this is duplicated because there seems to be no way to join the `if let` and `if`?
                 src.map_uses(mapper);
                 map_mod(mapper, dst);
             }
         }
         Inst::XMM_RM_R {
             ref mut src,
             ref mut dst,
             ..
         } => {
-            src.map_uses(mapper);
-            map_mod(mapper, dst);
+            if produces_const {
+                src.map_as_def(mapper);
+                map_def(mapper, dst);
+            } else {
+                src.map_uses(mapper);
+                map_mod(mapper, dst);
+            }
         }
         Inst::XmmRmiReg {
             ref mut src,
             ref mut dst,
             ..
         } => {
             src.map_uses(mapper);
             map_mod(mapper, dst);
@@ -2092,18 +2140,33 @@ impl MachInst for Inst {
     fn gen_constant<F: FnMut(RegClass, Type) -> Writable<Reg>>(
         to_reg: Writable<Reg>,
         value: u64,
         ty: Type,
         mut alloc_tmp: F,
     ) -> SmallVec<[Self; 4]> {
         let mut ret = SmallVec::new();
         if ty.is_int() {
-            let is_64 = ty == I64 && value > 0x7fffffff;
-            ret.push(Inst::imm_r(is_64, value, to_reg));
+            if value == 0 {
+                ret.push(Inst::alu_rmi_r(
+                    ty == I64,
+                    AluRmiROpcode::Xor,
+                    RegMemImm::reg(to_reg.to_reg()),
+                    to_reg,
+                ));
+            } else {
+                let is_64 = ty == I64 && value > 0x7fffffff;
+                ret.push(Inst::imm_r(is_64, value, to_reg));
+            }
+        } else if value == 0 {
+            ret.push(Inst::xmm_rm_r(
+                SseOpcode::Xorps,
+                RegMem::reg(to_reg.to_reg()),
+                to_reg,
+            ));
         } else {
             match ty {
                 F32 => {
                     let tmp = alloc_tmp(RegClass::I64, I32);
                     ret.push(Inst::imm32_r_unchecked(value, tmp));
 
                     ret.push(Inst::gpr_to_xmm(
                         SseOpcode::Movd,
--- a/third_party/rust/cranelift-codegen/src/isa/x64/lower.rs
+++ b/third_party/rust/cranelift-codegen/src/isa/x64/lower.rs
@@ -1038,28 +1038,28 @@ fn lower_insn_to_regs<C: LowerCtx<I = In
             ctx.emit_safepoint(Inst::TrapIf {
                 trap_code,
                 srcloc,
                 cc,
             });
         }
 
         Opcode::F64const => {
-            // TODO use xorpd for 0 and cmpeqpd for all 1s.
+            // TODO use cmpeqpd for all 1s.
             let value = ctx.get_constant(insn).unwrap();
             let dst = output_to_reg(ctx, outputs[0]);
             for inst in Inst::gen_constant(dst, value, F64, |reg_class, ty| {
                 ctx.alloc_tmp(reg_class, ty)
             }) {
                 ctx.emit(inst);
             }
         }
 
         Opcode::F32const => {
-            // TODO use xorps for 0 and cmpeqps for all 1s.
+            // TODO use cmpeqps for all 1s.
             let value = ctx.get_constant(insn).unwrap();
             let dst = output_to_reg(ctx, outputs[0]);
             for inst in Inst::gen_constant(dst, value, F32, |reg_class, ty| {
                 ctx.alloc_tmp(reg_class, ty)
             }) {
                 ctx.emit(inst);
             }
         }
--- a/third_party/rust/cranelift-codegen/src/machinst/abi.rs
+++ b/third_party/rust/cranelift-codegen/src/machinst/abi.rs
@@ -1,12 +1,12 @@
 //! ABI definitions.
 
 use crate::binemit::Stackmap;
-use crate::ir::{ArgumentExtension, StackSlot};
+use crate::ir::StackSlot;
 use crate::machinst::*;
 use crate::settings;
 
 use regalloc::{Reg, Set, SpillSlot, Writable};
 
 /// Trait implemented by an object that tracks ABI-related state (e.g., stack
 /// layout) and can generate code while emitting the *body* of a function.
 pub trait ABIBody {
@@ -47,22 +47,17 @@ pub trait ABIBody {
     /// Generate any setup instruction needed to save values to the
     /// return-value area. This is usually used when were are multiple return
     /// values or an otherwise large return value that must be passed on the
     /// stack; typically the ABI specifies an extra hidden argument that is a
     /// pointer to that memory.
     fn gen_retval_area_setup(&self) -> Option<Self::I>;
 
     /// Generate an instruction which copies a source register to a return value slot.
-    fn gen_copy_reg_to_retval(
-        &self,
-        idx: usize,
-        from_reg: Writable<Reg>,
-        ext: ArgumentExtension,
-    ) -> Vec<Self::I>;
+    fn gen_copy_reg_to_retval(&self, idx: usize, from_reg: Writable<Reg>) -> Vec<Self::I>;
 
     /// Generate a return instruction.
     fn gen_ret(&self) -> Self::I;
 
     /// Generate an epilogue placeholder. The returned instruction should return `true` from
     /// `is_epilogue_placeholder()`; this is used to indicate to the lowering driver when
     /// the epilogue should be inserted.
     fn gen_epilogue_placeholder(&self) -> Self::I;
--- a/third_party/rust/cranelift-codegen/src/machinst/lower.rs
+++ b/third_party/rust/cranelift-codegen/src/machinst/lower.rs
@@ -3,19 +3,18 @@
 //! machine code, except for register allocation.
 
 use crate::entity::SecondaryMap;
 use crate::fx::{FxHashMap, FxHashSet};
 use crate::inst_predicates::{has_side_effect_or_load, is_constant_64bit};
 use crate::ir::instructions::BranchInfo;
 use crate::ir::types::I64;
 use crate::ir::{
-    ArgumentExtension, ArgumentPurpose, Block, Constant, ConstantData, ExternalName, Function,
-    GlobalValueData, Inst, InstructionData, MemFlags, Opcode, Signature, SourceLoc, Type, Value,
-    ValueDef,
+    ArgumentPurpose, Block, Constant, ConstantData, ExternalName, Function, GlobalValueData, Inst,
+    InstructionData, MemFlags, Opcode, Signature, SourceLoc, Type, Value, ValueDef,
 };
 use crate::machinst::{
     ABIBody, BlockIndex, BlockLoweringOrder, LoweredBlock, MachLabel, VCode, VCodeBuilder,
     VCodeInst,
 };
 use crate::CodegenResult;
 
 use regalloc::{Reg, RegClass, StackmapRequestInfo, VirtualReg, Writable};
@@ -227,17 +226,17 @@ pub struct Lower<'func, I: VCodeInst> {
 
     /// Lowered machine instructions.
     vcode: VCodeBuilder<I>,
 
     /// Mapping from `Value` (SSA value in IR) to virtual register.
     value_regs: SecondaryMap<Value, Reg>,
 
     /// Return-value vregs.
-    retval_regs: Vec<(Reg, ArgumentExtension)>,
+    retval_regs: Vec<Reg>,
 
     /// Instruction colors.
     inst_colors: SecondaryMap<Inst, InstColor>,
 
     /// Instruction constant values, if known.
     inst_constants: FxHashMap<Inst, u64>,
 
     /// Instruction has a side-effect and must be codegen'd.
@@ -349,17 +348,17 @@ impl<'func, I: VCodeInst> Lower<'func, I
 
         // Assign a vreg to each return value.
         let mut retval_regs = vec![];
         for ret in &f.signature.returns {
             let v = next_vreg;
             next_vreg += 1;
             let regclass = I::rc_for_type(ret.value_type)?;
             let vreg = Reg::new_virtual(regclass, v);
-            retval_regs.push((vreg, ret.extension));
+            retval_regs.push(vreg);
             vcode.set_vreg_type(vreg.as_virtual_reg().unwrap(), ret.value_type);
         }
 
         // Compute instruction colors, find constant instructions, and find instructions with
         // side-effects, in one combined pass.
         let mut cur_color = 0;
         let mut inst_colors = SecondaryMap::with_default(InstColor::new(0));
         let mut inst_constants = FxHashMap::default();
@@ -422,19 +421,19 @@ impl<'func, I: VCodeInst> Lower<'func, I
             if let Some(insn) = self.vcode.abi().gen_retval_area_setup() {
                 self.emit(insn);
             }
         }
     }
 
     fn gen_retval_setup(&mut self, gen_ret_inst: GenerateReturn) {
         let retval_regs = self.retval_regs.clone();
-        for (i, (reg, ext)) in retval_regs.into_iter().enumerate() {
+        for (i, reg) in retval_regs.into_iter().enumerate() {
             let reg = Writable::from_reg(reg);
-            let insns = self.vcode.abi().gen_copy_reg_to_retval(i, reg, ext);
+            let insns = self.vcode.abi().gen_copy_reg_to_retval(i, reg);
             for insn in insns {
                 self.emit(insn);
             }
         }
         let inst = match gen_ret_inst {
             GenerateReturn::Yes => self.vcode.abi().gen_ret(),
             GenerateReturn::No => self.vcode.abi().gen_epilogue_placeholder(),
         };
@@ -839,17 +838,17 @@ impl<'func, I: VCodeInst> Lower<'func, I
 impl<'func, I: VCodeInst> LowerCtx for Lower<'func, I> {
     type I = I;
 
     fn abi(&mut self) -> &dyn ABIBody<I = I> {
         self.vcode.abi()
     }
 
     fn retval(&self, idx: usize) -> Writable<Reg> {
-        Writable::from_reg(self.retval_regs[idx].0)
+        Writable::from_reg(self.retval_regs[idx])
     }
 
     fn get_vm_context(&self) -> Option<Reg> {
         self.vm_context
     }
 
     fn data(&self, ir_inst: Inst) -> &InstructionData {
         &self.f.dfg[ir_inst]
--- a/third_party/rust/cranelift-wasm/.cargo-checksum.json
+++ b/third_party/rust/cranelift-wasm/.cargo-checksum.json
@@ -1,1 +1,1 @@
-{"files":{"Cargo.toml":"34ad61b3a40b5bfee68d575e749314cf8395484c0484fd40d39a9bd1f46d3e14","LICENSE":"268872b9816f90fd8e85db5a28d33f8150ebb8dd016653fb39ef1f94f2686bc5","README.md":"c82c252fbeeaa101a0eef042b9a925eb1fa3d2b51d19481b9c22e593e6a8d772","src/code_translator.rs":"77d407a26746381c1f433e0d13e758bfd2864936fc156c5eb5114a7dc146a2f1","src/environ/dummy.rs":"e9b06d1db4d25ab622d133ca927ec524a86d90d49eb67862dea0db734a0eadc4","src/environ/mod.rs":"692f35d75f125f9c071f7166252f427e4bac29401356f73307c6c36e23c667fb","src/environ/spec.rs":"b2ead10ea1f346d6fe2e4a5afc656754f0783fae98a3937b42cc106ad9e5eace","src/func_translator.rs":"48ee25da11063743459f9e9407512413075265e67713c6f5ab733798be2bf19d","src/lib.rs":"7bdbcf638fa30fb05e8320439881f7536824f7f60a7db4f0c1b51ab369edf895","src/module_translator.rs":"def8b0853f1e802faf57b38e90016577887a0698a5abce5b3cee4cd67e07ecf0","src/sections_translator.rs":"8bbf6cf774076c88f176296065b392ff21ed512be806629cce5d275271eee3a8","src/state/func_state.rs":"023e3eb4f69590167baecb3fa8e7b335d69a631fff68fa0ee249075699f71a30","src/state/mod.rs":"20014cb93615467b4d20321b52f67f66040417efcaa739a4804093bb559eed19","src/state/module_state.rs":"7ca3cb06b4481bc3ae74697fbcd437aea1d851eaa3cfe18cc013a4af43728957","src/translation_utils.rs":"69f20c47ea22f0badd21a6187b5f9764252a00d19643a7e3e691797a9fe34f1b","tests/wasm_testsuite.rs":"da8dedfd11918946e9cf6af68fd4826f020ef90a4e22742b1a30e61a3fb4aedd"},"package":null}
\ No newline at end of file
+{"files":{"Cargo.toml":"34ad61b3a40b5bfee68d575e749314cf8395484c0484fd40d39a9bd1f46d3e14","LICENSE":"268872b9816f90fd8e85db5a28d33f8150ebb8dd016653fb39ef1f94f2686bc5","README.md":"c82c252fbeeaa101a0eef042b9a925eb1fa3d2b51d19481b9c22e593e6a8d772","src/code_translator.rs":"77d407a26746381c1f433e0d13e758bfd2864936fc156c5eb5114a7dc146a2f1","src/environ/dummy.rs":"3fe0ab41d04b4ba517d7caf1617d30dda6489f73486383ed0c6a6fd0d8c9cbc9","src/environ/mod.rs":"692f35d75f125f9c071f7166252f427e4bac29401356f73307c6c36e23c667fb","src/environ/spec.rs":"9f709bddaa4638c1d913949f4e20406a07b1f097ccb7701d26ea0c23f39a8a20","src/func_translator.rs":"48ee25da11063743459f9e9407512413075265e67713c6f5ab733798be2bf19d","src/lib.rs":"7bdbcf638fa30fb05e8320439881f7536824f7f60a7db4f0c1b51ab369edf895","src/module_translator.rs":"1374fa56ca18a782083fa0f25f2ad675044a92bbf1a0a1cc44fcaf695807e044","src/sections_translator.rs":"11d65fd2e595e41f976e5c7d0df823f70449f79a9d2facbed61263616f8cfec1","src/state/func_state.rs":"023e3eb4f69590167baecb3fa8e7b335d69a631fff68fa0ee249075699f71a30","src/state/mod.rs":"20014cb93615467b4d20321b52f67f66040417efcaa739a4804093bb559eed19","src/state/module_state.rs":"7ca3cb06b4481bc3ae74697fbcd437aea1d851eaa3cfe18cc013a4af43728957","src/translation_utils.rs":"69f20c47ea22f0badd21a6187b5f9764252a00d19643a7e3e691797a9fe34f1b","tests/wasm_testsuite.rs":"da8dedfd11918946e9cf6af68fd4826f020ef90a4e22742b1a30e61a3fb4aedd"},"package":null}
\ No newline at end of file
--- a/third_party/rust/cranelift-wasm/src/environ/dummy.rs
+++ b/third_party/rust/cranelift-wasm/src/environ/dummy.rs
@@ -738,18 +738,16 @@ impl<'data> ModuleEnvironment<'data> for
             )?;
             func
         };
         self.func_bytecode_sizes.push(body_bytes.len());
         self.info.function_bodies.push(func);
         Ok(())
     }
 
-    fn declare_module_name(&mut self, name: &'data str) -> WasmResult<()> {
+    fn declare_module_name(&mut self, name: &'data str) {
         self.module_name = Some(String::from(name));
-        Ok(())
     }
 
-    fn declare_func_name(&mut self, func_index: FuncIndex, name: &'data str) -> WasmResult<()> {
+    fn declare_func_name(&mut self, func_index: FuncIndex, name: &'data str) {
         self.function_names[func_index] = String::from(name);
-        Ok(())
     }
 }
--- a/third_party/rust/cranelift-wasm/src/environ/spec.rs
+++ b/third_party/rust/cranelift-wasm/src/environ/spec.rs
@@ -61,16 +61,30 @@ impl TryFrom<wasmparser::Type> for WasmT
             EmptyBlockType | Func => Err(WasmError::InvalidWebAssembly {
                 message: "unexpected value type".to_string(),
                 offset: 0,
             }),
         }
     }
 }
 
+impl From<WasmType> for wasmparser::Type {
+    fn from(ty: WasmType) -> wasmparser::Type {
+        match ty {
+            WasmType::I32 => wasmparser::Type::I32,
+            WasmType::I64 => wasmparser::Type::I64,
+            WasmType::F32 => wasmparser::Type::F32,
+            WasmType::F64 => wasmparser::Type::F64,
+            WasmType::V128 => wasmparser::Type::V128,
+            WasmType::FuncRef => wasmparser::Type::FuncRef,
+            WasmType::ExternRef => wasmparser::Type::ExternRef,
+        }
+    }
+}
+
 /// WebAssembly function type -- equivalent of `wasmparser`'s FuncType.
 #[derive(Debug, Clone, Eq, PartialEq, Hash)]
 #[cfg_attr(feature = "enable-serde", derive(Serialize, Deserialize))]
 pub struct WasmFuncType {
     /// Function params types.
     pub params: Box<[WasmType]>,
     /// Returns params types.
     pub returns: Box<[WasmType]>,
@@ -738,20 +752,23 @@ pub trait ModuleEnvironment<'data>: Targ
     fn reserve_passive_data(&mut self, count: u32) -> WasmResult<()> {
         let _ = count;
         Ok(())
     }
 
     /// Declare a passive data segment.
     fn declare_passive_data(&mut self, data_index: DataIndex, data: &'data [u8]) -> WasmResult<()>;
 
+    /// Indicates how many functions the code section reports and the byte
+    /// offset of where the code sections starts.
+    fn reserve_function_bodies(&mut self, bodies: u32, code_section_offset: u64) {
+        drop((bodies, code_section_offset));
+    }
+
     /// Provides the contents of a function body.
-    ///
-    /// Note there's no `reserve_function_bodies` function because the number of
-    /// functions is already provided by `reserve_func_types`.
     fn define_function_body(
         &mut self,
         module_translation_state: &ModuleTranslationState,
         body_bytes: &'data [u8],
         body_offset: usize,
     ) -> WasmResult<()>;
 
     /// Provides the number of data initializers up front. By default this does nothing, but
@@ -768,25 +785,28 @@ pub trait ModuleEnvironment<'data>: Targ
         offset: usize,
         data: &'data [u8],
     ) -> WasmResult<()>;
 
     /// Declares the name of a module to the environment.
     ///
     /// By default this does nothing, but implementations can use this to read
     /// the module name subsection of the custom name section if desired.
-    fn declare_module_name(&mut self, _name: &'data str) -> WasmResult<()> {
-        Ok(())
-    }
+    fn declare_module_name(&mut self, _name: &'data str) {}
 
     /// Declares the name of a function to the environment.
     ///
     /// By default this does nothing, but implementations can use this to read
     /// the function name subsection of the custom name section if desired.
-    fn declare_func_name(&mut self, _func_index: FuncIndex, _name: &'data str) -> WasmResult<()> {
-        Ok(())
+    fn declare_func_name(&mut self, _func_index: FuncIndex, _name: &'data str) {}
+
+    /// Declares the name of a function's local to the environment.
+    ///
+    /// By default this does nothing, but implementations can use this to read
+    /// the local name subsection of the custom name section if desired.
+    fn declare_local_name(&mut self, _func_index: FuncIndex, _local_index: u32, _name: &'data str) {
     }
 
     /// Indicates that a custom section has been found in the wasm file
     fn custom_section(&mut self, _name: &'data str, _data: &'data [u8]) -> WasmResult<()> {
         Ok(())
     }
 }
--- a/third_party/rust/cranelift-wasm/src/module_translator.rs
+++ b/third_party/rust/cranelift-wasm/src/module_translator.rs
@@ -54,17 +54,20 @@ pub fn translate_module<'data>(
             Payload::StartSection { func, .. } => {
                 parse_start_section(func, environ)?;
             }
 
             Payload::ElementSection(elements) => {
                 parse_element_section(elements, environ)?;
             }
 
-            Payload::CodeSectionStart { .. } => {}
+            Payload::CodeSectionStart { count, range, .. } => {
+                environ.reserve_function_bodies(count, range.start as u64);
+            }
+
             Payload::CodeSectionEntry(code) => {
                 let mut code = code.get_binary_reader();
                 let size = code.bytes_remaining();
                 let offset = code.original_position();
                 environ.define_function_body(
                     &module_translation_state,
                     code.read_bytes(size)?,
                     offset,
@@ -86,17 +89,24 @@ pub fn translate_module<'data>(
             | Payload::ModuleCodeSectionEntry { .. } => {
                 unimplemented!("module linking not implemented yet")
             }
 
             Payload::CustomSection {
                 name: "name",
                 data,
                 data_offset,
-            } => parse_name_section(NameSectionReader::new(data, data_offset)?, environ)?,
+            } => {
+                let result = NameSectionReader::new(data, data_offset)
+                    .map_err(|e| e.into())
+                    .and_then(|s| parse_name_section(s, environ));
+                if let Err(e) = result {
+                    log::warn!("failed to parse name section {:?}", e);
+                }
+            }
 
             Payload::CustomSection { name, data, .. } => environ.custom_section(name, data)?,
 
             Payload::UnknownSection { .. } => unreachable!(),
         }
     }
 
     Ok(module_translation_state)
--- a/third_party/rust/cranelift-wasm/src/sections_translator.rs
+++ b/third_party/rust/cranelift-wasm/src/sections_translator.rs
@@ -8,31 +8,31 @@
 //! is handled, according to the semantics of WebAssembly, to only specific expressions that are
 //! interpreted on the fly.
 use crate::environ::{ModuleEnvironment, WasmError, WasmResult};
 use crate::state::ModuleTranslationState;
 use crate::translation_utils::{
     tabletype_to_type, type_to_type, DataIndex, ElemIndex, FuncIndex, Global, GlobalIndex,
     GlobalInit, Memory, MemoryIndex, SignatureIndex, Table, TableElementType, TableIndex,
 };
-use crate::{wasm_unsupported, HashMap};
+use crate::wasm_unsupported;
 use core::convert::TryFrom;
 use core::convert::TryInto;
 use cranelift_codegen::ir::immediates::V128Imm;
 use cranelift_codegen::ir::{self, AbiParam, Signature};
 use cranelift_entity::packed_option::ReservedValue;
 use cranelift_entity::EntityRef;
 use std::boxed::Box;
 use std::vec::Vec;
 use wasmparser::{
     self, Data, DataKind, DataSectionReader, Element, ElementItem, ElementItems, ElementKind,
     ElementSectionReader, Export, ExportSectionReader, ExternalKind, FunctionSectionReader,
     GlobalSectionReader, GlobalType, ImportSectionEntryType, ImportSectionReader,
-    MemorySectionReader, MemoryType, NameSectionReader, Naming, NamingReader, Operator,
-    TableSectionReader, Type, TypeDef, TypeSectionReader,
+    MemorySectionReader, MemoryType, NameSectionReader, Naming, Operator, TableSectionReader, Type,
+    TypeDef, TypeSectionReader,
 };
 
 /// Parses the Type section of the wasm module.
 pub fn parse_type_section(
     types: TypeSectionReader,
     module_translation_state: &mut ModuleTranslationState,
     environ: &mut dyn ModuleEnvironment,
 ) -> WasmResult<()> {
@@ -399,58 +399,45 @@ pub fn parse_data_section<'data>(
         }
     }
 
     Ok(())
 }
 
 /// Parses the Name section of the wasm module.
 pub fn parse_name_section<'data>(
-    mut names: NameSectionReader<'data>,
+    names: NameSectionReader<'data>,
     environ: &mut dyn ModuleEnvironment<'data>,
 ) -> WasmResult<()> {
-    while let Ok(subsection) = names.read() {
-        match subsection {
-            wasmparser::Name::Function(function_subsection) => {
-                if let Some(function_names) = function_subsection
-                    .get_map()
-                    .ok()
-                    .and_then(parse_function_name_subsection)
-                {
-                    for (index, name) in function_names {
-                        environ.declare_func_name(index, name)?;
+    for subsection in names {
+        match subsection? {
+            wasmparser::Name::Function(f) => {
+                let mut names = f.get_map()?;
+                for _ in 0..names.get_count() {
+                    let Naming { index, name } = names.read()?;
+                    // We reserve `u32::MAX` for our own use in cranelift-entity.
+                    if index != u32::max_value() {
+                        environ.declare_func_name(FuncIndex::from_u32(index), name);
                     }
                 }
             }
             wasmparser::Name::Module(module) => {
-                if let Ok(name) = module.get_name() {
-                    environ.declare_module_name(name)?;
+                let name = module.get_name()?;
+                environ.declare_module_name(name);
+            }
+            wasmparser::Name::Local(l) => {
+                let mut reader = l.get_function_local_reader()?;
+                for _ in 0..reader.get_count() {
+                    let f = reader.read()?;
+                    if f.func_index == u32::max_value() {
+                        continue;
+                    }
+                    let mut map = f.get_map()?;
+                    for _ in 0..map.get_count() {
+                        let Naming { index, name } = map.read()?;
+                        environ.declare_local_name(FuncIndex::from_u32(f.func_index), index, name)
+                    }
                 }
             }
-            wasmparser::Name::Local(_) => {}
-        };
+        }
     }
     Ok(())
 }
-
-fn parse_function_name_subsection(
-    mut naming_reader: NamingReader<'_>,
-) -> Option<HashMap<FuncIndex, &str>> {
-    let mut function_names = HashMap::new();
-    for _ in 0..naming_reader.get_count() {
-        let Naming { index, name } = naming_reader.read().ok()?;
-        if index == std::u32::MAX {
-            // We reserve `u32::MAX` for our own use in cranelift-entity.
-            return None;
-        }
-
-        if function_names
-            .insert(FuncIndex::from_u32(index), name)
-            .is_some()
-        {
-            // If the function index has been previously seen, then we
-            // break out of the loop and early return `None`, because these
-            // should be unique.
-            return None;
-        }
-    }
-    Some(function_names)
-}