Bug 576247 - asm_stkarg not implemented for x86_64. r=edwsmith
authorMakoto Kato <m_kato@ga2.so-net.ne.jp>
Wed, 25 May 2011 17:37:27 +0900
changeset 6474 bf9d9cfd04d4baff22e2b80528eb8d3e5475f259
parent 6473 67980239802cc1d3a7c8875221a62a2dfcc47410
child 6475 f2eecf428cb622876f9f74867eee1231c98fa6b2
push id3815
push userstejohns@adobe.com
push dateThu, 21 Jul 2011 00:23:51 +0000
reviewersedwsmith
bugs576247
Bug 576247 - asm_stkarg not implemented for x86_64. r=edwsmith
nanojit/NativeX64.cpp
nanojit/NativeX64.h
--- a/nanojit/NativeX64.cpp
+++ b/nanojit/NativeX64.cpp
@@ -52,17 +52,16 @@ completion
 - validate asm_cond with other conditions
 
 better code
 - put R12 back in play as a base register
 - no-disp addr modes (except RBP/R13)
 - disp64 branch/call
 - spill gp values to xmm registers?
 - prefer xmm registers for copies since gprs are in higher demand?
-- stack arg doubles
 - stack based LIR_paramp
 
 tracing
 - nFragExit
 
 */
 
 namespace nanojit
@@ -624,16 +623,17 @@ namespace nanojit
     void Assembler::RET()           { emit(X64_ret);     asm_output("ret");        }
 
     void Assembler::MOVQMI(R r, I d, I32 imm) { emitrm_imm32(X64_movqmi,r,d,imm); asm_output("movq %d(%s), %d",d,RQ(r),imm); }
     void Assembler::MOVLMI(R r, I d, I32 imm) { emitrm_imm32(X64_movlmi,r,d,imm); asm_output("movl %d(%s), %d",d,RQ(r),imm); }
     void Assembler::MOVSMI(R r, I d, I32 imm) { emitprm_imm16(X64_movsmi,r,d,imm); asm_output("movs %d(%s), %d",d,RQ(r),imm); }
     void Assembler::MOVBMI(R r, I d, I32 imm) { emitrm_imm8(X64_movbmi,r,d,imm); asm_output("movb %d(%s), %d",d,RQ(r),imm); }
 
     void Assembler::MOVQSPR(I d, R r)   { emit(X64_movqspr | U64(d) << 56 | U64((REGNUM(r)&7)<<3) << 40 | U64((REGNUM(r)&8)>>1) << 24); asm_output("movq %d(rsp), %s", d, RQ(r)); }    // insert r into mod/rm and rex bytes
+    void Assembler::MOVQSPX(I d, R r)   { emit(rexprb(X64_movqspx,RSP,r) | U64(d) << 56 | U64((REGNUM(r)&7)<<3) << 40); asm_output("movq %d(rsp), %s", d, RQ(r)); }
 
     void Assembler::XORPSA(R r, I32 i32)    { emitxm_abs(X64_xorpsa, r, i32); asm_output("xorps %s, (0x%x)",RQ(r), i32); }
     void Assembler::XORPSM(R r, NIns* a64)  { emitxm_rel(X64_xorpsm, r, a64); asm_output("xorps %s, (%p)",  RQ(r), a64); }
 
     void Assembler::X86_AND8R(R r)  { emit(X86_and8r | U64(REGNUM(r)<<3|(REGNUM(r)|4))<<56); asm_output("andb %s, %s", RB(r), RBhi(r)); }
     void Assembler::X86_SETNP(R r)  { emit(X86_setnp | U64(REGNUM(r)|4)<<56); asm_output("setnp %s", RBhi(r)); }
     void Assembler::X86_SETE(R r)   { emit(X86_sete  | U64(REGNUM(r))<<56);   asm_output("sete %s", RB(r)); }
 
@@ -1072,16 +1072,20 @@ namespace nanojit
             } else if (ty == ARGTYPE_UI) {
                 // zero extend uint32 to uint64
                 NanoAssert(p->isI());
                 MOVLR(r, r);
             } else {
                 NanoAssert(ty == ARGTYPE_Q);
                 // Do nothing.
             }
+        } else if (ty == ARGTYPE_D) {
+            NanoAssert(p->isD());
+            Register r = findRegFor(p, FpRegs);
+            MOVQSPX(stk_off, r);    // movsd [rsp+d8], xmm
         } else {
             TODO(asm_stkarg_non_int);
         }
     }
 
     void Assembler::asm_q2i(LIns *ins) {
         Register rr, ra;
         beginOp1Regs(ins, GpRegs, rr, ra);
--- a/nanojit/NativeX64.h
+++ b/nanojit/NativeX64.h
@@ -243,17 +243,18 @@ namespace nanojit
         X64_lealrm  = 0x00000000808D4007LL, // 32bit load effective addr reg <- disp32+base
         X64_learip  = 0x00000000058D4807LL, // 64bit RIP-relative lea. reg <- disp32+rip (modrm = 00rrr101 = 05)
         X64_movlr   = 0xC08B400000000003LL, // 32bit mov r <- b
         X64_movbmr  = 0x0000000080884007LL, // 8bit store r -> [b+d32]
         X64_movsmr  = 0x8089406600000004LL, // 16bit store r -> [b+d32]
         X64_movlmr  = 0x0000000080894007LL, // 32bit store r -> [b+d32]
         X64_movlrm  = 0x00000000808B4007LL, // 32bit load r <- [b+d32]
         X64_movqmr  = 0x0000000080894807LL, // 64bit store gpr -> [b+d32]
-        X64_movqspr = 0x0024448948000005LL, // 64bit store gpr -> [rsp+d32] (sib required)
+        X64_movqspr = 0x0024448948000005LL, // 64bit store gpr -> [rsp+d8] (sib required)
+        X64_movqspx = 0x002444110F40F207LL, // 64bit store xmm -> [rsp+d8] (sib required)
         X64_movqr   = 0xC08B480000000003LL, // 64bit mov r <- b
         X64_movqi   = 0xB848000000000002LL, // 64bit mov r <- imm64
         X64_movi    = 0xB840000000000002LL, // 32bit mov r <- immI
         X64_movqi32 = 0xC0C7480000000003LL, // 64bit mov r <- int64(immI)
         X64_movapsr = 0xC0280F4000000004LL, // 128bit mov xmm <- xmm
         X64_movqrx  = 0xC07E0F4866000005LL, // 64bit mov b <- xmm-r (reverses the usual r/b order)
         X64_movqxr  = 0xC06E0F4866000005LL, // 64bit mov b -> xmm-r
         X64_movqrm  = 0x00000000808B4807LL, // 64bit load r <- [b+d32]
@@ -603,16 +604,17 @@ namespace nanojit
         void JNB8(size_t n, NIns* t);\
         void JNBE8(size_t n, NIns* t);\
         void JNA8(size_t n, NIns* t);\
         void JNAE8(size_t n, NIns* t);\
         void CALL(size_t n, NIns* t);\
         void CALLRAX();\
         void RET();\
         void MOVQSPR(int d, Register r);\
+        void MOVQSPX(int d, Register r);\
         void XORPSA(Register r, int32_t i32);\
         void XORPSM(Register r, NIns* a64);\
         void X86_AND8R(Register r);\
         void X86_SETNP(Register r);\
         void X86_SETE(Register r);\
         void MOVQMI(Register base, int disp, int32_t imm32); \
         void MOVLMI(Register base, int disp, int32_t imm32); \
         void MOVSMI(Register base, int disp, int32_t imm16); \