Bug 1521158 - Invalidate ARM64 caches by increments of at most 32 bytes instead of increments of cache lines. r=sstangl a=pascalc
authorNicolas B. Pierron <nicolas.b.pierron@nbp.name>
Thu, 25 Apr 2019 16:39:14 +0000
changeset 526447 fab87214b264dcf281db22bf4e4d1a696a5f1d49
parent 526446 c261d2fbfb0184104451cf375e863ef91868f23c
child 526448 e41d56e7c5b8d6a669ec01ae69d96d4f8a934005
push id2032
push userffxbld-merge
push dateMon, 13 May 2019 09:36:57 +0000
treeherdermozilla-release@455c1065dcbe [default view] [failures only]
perfherder[talos] [build metrics] [platform microbench] (compared to previous push)
reviewerssstangl, pascalc
bugs1521158
milestone67.0
Bug 1521158 - Invalidate ARM64 caches by increments of at most 32 bytes instead of increments of cache lines. r=sstangl a=pascalc Differential Revision: https://phabricator.services.mozilla.com/D28827
js/src/jit/arm64/vixl/Cpu-vixl.cpp
--- a/js/src/jit/arm64/vixl/Cpu-vixl.cpp
+++ b/js/src/jit/arm64/vixl/Cpu-vixl.cpp
@@ -20,16 +20,19 @@
 // FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 // DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
 // SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
 // CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
 // OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
 #include "jit/arm64/vixl/Cpu-vixl.h"
+
+#include <algorithm>
+
 #include "jit/arm64/vixl/Utils-vixl.h"
 
 namespace vixl {
 
 // Initialise to smallest possible cache size.
 unsigned CPU::dcache_line_size_ = 1;
 unsigned CPU::icache_line_size_ = 1;
 
@@ -49,11 +52,20 @@ void CPU::SetUp() {
   // a power of two.
   uint32_t dcache_line_size_power_of_two =
       (cache_type_register & kDCacheLineSizeMask) >> kDCacheLineSizeShift;
   uint32_t icache_line_size_power_of_two =
       (cache_type_register & kICacheLineSizeMask) >> kICacheLineSizeShift;
 
   dcache_line_size_ = 4 << dcache_line_size_power_of_two;
   icache_line_size_ = 4 << icache_line_size_power_of_two;
+
+  // Bug 1521158 suggests that having CPU with different cache line sizes could
+  // cause issues as we would only invalidate half of the cache line of we
+  // invalidate every 128 bytes, but other little cores have a different stride
+  // such as 64 bytes. To be conservative, we will try reducing the stride to 32
+  // bytes, which should be smaller than any known cache line.
+  const uint32_t conservative_line_size = 32;
+  dcache_line_size_ = std::min(dcache_line_size_, conservative_line_size);
+  icache_line_size_ = std::min(icache_line_size_, conservative_line_size);
 }
 
 }  // namespace vixl