Bug 1521158: Robustify cache-line invalidations on AARCH64. r=jandem a=pascalc
authorKannan Vijayan <kvijayan@mozilla.com>
Thu, 25 Apr 2019 12:01:30 -0400
changeset 526448 e41d56e7c5b8d6a669ec01ae69d96d4f8a934005
parent 526447 fab87214b264dcf281db22bf4e4d1a696a5f1d49
child 526449 34aa656a9948ca56e5fa260650a23d28f190a7cf
push id2032
push userffxbld-merge
push dateMon, 13 May 2019 09:36:57 +0000
treeherdermozilla-release@455c1065dcbe [default view] [failures only]
perfherder[talos] [build metrics] [platform microbench] (compared to previous push)
reviewersjandem, pascalc
bugs1521158
milestone67.0
Bug 1521158: Robustify cache-line invalidations on AARCH64. r=jandem a=pascalc
js/src/jit/arm64/vixl/MozCpu-vixl.cpp
--- a/js/src/jit/arm64/vixl/MozCpu-vixl.cpp
+++ b/js/src/jit/arm64/vixl/MozCpu-vixl.cpp
@@ -76,22 +76,24 @@ void CPU::EnsureIAndDCacheCoherency(void
   uintptr_t end = start + length;
 
   do {
     __asm__ __volatile__ (
       // Clean each line of the D cache containing the target data.
       //
       // dc       : Data Cache maintenance
       //     c    : Clean
+      //      i   : Invalidate
       //      va  : by (Virtual) Address
-      //        u : to the point of Unification
-      // The point of unification for a processor is the point by which the
-      // instruction and data caches are guaranteed to see the same copy of a
-      // memory location. See ARM DDI 0406B page B2-12 for more information.
-      "   dc    cvau, %[dline]\n"
+      //        c : to the point of Coherency
+      // Original implementation used cvau, but changed to civac due to
+      // errata on Cortex-A53 819472, 826319, 827319 and 824069.
+      // See ARM DDI 0406B page B2-12 for more information.
+      //
+      "   dc    civac, %[dline]\n"
       :
       : [dline] "r" (dline)
       // This code does not write to memory, but the "memory" dependency
       // prevents GCC from reordering the code.
       : "memory");
     dline += dsize;
   } while (dline < end);