Bug 1510749 - The AArch64 ISR explicitly allows CSINC to accept ZR. r=nbp
authorSean Stangl <sean.stangl@gmail.com>
Fri, 30 Nov 2018 11:21:00 +0200
changeset 508263 6c17ac872bdfa23edf836b45246eca9201430d6f
parent 508262 51b417f1d2c3ef81f200ef37041864980b962df8
child 508264 534d6864862bdbcec64551b12bc87e5a230b66ab
push id1905
push userffxbld-merge
push dateMon, 21 Jan 2019 12:33:13 +0000
treeherdermozilla-release@c2fca1944d8c [default view] [failures only]
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reviewersnbp
bugs1510749
milestone65.0a1
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Bug 1510749 - The AArch64 ISR explicitly allows CSINC to accept ZR. r=nbp
js/src/jit/arm64/vixl/MacroAssembler-vixl.h
--- a/js/src/jit/arm64/vixl/MacroAssembler-vixl.h
+++ b/js/src/jit/arm64/vixl/MacroAssembler-vixl.h
@@ -651,18 +651,22 @@ class MacroAssembler : public js::jit::A
     SingleEmissionCheckScope guard(this);
     csetm(rd, cond);
   }
   void Csinc(const Register& rd,
              const Register& rn,
              const Register& rm,
              Condition cond) {
     VIXL_ASSERT(!rd.IsZero());
-    VIXL_ASSERT(!rn.IsZero());
-    VIXL_ASSERT(!rm.IsZero());
+    // The VIXL source code contains these assertions, but the AArch64 ISR
+    // explicitly permits the use of zero registers. CSET itself is defined
+    // in terms of CSINC with WZR/XZR.
+    //
+    // VIXL_ASSERT(!rn.IsZero());
+    // VIXL_ASSERT(!rm.IsZero());
     VIXL_ASSERT((cond != al) && (cond != nv));
     SingleEmissionCheckScope guard(this);
     csinc(rd, rn, rm, cond);
   }
   void Csinv(const Register& rd,
              const Register& rn,
              const Register& rm,
              Condition cond) {