Bug 569819 - Fix nanojit compilation failure on mingw-w64. r=edwsmith
authorJacek Caban <jacek@codeweavers.com>
Fri, 25 Jun 2010 15:59:05 +0200
changeset 48597 6bba024e5fc8a3b1d1ce9720f58819f450203647
parent 48596 61ca032584fe419486a627e80ee66cbe418a9968
child 48598 4de031f4788f851c9ac8e51162dfbf9687b011b2
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reviewersedwsmith
bugs569819
milestone2.0b2pre
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Bug 569819 - Fix nanojit compilation failure on mingw-w64. r=edwsmith
js/src/nanojit/Assembler.cpp
js/src/nanojit/Native.h
js/src/nanojit/NativeX64.h
--- a/js/src/nanojit/Assembler.cpp
+++ b/js/src/nanojit/Assembler.cpp
@@ -819,17 +819,17 @@ namespace nanojit
         // we are done producing the exit logic for the guard so demark where our exit block code begins
         NIns* jmpTarget = _nIns;     // target in exit path for our mainline conditional jump
 
         // swap back pointers, effectively storing the last location used in the exit path
         swapCodeChunks();
         _inExit = false;
 
         //verbose_only( verbose_outputf("         LIR_xt/xf swapCodeChunks, _nIns is now %08X(%08X), _nExitIns is now %08X(%08X)",_nIns, *_nIns,_nExitIns,*_nExitIns) );
-        verbose_only( verbose_outputf("%010lx:", (unsigned long)jmpTarget);)
+        verbose_only( verbose_outputf("%p:", jmpTarget);)
         verbose_only( verbose_outputf("----------------------------------- ## BEGIN exit block (LIR_xt|LIR_xf)") );
 
 #ifdef NANOJIT_IA32
         NanoAssertMsgf(_fpuStkDepth == _sv_fpuStkDepth, "LIR_xtf, _fpuStkDepth=%d, expect %d",_fpuStkDepth, _sv_fpuStkDepth);
         debug_only( _fpuStkDepth = _sv_fpuStkDepth; _sv_fpuStkDepth = 9999; )
 #endif
 
         return jmpTarget;
--- a/js/src/nanojit/Native.h
+++ b/js/src/nanojit/Native.h
@@ -147,17 +147,17 @@ namespace nanojit {
         #define gpn(r)                    regNames[(r)]
     #elif defined(NJ_VERBOSE)
         // Used for printing native instructions.  Like Assembler::outputf(),
         // but only outputs if LC_Native is set.  Also prepends the output
         // with the address of the current native instruction.
         #define asm_output(...) do { \
             if (_logc->lcbits & LC_Native) { \
                 outline[0]='\0'; \
-               VMPI_sprintf(outline, "%010lx   ", (unsigned long)_nIns); \
+               VMPI_sprintf(outline, "%p   ", _nIns); \
                 sprintf(&outline[13], ##__VA_ARGS__); \
                 output(); \
             } \
         } while (0) /* no semi */
         #define gpn(r)                  regNames[(r)]
     #else
         #define asm_output(...)
         #define gpn(r)
--- a/js/src/nanojit/NativeX64.h
+++ b/js/src/nanojit/NativeX64.h
@@ -323,17 +323,17 @@ namespace nanojit
         X86_sete    = 0xC0940F0000000003LL, // no-rex version of X64_sete
         X86_setnp   = 0xC09B0F0000000003LL  // no-rex set byte if odd parity (ordered fcmp result) (PF == 0)
     };
 
     typedef uint32_t RegisterMask;
 
     static const RegisterMask GpRegs = 0xffff;
     static const RegisterMask FpRegs = 0xffff0000;
-#ifdef _MSC_VER
+#ifdef _WIN64
     static const RegisterMask SavedRegs = 1<<RBX | 1<<RSI | 1<<RDI | 1<<R12 | 1<<R13 | 1<<R14 | 1<<R15;
     static const int NumSavedRegs = 7; // rbx, rsi, rdi, r12-15
     static const int NumArgRegs = 4;
 #else
     static const RegisterMask SavedRegs = 1<<RBX | 1<<R12 | 1<<R13 | 1<<R14 | 1<<R15;
     static const int NumSavedRegs = 5; // rbx, r12-15
     static const int NumArgRegs = 6;
 #endif