Bug 1094855: Add helpers for cmpps; r=sunfish
authorBenjamin Bouvier <benj@benj.me>
Fri, 21 Nov 2014 17:27:35 +0100
changeset 241245 dcd252c4cfadc6c28d2c440a4b97d3824b955cee
parent 241244 8937c8785f74dd7ef92268aa45cfbbd330b2812c
child 241246 f7ba8aa473d3ad6cd9a0906072806f76386302a5
push idunknown
push userunknown
push dateunknown
reviewerssunfish
bugs1094855
milestone36.0a1
Bug 1094855: Add helpers for cmpps; r=sunfish
js/src/jit/shared/Assembler-x86-shared.h
js/src/jit/shared/BaseAssembler-x86-shared.h
js/src/jit/shared/CodeGenerator-x86-shared.cpp
--- a/js/src/jit/shared/Assembler-x86-shared.h
+++ b/js/src/jit/shared/Assembler-x86-shared.h
@@ -1686,16 +1686,31 @@ class AssemblerX86Shared : public Assemb
             break;
           case Operand::MEM_ADDRESS32:
             masm.cmpps_mr(src.address(), dest.code(), order);
             break;
           default:
             MOZ_CRASH("unexpected operand kind");
         }
     }
+    void cmpeqps(const Operand &src, FloatRegister dest) {
+        cmpps(src, dest, X86Assembler::ConditionCmp_EQ);
+    }
+    void cmpltps(const Operand &src, FloatRegister dest) {
+        cmpps(src, dest, X86Assembler::ConditionCmp_LT);
+    }
+    void cmpleps(const Operand &src, FloatRegister dest) {
+        cmpps(src, dest, X86Assembler::ConditionCmp_LE);
+    }
+    void cmpunordps(const Operand &src, FloatRegister dest) {
+        cmpps(src, dest, X86Assembler::ConditionCmp_UNORD);
+    }
+    void cmpneqps(const Operand &src, FloatRegister dest) {
+        cmpps(src, dest, X86Assembler::ConditionCmp_NEQ);
+    }
     void rcpps(const Operand &src, FloatRegister dest) {
         MOZ_ASSERT(HasSSE2());
         switch (src.kind()) {
           case Operand::FPREG:
             masm.rcpps_rr(src.fpu(), dest.code());
             break;
           case Operand::MEM_REG_DISP:
             masm.rcpps_mr(src.disp(), src.base(), dest.code());
--- a/js/src/jit/shared/BaseAssembler-x86-shared.h
+++ b/js/src/jit/shared/BaseAssembler-x86-shared.h
@@ -192,16 +192,28 @@ public:
         ConditionGE,
         ConditionLE,
         ConditionG,
 
         ConditionC  = ConditionB,
         ConditionNC = ConditionAE
     } Condition;
 
+    // Conditions for CMP instructions (CMPSS, CMPSD, CMPPS, CMPPD, etc).
+    typedef enum {
+        ConditionCmp_EQ    = 0x0,
+        ConditionCmp_LT    = 0x1,
+        ConditionCmp_LE    = 0x2,
+        ConditionCmp_UNORD = 0x3,
+        ConditionCmp_NEQ   = 0x4,
+        ConditionCmp_NLT   = 0x5,
+        ConditionCmp_NLE   = 0x6,
+        ConditionCmp_ORD   = 0x7,
+    } ConditionCmp;
+
     static const char* nameCC(Condition cc)
     {
         static const char* const names[16]
           = { "o ", "no", "b ", "ae", "e ", "ne", "be", "a ",
               "s ", "ns", "p ", "np", "l ", "ge", "le", "g " };
         int ix = (int)cc;
         return (ix < 0 || ix > 15) ? "??" : names[ix];
     }
--- a/js/src/jit/shared/CodeGenerator-x86-shared.cpp
+++ b/js/src/jit/shared/CodeGenerator-x86-shared.cpp
@@ -2715,26 +2715,26 @@ CodeGeneratorX86Shared::visitSimdBinaryC
 {
     FloatRegister lhs = ToFloatRegister(ins->lhs());
     Operand rhs = ToOperand(ins->rhs());
     MOZ_ASSERT(ToFloatRegister(ins->output()) == lhs);
 
     MSimdBinaryComp::Operation op = ins->operation();
     switch (op) {
       case MSimdBinaryComp::equal:
-        masm.cmpps(rhs, lhs, 0x0);
+        masm.cmpeqps(rhs, lhs);
         return true;
       case MSimdBinaryComp::lessThan:
-        masm.cmpps(rhs, lhs, 0x1);
+        masm.cmpltps(rhs, lhs);
         return true;
       case MSimdBinaryComp::lessThanOrEqual:
-        masm.cmpps(rhs, lhs, 0x2);
+        masm.cmpleps(rhs, lhs);
         return true;
       case MSimdBinaryComp::notEqual:
-        masm.cmpps(rhs, lhs, 0x4);
+        masm.cmpneqps(rhs, lhs);
         return true;
       case MSimdBinaryComp::greaterThanOrEqual:
       case MSimdBinaryComp::greaterThan:
         // We reverse these before register allocation so that we don't have to
         // copy into and out of temporaries after codegen.
         MOZ_CRASH("lowering should have reversed this");
     }
     MOZ_CRASH("unexpected SIMD op");
@@ -2791,17 +2791,17 @@ CodeGeneratorX86Shared::visitSimdBinaryA
       case MSimdBinaryArith::Mul:
         masm.packedMulFloat32(rhs, lhs);
         return true;
       case MSimdBinaryArith::Div:
         masm.packedDivFloat32(rhs, lhs);
         return true;
       case MSimdBinaryArith::Max: {
         masm.movaps(lhs, ScratchSimdReg);
-        masm.cmpps(rhs, ScratchSimdReg, 0x3);
+        masm.cmpunordps(rhs, ScratchSimdReg);
 
         FloatRegister tmp = ToFloatRegister(ins->temp());
         masm.movaps(rhs, tmp);
         masm.maxps(Operand(lhs), tmp);
         masm.maxps(rhs, lhs);
 
         masm.andps(tmp, lhs);
         masm.orps(ScratchSimdReg, lhs); // or in the all-ones NaNs