--- a/js/src/jit/shared/BaseAssembler-x86-shared.h
+++ b/js/src/jit/shared/BaseAssembler-x86-shared.h
@@ -1887,21 +1887,31 @@ public:
 
     void movq_i64r(int64_t imm, RegisterID dst)
     {
         spew("movabsq    $0x%" PRIx64 ", %s", imm, GPReg64Name(dst));
         m_formatter.oneByteOp64(OP_MOV_EAXIv, dst);
         m_formatter.immediate64(imm);
     }
 
-    void movsxd_rr(RegisterID src, RegisterID dst)
-    {
-        spew("movsxd     %s, %s", GPReg32Name(src), GPReg64Name(dst));
+    void movslq_rr(RegisterID src, RegisterID dst)
+    {
+        spew("movslq     %s, %s", GPReg32Name(src), GPReg64Name(dst));
         m_formatter.oneByteOp64(OP_MOVSXD_GvEv, src, dst);
     }
+    void movslq_mr(int32_t offset, RegisterID base, RegisterID dst)
+    {
+        spew("movslq     " MEM_ob ", %s", ADDR_ob(offset, base), GPReg64Name(dst));
+        m_formatter.oneByteOp64(OP_MOVSXD_GvEv, offset, base, dst);
+    }
+    void movslq_mr(int32_t offset, RegisterID base, RegisterID index, int scale, RegisterID dst)
+    {
+        spew("movslq     " MEM_obs ", %s", ADDR_obs(offset, base, index, scale), GPReg64Name(dst));
+        m_formatter.oneByteOp64(OP_MOVSXD_GvEv, offset, base, index, scale, dst);
+    }
 
     MOZ_WARN_UNUSED_RESULT JmpSrc
     movl_ripr(RegisterID dst)
     {
         m_formatter.oneByteRipOp(OP_MOV_GvEv, 0, (RegisterID)dst);
         JmpSrc label(m_formatter.size());
         spew("movl       " MEM_o32r ", %s", ADDR_o32r(label.offset()), GPReg32Name(dst));
         return label;

--- a/js/src/jit/x64/Assembler-x64.h
+++ b/js/src/jit/x64/Assembler-x64.h
@@ -407,16 +407,32 @@ class Assembler : public AssemblerX86Sha
     void movq(Register src, Register dest) {
         masm.movq_rr(src.code(), dest.code());
     }
 
     void xchgq(Register src, Register dest) {
         masm.xchgq_rr(src.code(), dest.code());
     }
 
+    void movslq(Register src, Register dest) {
+        masm.movslq_rr(src.code(), dest.code());
+    }
+    void movslq(const Operand &src, Register dest) {
+        switch (src.kind()) {
+          case Operand::MEM_REG_DISP:
+            masm.movslq_mr(src.disp(), src.base(), dest.code());
+            break;
+          case Operand::MEM_SCALE:
+            masm.movslq_mr(src.disp(), src.base(), src.index(), src.scale(), dest.code());
+            break;
+          default:
+            MOZ_CRASH("unexpected operand kind");
+        }
+    }
+
     void andq(Register src, Register dest) {
         masm.andq_rr(src.code(), dest.code());
     }
     void andq(Imm32 imm, Register dest) {
         masm.andq_ir(imm.value, dest.code());
     }
     void andq(const Operand &src, Register dest) {
         switch (src.kind()) {