Bug 1528597 - ARM64: Fix CodeGenerator::visiShiftI Ursh case doing more than other architecture and baseline. r=sstangl
authorNicolas B. Pierron <nicolas.b.pierron@nbp.name>
Fri, 01 Mar 2019 16:14:42 +0000
changeset 519842 e4bda8b288b31ebcf537a1764c6f166cee5c3fb5
parent 519841 6933acee1ad9aba811d05eb9d820d9397f45bd2a
child 519843 ff07a2a59bb0b6df5382f36fc661fa9b7dd46d30
push id10862
push userffxbld-merge
push dateMon, 11 Mar 2019 13:01:11 +0000
treeherdermozilla-beta@a2e7f5c935da [default view] [failures only]
perfherder[talos] [build metrics] [platform microbench] (compared to previous push)
reviewerssstangl
bugs1528597
milestone67.0a1
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Bug 1528597 - ARM64: Fix CodeGenerator::visiShiftI Ursh case doing more than other architecture and baseline. r=sstangl Differential Revision: https://phabricator.services.mozilla.com/D21385
js/src/jit-test/tests/ion/ursh-sign-bug1528597.js
js/src/jit/arm64/CodeGenerator-arm64.cpp
new file mode 100644
--- /dev/null
+++ b/js/src/jit-test/tests/ion/ursh-sign-bug1528597.js
@@ -0,0 +1,8 @@
+setJitCompilerOption('ion.enable', 1);
+function g(x) {
+    for (let i = 0; i < 2; ++i) {
+        var y = x[i];
+        print(y >>> y);
+    }
+}
+g([2147483649, -2147483648]);
--- a/js/src/jit/arm64/CodeGenerator-arm64.cpp
+++ b/js/src/jit/arm64/CodeGenerator-arm64.cpp
@@ -702,21 +702,18 @@ void CodeGenerator::visitShiftI(LShiftI*
         break;
       case JSOP_RSH:
         masm.Asr(dest, lhs, rhsreg);
         break;
       case JSOP_URSH:
         masm.Lsr(dest, lhs, rhsreg);
         if (ins->mir()->toUrsh()->fallible()) {
           /// x >>> 0 can overflow.
-          Label nonzero;
-          masm.Cbnz(rhsreg, &nonzero);
           masm.Cmp(dest, Operand(0));
           bailoutIf(Assembler::LessThan, ins->snapshot());
-          masm.bind(&nonzero);
         }
         break;
       default:
         MOZ_CRASH("Unexpected shift op");
     }
   }
 }