bug 809306 - fix a bunch of static initializers caused by ion monkey's assembler headers r=dvander
authorTrevor Saunders <trev.saunders@gmail.com>
Fri, 07 Jun 2013 15:49:03 -0400
changeset 146590 e213c2a01ec284be2e37bc20acb8c6cf43498fa5
parent 146589 1f7059b5a6c6c53447ef95d25e71a87b0c444dd2
child 146591 5f243d3f45beae0ed65011357e2f4274a89dd164
push id2697
push userbbajaj@mozilla.com
push dateMon, 05 Aug 2013 18:49:53 +0000
treeherdermozilla-beta@dfec938c7b63 [default view] [failures only]
perfherder[talos] [build metrics] [platform microbench] (compared to previous push)
reviewersdvander
bugs809306
milestone24.0a1
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nightly linux64
nightly mac
nightly win32
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last release without
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bug 809306 - fix a bunch of static initializers caused by ion monkey's assembler headers r=dvander
js/src/ion/RangeAnalysis.cpp
js/src/ion/RangeAnalysis.h
js/src/ion/RegisterAllocator.h
js/src/ion/RegisterSets.h
js/src/ion/arm/Assembler-arm.h
js/src/ion/x64/Assembler-x64.h
js/src/ion/x86/Assembler-x86.h
--- a/js/src/ion/RangeAnalysis.cpp
+++ b/js/src/ion/RangeAnalysis.cpp
@@ -80,21 +80,16 @@ using mozilla::IsNegative;
 // }
 // y = Phi(y1, y4);
 //
 // We insert beta nodes for the purposes of range analysis (they might also be
 // usefully used for other forms of bounds check elimination) and remove them
 // after range analysis is performed. The remaining compiler phases do not ever
 // encounter beta nodes.
 
-RangeAnalysis::RangeAnalysis(MIRGraph &graph)
-  : graph_(graph)
-{
-}
-
 static bool
 IsDominatedUse(MBasicBlock *block, MUse *use)
 {
     MNode *n = use->consumer();
     bool isPhi = n->isDefinition() && n->toDefinition()->isPhi();
 
     if (isPhi)
         return block->dominates(n->block()->getPredecessor(use->index()));
--- a/js/src/ion/RangeAnalysis.h
+++ b/js/src/ion/RangeAnalysis.h
@@ -73,17 +73,18 @@ class RangeAnalysis
     bool blockDominates(MBasicBlock *b, MBasicBlock *b2);
     void replaceDominatedUsesWith(MDefinition *orig, MDefinition *dom,
                                   MBasicBlock *block);
 
   protected:
     MIRGraph &graph_;
 
   public:
-    RangeAnalysis(MIRGraph &graph);
+    MOZ_CONSTEXPR RangeAnalysis(MIRGraph &graph) :
+        graph_(graph) {}
     bool addBetaNobes();
     bool analyze();
     bool removeBetaNobes();
     bool truncate();
 
   private:
     void analyzeLoop(MBasicBlock *header);
     LoopIterationBound *analyzeLoopIterationCount(MBasicBlock *header,
--- a/js/src/ion/RegisterAllocator.h
+++ b/js/src/ion/RegisterAllocator.h
@@ -2,16 +2,18 @@
  * vim: set ts=8 sts=4 et sw=4 tw=99:
  * This Source Code Form is subject to the terms of the Mozilla Public
  * License, v. 2.0. If a copy of the MPL was not distributed with this
  * file, You can obtain one at http://mozilla.org/MPL/2.0/. */
 
 #ifndef js_ion_registerallocator_h__
 #define js_ion_registerallocator_h__
 
+#include "mozilla/Attributes.h"
+
 #include "Ion.h"
 #include "MIR.h"
 #include "MIRGraph.h"
 #include "InlineList.h"
 #include "LIR.h"
 #include "Lowering.h"
 
 // Generic structures and functions for use by register allocators.
@@ -135,17 +137,17 @@ struct AllocationIntegrityState
 // this instruction, it can be clobbered in the output". Just having ranges
 // of instruction IDs is insufficiently expressive to denote all possibilities.
 // This class solves this issue by associating an extra bit with the instruction
 // ID which indicates whether the position is the input half or output half of
 // an instruction.
 class CodePosition
 {
   private:
-    CodePosition(const uint32_t &bits)
+    MOZ_CONSTEXPR CodePosition(const uint32_t &bits)
       : bits_(bits)
     { }
 
     static const unsigned int INSTRUCTION_SHIFT = 1;
     static const unsigned int SUBPOSITION_MASK = 1;
     uint32_t bits_;
 
   public:
@@ -154,17 +156,17 @@ class CodePosition
 
     // This is the half of the instruction this code position represents, as
     // described in the huge comment above.
     enum SubPosition {
         INPUT,
         OUTPUT
     };
 
-    CodePosition() : bits_(0)
+    MOZ_CONSTEXPR CodePosition() : bits_(0)
     { }
 
     CodePosition(uint32_t instruction, SubPosition where) {
         JS_ASSERT(instruction < 0x80000000u);
         JS_ASSERT(((uint32_t)where & SUBPOSITION_MASK) == (uint32_t)where);
         bits_ = (instruction << INSTRUCTION_SHIFT) | (uint32_t)where;
     }
 
--- a/js/src/ion/RegisterSets.h
+++ b/js/src/ion/RegisterSets.h
@@ -87,17 +87,17 @@ struct AnyRegister {
 // platforms, two registers on 32 bit platforms.
 class ValueOperand
 {
 #if defined(JS_NUNBOX32)
     Register type_;
     Register payload_;
 
   public:
-    ValueOperand(Register type, Register payload)
+    MOZ_CONSTEXPR ValueOperand(Register type, Register payload)
       : type_(type), payload_(payload)
     { }
 
     Register typeReg() const {
         return type_;
     }
     Register payloadReg() const {
         return payload_;
@@ -112,17 +112,17 @@ class ValueOperand
     bool operator!=(const ValueOperand &o) const {
         return !(*this == o);
     }
 
 #elif defined(JS_PUNBOX64)
     Register value_;
 
   public:
-    explicit ValueOperand(Register value)
+    explicit MOZ_CONSTEXPR ValueOperand(Register value)
       : value_(value)
     { }
 
     Register valueReg() const {
         return value_;
     }
 
     Register scratchReg() const {
@@ -292,23 +292,23 @@ struct Int32Key {
 };
 
 template <typename T>
 class TypedRegisterSet
 {
     uint32_t bits_;
 
   public:
-    explicit TypedRegisterSet(uint32_t bits)
+    explicit MOZ_CONSTEXPR TypedRegisterSet(uint32_t bits)
       : bits_(bits)
     { }
 
-    TypedRegisterSet() : bits_(0)
+    MOZ_CONSTEXPR TypedRegisterSet() : bits_(0)
     { }
-    TypedRegisterSet(const TypedRegisterSet<T> &set) : bits_(set.bits_)
+    MOZ_CONSTEXPR TypedRegisterSet(const TypedRegisterSet<T> &set) : bits_(set.bits_)
     { }
 
     static inline TypedRegisterSet All() {
         return TypedRegisterSet(T::Codes::AllocatableMask);
     }
     static inline TypedRegisterSet Intersect(const TypedRegisterSet &lhs,
                                              const TypedRegisterSet &rhs) {
         return TypedRegisterSet(lhs.bits_ & rhs.bits_);
@@ -466,17 +466,17 @@ class RegisterSet {
     GeneralRegisterSet gpr_;
     FloatRegisterSet fpu_;
 
     friend class AnyRegisterIterator;
 
   public:
     RegisterSet()
     { }
-    RegisterSet(const GeneralRegisterSet &gpr, const FloatRegisterSet &fpu)
+    MOZ_CONSTEXPR RegisterSet(const GeneralRegisterSet &gpr, const FloatRegisterSet &fpu)
       : gpr_(gpr),
         fpu_(fpu)
     { }
     static inline RegisterSet All() {
         return RegisterSet(GeneralRegisterSet::All(), FloatRegisterSet::All());
     }
     static inline RegisterSet Intersect(const RegisterSet &lhs, const RegisterSet &rhs) {
         return RegisterSet(GeneralRegisterSet::Intersect(lhs.gpr_, rhs.gpr_),
@@ -574,20 +574,20 @@ class RegisterSet {
         if (isFloat)
             return AnyRegister(takeFloat());
         return AnyRegister(takeGeneral());
     }
     void clear() {
         gpr_.clear();
         fpu_.clear();
     }
-    GeneralRegisterSet gprs() const {
+    MOZ_CONSTEXPR GeneralRegisterSet gprs() const {
         return gpr_;
     }
-    FloatRegisterSet fpus() const {
+    MOZ_CONSTEXPR FloatRegisterSet fpus() const {
         return fpu_;
     }
     bool operator ==(const RegisterSet &other) const {
         return other.gpr_ == gpr_ && other.fpu_ == fpu_;
     }
 
     void maybeTake(Register reg) {
         if (gpr_.has(reg))
--- a/js/src/ion/arm/Assembler-arm.h
+++ b/js/src/ion/arm/Assembler-arm.h
@@ -2,16 +2,17 @@
  * vim: set ts=8 sts=4 et sw=4 tw=99:
  * This Source Code Form is subject to the terms of the Mozilla Public
  * License, v. 2.0. If a copy of the MPL was not distributed with this
  * file, You can obtain one at http://mozilla.org/MPL/2.0/. */
 
 #ifndef jsion_cpu_arm_assembler_h__
 #define jsion_cpu_arm_assembler_h__
 
+#include "mozilla/Attributes.h"
 #include "mozilla/MathAlgorithms.h"
 #include "mozilla/Util.h"
 
 #include "ion/shared/Assembler-shared.h"
 #include "assembler/assembler/AssemblerBufferWithConstantPool.h"
 #include "ion/CompactBuffer.h"
 #include "ion/IonCode.h"
 #include "ion/arm/Architecture-arm.h"
@@ -21,54 +22,54 @@ namespace js {
 namespace ion {
 
 //NOTE: there are duplicates in this list!
 // sometimes we want to specifically refer to the
 // link register as a link register (bl lr is much
 // clearer than bl r14).  HOWEVER, this register can
 // easily be a gpr when it is not busy holding the return
 // address.
-static const Register r0  = { Registers::r0 };
-static const Register r1  = { Registers::r1 };
-static const Register r2  = { Registers::r2 };
-static const Register r3  = { Registers::r3 };
-static const Register r4  = { Registers::r4 };
-static const Register r5  = { Registers::r5 };
-static const Register r6  = { Registers::r6 };
-static const Register r7  = { Registers::r7 };
-static const Register r8  = { Registers::r8 };
-static const Register r9  = { Registers::r9 };
-static const Register r10 = { Registers::r10 };
-static const Register r11 = { Registers::r11 };
-static const Register r12 = { Registers::ip };
-static const Register ip  = { Registers::ip };
-static const Register sp  = { Registers::sp };
-static const Register r14 = { Registers::lr };
-static const Register lr  = { Registers::lr };
-static const Register pc  = { Registers::pc };
+static const MOZ_CONSTEXPR Register r0  = { Registers::r0 };
+static const MOZ_CONSTEXPR Register r1  = { Registers::r1 };
+static const MOZ_CONSTEXPR Register r2  = { Registers::r2 };
+static const MOZ_CONSTEXPR Register r3  = { Registers::r3 };
+static const MOZ_CONSTEXPR Register r4  = { Registers::r4 };
+static const MOZ_CONSTEXPR Register r5  = { Registers::r5 };
+static const MOZ_CONSTEXPR Register r6  = { Registers::r6 };
+static const MOZ_CONSTEXPR Register r7  = { Registers::r7 };
+static const MOZ_CONSTEXPR Register r8  = { Registers::r8 };
+static const MOZ_CONSTEXPR Register r9  = { Registers::r9 };
+static const MOZ_CONSTEXPR Register r10 = { Registers::r10 };
+static const MOZ_CONSTEXPR Register r11 = { Registers::r11 };
+static const MOZ_CONSTEXPR Register r12 = { Registers::ip };
+static const MOZ_CONSTEXPR Register ip  = { Registers::ip };
+static const MOZ_CONSTEXPR Register sp  = { Registers::sp };
+static const MOZ_CONSTEXPR Register r14 = { Registers::lr };
+static const MOZ_CONSTEXPR Register lr  = { Registers::lr };
+static const MOZ_CONSTEXPR Register pc  = { Registers::pc };
 
-static const Register ScratchRegister = {Registers::ip};
+static const MOZ_CONSTEXPR Register ScratchRegister = {Registers::ip};
 
-static const Register OsrFrameReg = r3;
-static const Register ArgumentsRectifierReg = r8;
-static const Register CallTempReg0 = r5;
-static const Register CallTempReg1 = r6;
-static const Register CallTempReg2 = r7;
-static const Register CallTempReg3 = r8;
-static const Register CallTempReg4 = r0;
-static const Register CallTempReg5 = r1;
-static const Register CallTempReg6 = r2;
+static const MOZ_CONSTEXPR Register OsrFrameReg = r3;
+static const MOZ_CONSTEXPR Register ArgumentsRectifierReg = r8;
+static const MOZ_CONSTEXPR Register CallTempReg0 = r5;
+static const MOZ_CONSTEXPR Register CallTempReg1 = r6;
+static const MOZ_CONSTEXPR Register CallTempReg2 = r7;
+static const MOZ_CONSTEXPR Register CallTempReg3 = r8;
+static const MOZ_CONSTEXPR Register CallTempReg4 = r0;
+static const MOZ_CONSTEXPR Register CallTempReg5 = r1;
+static const MOZ_CONSTEXPR Register CallTempReg6 = r2;
 
-static const Register IntArgReg0 = r0;
-static const Register IntArgReg1 = r1;
-static const Register IntArgReg2 = r2;
-static const Register IntArgReg3 = r3;
-static const Register GlobalReg = r10;
-static const Register HeapReg = r11;
-static const Register CallTempNonArgRegs[] = { r5, r6, r7, r8 };
+static const MOZ_CONSTEXPR Register IntArgReg0 = r0;
+static const MOZ_CONSTEXPR Register IntArgReg1 = r1;
+static const MOZ_CONSTEXPR Register IntArgReg2 = r2;
+static const MOZ_CONSTEXPR Register IntArgReg3 = r3;
+static const MOZ_CONSTEXPR Register GlobalReg = r10;
+static const MOZ_CONSTEXPR Register HeapReg = r11;
+static const MOZ_CONSTEXPR Register CallTempNonArgRegs[] = { r5, r6, r7, r8 };
 static const uint32_t NumCallTempNonArgRegs =
     mozilla::ArrayLength(CallTempNonArgRegs);
 class ABIArgGenerator
 {
 #if defined(JS_CPU_ARM_HARDFP)
     unsigned intRegIndex_;
     unsigned floatRegIndex_;
 #else
@@ -82,47 +83,47 @@ class ABIArgGenerator
     ABIArg next(MIRType argType);
     ABIArg &current() { return current_; }
     uint32_t stackBytesConsumedSoFar() const { return stackOffset_; }
     static const Register NonArgReturnVolatileReg0;
     static const Register NonArgReturnVolatileReg1;
 
 };
 
-static const Register PreBarrierReg = r1;
+static const MOZ_CONSTEXPR Register PreBarrierReg = r1;
 
-static const Register InvalidReg = { Registers::invalid_reg };
-static const FloatRegister InvalidFloatReg = { FloatRegisters::invalid_freg };
+static const MOZ_CONSTEXPR Register InvalidReg = { Registers::invalid_reg };
+static const MOZ_CONSTEXPR FloatRegister InvalidFloatReg = { FloatRegisters::invalid_freg };
 
-static const Register JSReturnReg_Type = r3;
-static const Register JSReturnReg_Data = r2;
-static const Register StackPointer = sp;
-static const Register FramePointer = InvalidReg;
-static const Register ReturnReg = r0;
-static const FloatRegister ReturnFloatReg = { FloatRegisters::d0 };
-static const FloatRegister ScratchFloatReg = { FloatRegisters::d1 };
+static const MOZ_CONSTEXPR Register JSReturnReg_Type = r3;
+static const MOZ_CONSTEXPR Register JSReturnReg_Data = r2;
+static const MOZ_CONSTEXPR Register StackPointer = sp;
+static const MOZ_CONSTEXPR Register FramePointer = InvalidReg;
+static const MOZ_CONSTEXPR Register ReturnReg = r0;
+static const MOZ_CONSTEXPR FloatRegister ReturnFloatReg = { FloatRegisters::d0 };
+static const MOZ_CONSTEXPR FloatRegister ScratchFloatReg = { FloatRegisters::d1 };
 
-static const FloatRegister NANReg = { FloatRegisters::d15 };
+static const MOZ_CONSTEXPR FloatRegister NANReg = { FloatRegisters::d15 };
 
-static const FloatRegister d0  = {FloatRegisters::d0};
-static const FloatRegister d1  = {FloatRegisters::d1};
-static const FloatRegister d2  = {FloatRegisters::d2};
-static const FloatRegister d3  = {FloatRegisters::d3};
-static const FloatRegister d4  = {FloatRegisters::d4};
-static const FloatRegister d5  = {FloatRegisters::d5};
-static const FloatRegister d6  = {FloatRegisters::d6};
-static const FloatRegister d7  = {FloatRegisters::d7};
-static const FloatRegister d8  = {FloatRegisters::d8};
-static const FloatRegister d9  = {FloatRegisters::d9};
-static const FloatRegister d10 = {FloatRegisters::d10};
-static const FloatRegister d11 = {FloatRegisters::d11};
-static const FloatRegister d12 = {FloatRegisters::d12};
-static const FloatRegister d13 = {FloatRegisters::d13};
-static const FloatRegister d14 = {FloatRegisters::d14};
-static const FloatRegister d15 = {FloatRegisters::d15};
+static const MOZ_CONSTEXPR FloatRegister d0  = {FloatRegisters::d0};
+static const MOZ_CONSTEXPR FloatRegister d1  = {FloatRegisters::d1};
+static const MOZ_CONSTEXPR FloatRegister d2  = {FloatRegisters::d2};
+static const MOZ_CONSTEXPR FloatRegister d3  = {FloatRegisters::d3};
+static const MOZ_CONSTEXPR FloatRegister d4  = {FloatRegisters::d4};
+static const MOZ_CONSTEXPR FloatRegister d5  = {FloatRegisters::d5};
+static const MOZ_CONSTEXPR FloatRegister d6  = {FloatRegisters::d6};
+static const MOZ_CONSTEXPR FloatRegister d7  = {FloatRegisters::d7};
+static const MOZ_CONSTEXPR FloatRegister d8  = {FloatRegisters::d8};
+static const MOZ_CONSTEXPR FloatRegister d9  = {FloatRegisters::d9};
+static const MOZ_CONSTEXPR FloatRegister d10 = {FloatRegisters::d10};
+static const MOZ_CONSTEXPR FloatRegister d11 = {FloatRegisters::d11};
+static const MOZ_CONSTEXPR FloatRegister d12 = {FloatRegisters::d12};
+static const MOZ_CONSTEXPR FloatRegister d13 = {FloatRegisters::d13};
+static const MOZ_CONSTEXPR FloatRegister d14 = {FloatRegisters::d14};
+static const MOZ_CONSTEXPR FloatRegister d15 = {FloatRegisters::d15};
 
 // For maximal awesomeness, 8 should be sufficent.
 // ldrd/strd (dual-register load/store) operate in a single cycle
 // when the address they are dealing with is 8 byte aligned.
 // Also, the ARM abi wants the stack to be 8 byte aligned at
 // function boundaries.  I'm trying to make sure this is always true.
 static const uint32_t StackAlignment = 8;
 static const uint32_t CodeAlignment = 8;
--- a/js/src/ion/x64/Assembler-x64.h
+++ b/js/src/ion/x64/Assembler-x64.h
@@ -10,128 +10,128 @@
 #include "ion/shared/Assembler-shared.h"
 #include "ion/CompactBuffer.h"
 #include "ion/IonCode.h"
 #include "mozilla/Util.h"
 
 namespace js {
 namespace ion {
 
-static const Register rax = { JSC::X86Registers::eax };
-static const Register rbx = { JSC::X86Registers::ebx };
-static const Register rcx = { JSC::X86Registers::ecx };
-static const Register rdx = { JSC::X86Registers::edx };
-static const Register rsi = { JSC::X86Registers::esi };
-static const Register rdi = { JSC::X86Registers::edi };
-static const Register rbp = { JSC::X86Registers::ebp };
-static const Register r8  = { JSC::X86Registers::r8  };
-static const Register r9  = { JSC::X86Registers::r9  };
-static const Register r10 = { JSC::X86Registers::r10 };
-static const Register r11 = { JSC::X86Registers::r11 };
-static const Register r12 = { JSC::X86Registers::r12 };
-static const Register r13 = { JSC::X86Registers::r13 };
-static const Register r14 = { JSC::X86Registers::r14 };
-static const Register r15 = { JSC::X86Registers::r15 };
-static const Register rsp = { JSC::X86Registers::esp };
+static const MOZ_CONSTEXPR Register rax = { JSC::X86Registers::eax };
+static const MOZ_CONSTEXPR Register rbx = { JSC::X86Registers::ebx };
+static const MOZ_CONSTEXPR Register rcx = { JSC::X86Registers::ecx };
+static const MOZ_CONSTEXPR Register rdx = { JSC::X86Registers::edx };
+static const MOZ_CONSTEXPR Register rsi = { JSC::X86Registers::esi };
+static const MOZ_CONSTEXPR Register rdi = { JSC::X86Registers::edi };
+static const MOZ_CONSTEXPR Register rbp = { JSC::X86Registers::ebp };
+static const MOZ_CONSTEXPR Register r8  = { JSC::X86Registers::r8  };
+static const MOZ_CONSTEXPR Register r9  = { JSC::X86Registers::r9  };
+static const MOZ_CONSTEXPR Register r10 = { JSC::X86Registers::r10 };
+static const MOZ_CONSTEXPR Register r11 = { JSC::X86Registers::r11 };
+static const MOZ_CONSTEXPR Register r12 = { JSC::X86Registers::r12 };
+static const MOZ_CONSTEXPR Register r13 = { JSC::X86Registers::r13 };
+static const MOZ_CONSTEXPR Register r14 = { JSC::X86Registers::r14 };
+static const MOZ_CONSTEXPR Register r15 = { JSC::X86Registers::r15 };
+static const MOZ_CONSTEXPR Register rsp = { JSC::X86Registers::esp };
 
-static const FloatRegister xmm0 = { JSC::X86Registers::xmm0 };
-static const FloatRegister xmm1 = { JSC::X86Registers::xmm1 };
-static const FloatRegister xmm2 = { JSC::X86Registers::xmm2 };
-static const FloatRegister xmm3 = { JSC::X86Registers::xmm3 };
-static const FloatRegister xmm4 = { JSC::X86Registers::xmm4 };
-static const FloatRegister xmm5 = { JSC::X86Registers::xmm5 };
-static const FloatRegister xmm6 = { JSC::X86Registers::xmm6 };
-static const FloatRegister xmm7 = { JSC::X86Registers::xmm7 };
-static const FloatRegister xmm8 = { JSC::X86Registers::xmm8 };
-static const FloatRegister xmm9 = { JSC::X86Registers::xmm9 };
-static const FloatRegister xmm10 = { JSC::X86Registers::xmm10 };
-static const FloatRegister xmm11 = { JSC::X86Registers::xmm11 };
-static const FloatRegister xmm12 = { JSC::X86Registers::xmm12 };
-static const FloatRegister xmm13 = { JSC::X86Registers::xmm13 };
-static const FloatRegister xmm14 = { JSC::X86Registers::xmm14 };
-static const FloatRegister xmm15 = { JSC::X86Registers::xmm15 };
+static const MOZ_CONSTEXPR FloatRegister xmm0 = { JSC::X86Registers::xmm0 };
+static const MOZ_CONSTEXPR FloatRegister xmm1 = { JSC::X86Registers::xmm1 };
+static const MOZ_CONSTEXPR FloatRegister xmm2 = { JSC::X86Registers::xmm2 };
+static const MOZ_CONSTEXPR FloatRegister xmm3 = { JSC::X86Registers::xmm3 };
+static const MOZ_CONSTEXPR FloatRegister xmm4 = { JSC::X86Registers::xmm4 };
+static const MOZ_CONSTEXPR FloatRegister xmm5 = { JSC::X86Registers::xmm5 };
+static const MOZ_CONSTEXPR FloatRegister xmm6 = { JSC::X86Registers::xmm6 };
+static const MOZ_CONSTEXPR FloatRegister xmm7 = { JSC::X86Registers::xmm7 };
+static const MOZ_CONSTEXPR FloatRegister xmm8 = { JSC::X86Registers::xmm8 };
+static const MOZ_CONSTEXPR FloatRegister xmm9 = { JSC::X86Registers::xmm9 };
+static const MOZ_CONSTEXPR FloatRegister xmm10 = { JSC::X86Registers::xmm10 };
+static const MOZ_CONSTEXPR FloatRegister xmm11 = { JSC::X86Registers::xmm11 };
+static const MOZ_CONSTEXPR FloatRegister xmm12 = { JSC::X86Registers::xmm12 };
+static const MOZ_CONSTEXPR FloatRegister xmm13 = { JSC::X86Registers::xmm13 };
+static const MOZ_CONSTEXPR FloatRegister xmm14 = { JSC::X86Registers::xmm14 };
+static const MOZ_CONSTEXPR FloatRegister xmm15 = { JSC::X86Registers::xmm15 };
 
 // X86-common synonyms.
 static const Register eax = rax;
 static const Register ebx = rbx;
 static const Register ecx = rcx;
 static const Register edx = rdx;
 static const Register esi = rsi;
 static const Register edi = rdi;
 static const Register ebp = rbp;
 static const Register esp = rsp;
 
-static const Register InvalidReg = { JSC::X86Registers::invalid_reg };
-static const FloatRegister InvalidFloatReg = { JSC::X86Registers::invalid_xmm };
+static const MOZ_CONSTEXPR Register InvalidReg = { JSC::X86Registers::invalid_reg };
+static const MOZ_CONSTEXPR FloatRegister InvalidFloatReg = { JSC::X86Registers::invalid_xmm };
 
 static const Register StackPointer = rsp;
 static const Register FramePointer = rbp;
-static const Register JSReturnReg = rcx;
+static const MOZ_CONSTEXPR Register JSReturnReg = rcx;
 // Avoid, except for assertions.
-static const Register JSReturnReg_Type = JSReturnReg;
-static const Register JSReturnReg_Data = JSReturnReg;
+static const MOZ_CONSTEXPR Register JSReturnReg_Type = JSReturnReg;
+static const MOZ_CONSTEXPR Register JSReturnReg_Data = JSReturnReg;
 
-static const Register ReturnReg = rax;
-static const Register ScratchReg = r11;
-static const Register HeapReg = r15;
-static const FloatRegister ReturnFloatReg = xmm0;
-static const FloatRegister ScratchFloatReg = xmm15;
+static const MOZ_CONSTEXPR Register ReturnReg = rax;
+static const MOZ_CONSTEXPR Register ScratchReg = r11;
+static const MOZ_CONSTEXPR Register HeapReg = r15;
+static const MOZ_CONSTEXPR FloatRegister ReturnFloatReg = xmm0;
+static const MOZ_CONSTEXPR FloatRegister ScratchFloatReg = xmm15;
 
-static const Register ArgumentsRectifierReg = r8;
-static const Register CallTempReg0 = rax;
-static const Register CallTempReg1 = rdi;
-static const Register CallTempReg2 = rbx;
-static const Register CallTempReg3 = rcx;
-static const Register CallTempReg4 = rsi;
-static const Register CallTempReg5 = rdx;
-static const Register CallTempReg6 = rbp;
+static const MOZ_CONSTEXPR Register ArgumentsRectifierReg = r8;
+static const MOZ_CONSTEXPR Register CallTempReg0 = rax;
+static const MOZ_CONSTEXPR Register CallTempReg1 = rdi;
+static const MOZ_CONSTEXPR Register CallTempReg2 = rbx;
+static const MOZ_CONSTEXPR Register CallTempReg3 = rcx;
+static const MOZ_CONSTEXPR Register CallTempReg4 = rsi;
+static const MOZ_CONSTEXPR Register CallTempReg5 = rdx;
+static const MOZ_CONSTEXPR Register CallTempReg6 = rbp;
 
 // Different argument registers for WIN64
 #if defined(_WIN64)
-static const Register IntArgReg0 = rcx;
-static const Register IntArgReg1 = rdx;
-static const Register IntArgReg2 = r8;
-static const Register IntArgReg3 = r9;
-static const uint32_t NumIntArgRegs = 4;
-static const Register IntArgRegs[NumIntArgRegs] = { rcx, rdx, r8, r9 };
+static const MOZ_CONSTEXPR Register IntArgReg0 = rcx;
+static constMOZ_CONSTEXPRconstexpr Register IntArgReg1 = rdx;
+static const MOZ_CONSTEXPR Register IntArgReg2 = r8;
+static const MOZ_CONSTEXPR Register IntArgReg3 = r9;
+static constMOZ_CONSTEXPRuint32_t NumIntArgRegs = 4;
+static const MOZ_CONSTEXPR Register IntArgRegs[NumIntArgRegs] = { rcx, rdx, r8, r9 };
 
-static const Register CallTempNonArgRegs[] = { rax, rdi, rbx, rsi };
+static const MOZ_CONSTEXPR Register CallTempNonArgRegs[] = { rax, rdi, rbx, rsi };
 static const uint32_t NumCallTempNonArgRegs =
     mozilla::ArrayLength(CallTempNonArgRegs);
 
-static const FloatRegister FloatArgReg0 = xmm0;
-static const FloatRegister FloatArgReg1 = xmm1;
-static const FloatRegister FloatArgReg2 = xmm2;
-static const FloatRegister FloatArgReg3 = xmm3;
+static const MOZ_CONSTEXPR FloatRegister FloatArgReg0 = xmm0;
+static const MOZ_CONSTEXPR FloatRegister FloatArgReg1 = xmm1;
+static const MOZ_CONSTEXPR FloatRegister FloatArgReg2 = xmm2;
+static const MOZ_CONSTEXPR FloatRegister FloatArgReg3 = xmm3;
 static const uint32_t NumFloatArgRegs = 4;
 static const FloatRegister FloatArgRegs[NumFloatArgRegs] = { xmm0, xmm1, xmm2, xmm3 };
 #else
-static const Register IntArgReg0 = rdi;
-static const Register IntArgReg1 = rsi;
-static const Register IntArgReg2 = rdx;
-static const Register IntArgReg3 = rcx;
-static const Register IntArgReg4 = r8;
-static const Register IntArgReg5 = r9;
-static const uint32_t NumIntArgRegs = 6;
-static const Register IntArgRegs[NumIntArgRegs] = { rdi, rsi, rdx, rcx, r8, r9 };
+static const MOZ_CONSTEXPR Register IntArgReg0 = rdi;
+static const MOZ_CONSTEXPR Register IntArgReg1 = rsi;
+static const MOZ_CONSTEXPR Register IntArgReg2 = rdx;
+static const MOZ_CONSTEXPR Register IntArgReg3 = rcx;
+static const MOZ_CONSTEXPR Register IntArgReg4 = r8;
+static const MOZ_CONSTEXPR Register IntArgReg5 = r9;
+static const MOZ_CONSTEXPR uint32_t NumIntArgRegs = 6;
+static const MOZ_CONSTEXPR Register IntArgRegs[NumIntArgRegs] = { rdi, rsi, rdx, rcx, r8, r9 };
 
-static const Register CallTempNonArgRegs[] = { rax, rbx };
+static const MOZ_CONSTEXPR Register CallTempNonArgRegs[] = { rax, rbx };
 static const uint32_t NumCallTempNonArgRegs =
     mozilla::ArrayLength(CallTempNonArgRegs);
 
-static const FloatRegister FloatArgReg0 = xmm0;
-static const FloatRegister FloatArgReg1 = xmm1;
-static const FloatRegister FloatArgReg2 = xmm2;
-static const FloatRegister FloatArgReg3 = xmm3;
-static const FloatRegister FloatArgReg4 = xmm4;
-static const FloatRegister FloatArgReg5 = xmm5;
-static const FloatRegister FloatArgReg6 = xmm6;
-static const FloatRegister FloatArgReg7 = xmm7;
-static const uint32_t NumFloatArgRegs = 8;
-static const FloatRegister FloatArgRegs[NumFloatArgRegs] = { xmm0, xmm1, xmm2, xmm3, xmm4, xmm5, xmm6, xmm7 };
+static const MOZ_CONSTEXPR FloatRegister FloatArgReg0 = xmm0;
+static const MOZ_CONSTEXPR FloatRegister FloatArgReg1 = xmm1;
+static const MOZ_CONSTEXPR FloatRegister FloatArgReg2 = xmm2;
+static const MOZ_CONSTEXPR FloatRegister FloatArgReg3 = xmm3;
+static const MOZ_CONSTEXPR FloatRegister FloatArgReg4 = xmm4;
+static const MOZ_CONSTEXPR FloatRegister FloatArgReg5 = xmm5;
+static const MOZ_CONSTEXPR FloatRegister FloatArgReg6 = xmm6;
+static const MOZ_CONSTEXPR FloatRegister FloatArgReg7 = xmm7;
+static const MOZ_CONSTEXPR uint32_t NumFloatArgRegs = 8;
+static const MOZ_CONSTEXPR FloatRegister FloatArgRegs[NumFloatArgRegs] = { xmm0, xmm1, xmm2, xmm3, xmm4, xmm5, xmm6, xmm7 };
 #endif
 
 class ABIArgGenerator
 {
 #if defined(XP_WIN)
     unsigned regIndex_;
 #else
     unsigned intRegIndex_;
@@ -147,19 +147,19 @@ class ABIArgGenerator
     uint32_t stackBytesConsumedSoFar() const { return stackOffset_; }
 
     // Note: these registers are all guaranteed to be different
     static const Register NonArgReturnVolatileReg0;
     static const Register NonArgReturnVolatileReg1;
     static const Register NonVolatileReg;
 };
 
-static const Register OsrFrameReg = IntArgReg3;
+static const MOZ_CONSTEXPR Register OsrFrameReg = IntArgReg3;
 
-static const Register PreBarrierReg = rdx;
+static const MOZ_CONSTEXPR Register PreBarrierReg = rdx;
 
 // GCC stack is aligned on 16 bytes, but we don't maintain the invariant in
 // jitted code.
 static const uint32_t StackAlignment = 16;
 static const bool StackKeptAligned = false;
 static const uint32_t CodeAlignment = 8;
 static const uint32_t NativeFrameSize = sizeof(void*);
 static const uint32_t AlignmentAtPrologue = sizeof(void*);
@@ -260,17 +260,17 @@ class Operand
 } // namespace js
 
 #include "ion/shared/Assembler-x86-shared.h"
 
 namespace js {
 namespace ion {
 
 // Return operand from a JS -> JS call.
-static const ValueOperand JSReturnOperand = ValueOperand(JSReturnReg);
+static const MOZ_CONSTEXPR ValueOperand JSReturnOperand = ValueOperand(JSReturnReg);
 
 class Assembler : public AssemblerX86Shared
 {
     // x64 jumps may need extra bits of relocation, because a jump may extend
     // beyond the signed 32-bit range. To account for this we add an extended
     // jump table at the bottom of the instruction stream, and if a jump
     // overflows its range, it will redirect here.
     //
--- a/js/src/ion/x86/Assembler-x86.h
+++ b/js/src/ion/x86/Assembler-x86.h
@@ -13,56 +13,56 @@
 #include "ion/IonCode.h"
 #include "mozilla/Util.h"
 
 #include "jsscriptinlines.h"
 
 namespace js {
 namespace ion {
 
-static const Register eax = { JSC::X86Registers::eax };
-static const Register ecx = { JSC::X86Registers::ecx };
-static const Register edx = { JSC::X86Registers::edx };
-static const Register ebx = { JSC::X86Registers::ebx };
-static const Register esp = { JSC::X86Registers::esp };
-static const Register ebp = { JSC::X86Registers::ebp };
-static const Register esi = { JSC::X86Registers::esi };
-static const Register edi = { JSC::X86Registers::edi };
+static const MOZ_CONSTEXPR Register eax = { JSC::X86Registers::eax };
+static const MOZ_CONSTEXPR Register ecx = { JSC::X86Registers::ecx };
+static const MOZ_CONSTEXPR Register edx = { JSC::X86Registers::edx };
+static const MOZ_CONSTEXPR Register ebx = { JSC::X86Registers::ebx };
+static const MOZ_CONSTEXPR Register esp = { JSC::X86Registers::esp };
+static const MOZ_CONSTEXPR Register ebp = { JSC::X86Registers::ebp };
+static const MOZ_CONSTEXPR Register esi = { JSC::X86Registers::esi };
+static const MOZ_CONSTEXPR Register edi = { JSC::X86Registers::edi };
 
-static const FloatRegister xmm0 = { JSC::X86Registers::xmm0 };
-static const FloatRegister xmm1 = { JSC::X86Registers::xmm1 };
-static const FloatRegister xmm2 = { JSC::X86Registers::xmm2 };
-static const FloatRegister xmm3 = { JSC::X86Registers::xmm3 };
-static const FloatRegister xmm4 = { JSC::X86Registers::xmm4 };
-static const FloatRegister xmm5 = { JSC::X86Registers::xmm5 };
-static const FloatRegister xmm6 = { JSC::X86Registers::xmm6 };
-static const FloatRegister xmm7 = { JSC::X86Registers::xmm7 };
+static const MOZ_CONSTEXPR FloatRegister xmm0 = { JSC::X86Registers::xmm0 };
+static const MOZ_CONSTEXPR FloatRegister xmm1 = { JSC::X86Registers::xmm1 };
+static const MOZ_CONSTEXPR FloatRegister xmm2 = { JSC::X86Registers::xmm2 };
+static const MOZ_CONSTEXPR FloatRegister xmm3 = { JSC::X86Registers::xmm3 };
+static const MOZ_CONSTEXPR FloatRegister xmm4 = { JSC::X86Registers::xmm4 };
+static const MOZ_CONSTEXPR FloatRegister xmm5 = { JSC::X86Registers::xmm5 };
+static const MOZ_CONSTEXPR FloatRegister xmm6 = { JSC::X86Registers::xmm6 };
+static const MOZ_CONSTEXPR FloatRegister xmm7 = { JSC::X86Registers::xmm7 };
 
-static const Register InvalidReg = { JSC::X86Registers::invalid_reg };
-static const FloatRegister InvalidFloatReg = { JSC::X86Registers::invalid_xmm };
+static const MOZ_CONSTEXPR Register InvalidReg = { JSC::X86Registers::invalid_reg };
+static const MOZ_CONSTEXPR FloatRegister InvalidFloatReg = { JSC::X86Registers::invalid_xmm };
 
-static const Register JSReturnReg_Type = ecx;
-static const Register JSReturnReg_Data = edx;
-static const Register StackPointer = esp;
-static const Register FramePointer = ebp;
-static const Register ReturnReg = eax;
-static const FloatRegister ReturnFloatReg = xmm0;
-static const FloatRegister ScratchFloatReg = xmm7;
+static const MOZ_CONSTEXPR Register JSReturnReg_Type = ecx;
+static const MOZ_CONSTEXPR Register JSReturnReg_Data = edx;
+static const MOZ_CONSTEXPR Register StackPointer = esp;
+static const MOZ_CONSTEXPR Register FramePointer = ebp;
+static const MOZ_CONSTEXPR Register ReturnReg = eax;
+static const MOZ_CONSTEXPR FloatRegister ReturnFloatReg = xmm0;
+static const MOZ_CONSTEXPR FloatRegister ScratchFloatReg = xmm7;
 
-static const Register ArgumentsRectifierReg = esi;
-static const Register CallTempReg0 = edi;
-static const Register CallTempReg1 = eax;
-static const Register CallTempReg2 = ebx;
-static const Register CallTempReg3 = ecx;
-static const Register CallTempReg4 = esi;
-static const Register CallTempReg5 = edx;
-static const Register CallTempReg6 = ebp;
+static const MOZ_CONSTEXPR Register ArgumentsRectifierReg = esi;
+static const MOZ_CONSTEXPR Register CallTempReg0 = edi;
+static const MOZ_CONSTEXPR Register CallTempReg1 = eax;
+static const MOZ_CONSTEXPR Register CallTempReg2 = ebx;
+static const MOZ_CONSTEXPR Register CallTempReg3 = ecx;
+static const MOZ_CONSTEXPR Register CallTempReg4 = esi;
+static const MOZ_CONSTEXPR Register CallTempReg5 = edx;
+static const MOZ_CONSTEXPR Register CallTempReg6 = ebp;
 
 // We have no arg regs, so our NonArgRegs are just our CallTempReg*
-static const Register CallTempNonArgRegs[] = { edi, eax, ebx, ecx, esi, edx };
+static const MOZ_CONSTEXPR Register CallTempNonArgRegs[] = { edi, eax, ebx, ecx, esi, edx };
 static const uint32_t NumCallTempNonArgRegs =
     mozilla::ArrayLength(CallTempNonArgRegs);
 
 class ABIArgGenerator
 {
     uint32_t stackOffset_;
     ABIArg current_;
 
@@ -73,18 +73,18 @@ class ABIArgGenerator
     uint32_t stackBytesConsumedSoFar() const { return stackOffset_; }
 
     // Note: these registers are all guaranteed to be different
     static const Register NonArgReturnVolatileReg0;
     static const Register NonArgReturnVolatileReg1;
     static const Register NonVolatileReg;
 };
 
-static const Register OsrFrameReg = edx;
-static const Register PreBarrierReg = edx;
+static const MOZ_CONSTEXPR Register OsrFrameReg = edx;
+static const MOZ_CONSTEXPR Register PreBarrierReg = edx;
 
 // GCC stack is aligned on 16 bytes, but we don't maintain the invariant in
 // jitted code.
 #if defined(__GNUC__)
 static const uint32_t StackAlignment = 16;
 #else
 static const uint32_t StackAlignment = 4;
 #endif