Bug 1013906 - Update irregexp to work on MIPS. r=bhackett
authorBranislav Rankov <branislav.rankov@imgtec.com>
Tue, 03 Jun 2014 18:12:36 +0200
changeset 206060 d09bea16045c03dd1fd05d8630a0be6902a587a1
parent 206059 b56930ff7e05d909c0b3932b21f7bd2a527237e7
child 206061 5eea6f492ed5b17df94bdeddc243769dce0f797b
push id3741
push userasasaki@mozilla.com
push dateMon, 21 Jul 2014 20:25:18 +0000
treeherdermozilla-beta@4d6f46f5af68 [default view] [failures only]
perfherder[talos] [build metrics] [platform microbench] (compared to previous push)
reviewersbhackett
bugs1013906
milestone32.0a1
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Bug 1013906 - Update irregexp to work on MIPS. r=bhackett
js/src/irregexp/NativeRegExpMacroAssembler.cpp
--- a/js/src/irregexp/NativeRegExpMacroAssembler.cpp
+++ b/js/src/irregexp/NativeRegExpMacroAssembler.cpp
@@ -91,19 +91,21 @@ NativeRegExpMacroAssembler::NativeRegExp
 
     // Determine the non-volatile registers which might be modified by jitcode.
     for (GeneralRegisterIterator iter(GeneralRegisterSet::NonVolatile()); iter.more(); iter++) {
         Register reg = *iter;
         if (!regs.has(reg))
             savedNonVolatileRegisters.add(reg);
     }
 
-#ifdef JS_CODEGEN_ARM
+#if defined(JS_CODEGEN_ARM)
     // ARM additionally requires that the link register be saved.
     savedNonVolatileRegisters.add(Register::FromCode(Registers::lr));
+#elif defined(JS_CODEGEN_MIPS)
+    savedNonVolatileRegisters.add(Register::FromCode(Registers::ra));
 #endif
 
     masm.jump(&entry_label_);
     masm.bind(&start_label_);
 }
 
 #define SPEW_PREFIX IonSpew_Codegen, "!!! "
 
@@ -388,18 +390,20 @@ NativeRegExpMacroAssembler::GenerateCode
         masm.bind(&stack_overflow_label_);
 
         Label grow_failed;
 
         masm.movePtr(ImmPtr(runtime), temp1);
 
         // Save registers before calling C function
         RegisterSet volatileRegs = RegisterSet::Volatile();
-#ifdef JS_CODEGEN_ARM
+#if defined(JS_CODEGEN_ARM)
         volatileRegs.add(Register::FromCode(Registers::lr));
+#elif defined(JS_CODEGEN_MIPS)
+        volatileRegs.add(Register::FromCode(Registers::ra));
 #endif
         volatileRegs.takeUnchecked(temp0);
         volatileRegs.takeUnchecked(temp1);
         masm.PushRegsInMask(volatileRegs);
 
         masm.setupUnalignedABICall(1, temp0);
         masm.passABIArg(temp1);
         masm.callWithABI(JS_FUNC_TO_DATA_PTR(void *, GrowBacktrackStack));
@@ -810,17 +814,17 @@ NativeRegExpMacroAssembler::CheckBitInTa
 
     JS_ASSERT(mode_ != ASCII); // Ascii case not handled here.
 
     masm.movePtr(ImmPtr(table), temp0);
     masm.move32(Imm32(kTableSize - 1), temp1);
     masm.and32(current_character, temp1);
 
     masm.load8ZeroExtend(BaseIndex(temp0, temp1, TimesOne), temp0);
-    masm.branchTest32(Assembler::NotEqual, temp0, temp0, BranchOrBacktrack(on_bit_set));
+    masm.branchTest32(Assembler::NonZero, temp0, temp0, BranchOrBacktrack(on_bit_set));
 }
 
 void
 NativeRegExpMacroAssembler::Fail()
 {
     IonSpew(SPEW_PREFIX "Fail");
 
     if (!global())
@@ -1223,17 +1227,21 @@ NativeRegExpMacroAssembler::CheckSpecial
       default:
         return false;
     }
 }
 
 bool
 NativeRegExpMacroAssembler::CanReadUnaligned()
 {
+#if defined(JS_CODEGEN_MIPS)
+    return false;
+#else
     return true;
+#endif
 }
 
 const uint8_t
 NativeRegExpMacroAssembler::word_character_map[] =
 {
     0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
     0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
     0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,