Backed out changeset 1f7837e3840d (bug 1406999) for build bustages on MacroAssembler.cpp r=backout on a CLOSED TREE
authorNarcis Beleuzu <nbeleuzu@mozilla.com>
Thu, 21 Dec 2017 07:14:33 +0200
changeset 448871 c6297aca62a422e4a8988a9a8b186e22d737aa99
parent 448870 5a50adabbb1171a696f4c24abd976492e8f84ed8
child 448872 41084549f30fe029c96f19bcd1fbfd6f209df874
child 448953 c6925bd4003d58764a34739838e57d5921769c5d
push id8527
push userCallek@gmail.com
push dateThu, 11 Jan 2018 21:05:50 +0000
treeherdermozilla-beta@95342d212a7a [default view] [failures only]
perfherder[talos] [build metrics] [platform microbench] (compared to previous push)
reviewersbackout
bugs1406999
milestone59.0a1
backs out1f7837e3840d2e1738200c22f8be3b3118fe84b1
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Backed out changeset 1f7837e3840d (bug 1406999) for build bustages on MacroAssembler.cpp r=backout on a CLOSED TREE
js/src/jit/JitFrames.cpp
js/src/jit/MacroAssembler.cpp
js/src/jit/mips-shared/Architecture-mips-shared.h
js/src/jit/mips-shared/Assembler-mips-shared.cpp
js/src/jit/mips-shared/Assembler-mips-shared.h
js/src/jit/mips32/Architecture-mips32.cpp
js/src/jit/mips32/Architecture-mips32.h
js/src/jit/mips32/Assembler-mips32.h
js/src/jit/mips32/CodeGenerator-mips32.cpp
js/src/jit/mips32/MacroAssembler-mips32.cpp
js/src/wasm/WasmStubs.cpp
--- a/js/src/jit/JitFrames.cpp
+++ b/js/src/jit/JitFrames.cpp
@@ -2237,19 +2237,24 @@ MachineState::FromBailout(RegisterDump::
         machine.setRegisterLocation(Register::FromCode(i), &regs[i].r);
 #ifdef JS_CODEGEN_ARM
     float* fbase = (float*)&fpregs[0];
     for (unsigned i = 0; i < FloatRegisters::TotalDouble; i++)
         machine.setRegisterLocation(FloatRegister(i, FloatRegister::Double), &fpregs[i].d);
     for (unsigned i = 0; i < FloatRegisters::TotalSingle; i++)
         machine.setRegisterLocation(FloatRegister(i, FloatRegister::Single), (double*)&fbase[i]);
 #elif defined(JS_CODEGEN_MIPS32)
-    for (unsigned i = 0; i < FloatRegisters::TotalPhys; i++) {
-        machine.setRegisterLocation(FloatRegister::FromIndex(i, FloatRegister::Double), &fpregs[i]);
-        machine.setRegisterLocation(FloatRegister::FromIndex(i, FloatRegister::Single), &fpregs[i]);
+    float* fbase = (float*)&fpregs[0];
+    for (unsigned i = 0; i < FloatRegisters::TotalDouble; i++) {
+        machine.setRegisterLocation(FloatRegister::FromIndex(i, FloatRegister::Double),
+                                    &fpregs[i].d);
+    }
+    for (unsigned i = 0; i < FloatRegisters::TotalSingle; i++) {
+        machine.setRegisterLocation(FloatRegister::FromIndex(i, FloatRegister::Single),
+                                    (double*)&fbase[i]);
     }
 #elif defined(JS_CODEGEN_MIPS64)
     for (unsigned i = 0; i < FloatRegisters::TotalPhys; i++) {
         machine.setRegisterLocation(FloatRegister(i, FloatRegisters::Double), &fpregs[i]);
         machine.setRegisterLocation(FloatRegister(i, FloatRegisters::Single), &fpregs[i]);
     }
 #elif defined(JS_CODEGEN_X86) || defined(JS_CODEGEN_X64)
     for (unsigned i = 0; i < FloatRegisters::TotalPhys; i++) {
--- a/js/src/jit/MacroAssembler.cpp
+++ b/js/src/jit/MacroAssembler.cpp
@@ -1962,17 +1962,17 @@ MacroAssembler::convertValueToFloatingPo
     boolValueToFloatingPoint(value, output, outputType);
     jump(&done);
 
     bind(&isInt32);
     int32ValueToFloatingPoint(value, output, outputType);
     jump(&done);
 
     bind(&isDouble);
-    FloatRegister tmp = output.asDouble();
+    FloatRegister tmp = output;
     if (outputType == MIRType::Float32 && hasMultiAlias())
         tmp = ScratchDoubleReg;
 
     unboxDouble(value, tmp);
     if (outputType == MIRType::Float32)
         convertDoubleToFloat32(tmp, output);
 
     bind(&done);
--- a/js/src/jit/mips-shared/Architecture-mips-shared.h
+++ b/js/src/jit/mips-shared/Architecture-mips-shared.h
@@ -261,79 +261,58 @@ class FloatRegistersMIPSShared
         f26,
         f27,
         f28,
         f29,
         f30,
         f31,
         invalid_freg
     };
-    typedef uint32_t Code;
+    typedef FPRegisterID Code;
     typedef FPRegisterID Encoding;
 
     // Content spilled during bailouts.
     union RegisterContent {
         double d;
     };
 
-    static const char* GetName(Encoding code) {
+    static const char* GetName(Code code) {
         static const char * const Names[] = { "f0", "f1", "f2", "f3",  "f4", "f5",  "f6", "f7",
                                               "f8", "f9",  "f10", "f11", "f12", "f13",
                                               "f14", "f15", "f16", "f17", "f18", "f19",
                                               "f20", "f21", "f22", "f23", "f24", "f25",
                                               "f26", "f27", "f28", "f29", "f30", "f31"};
         return Names[code];
     }
 
-    static const Encoding Invalid = invalid_freg;
+    static const Code Invalid = invalid_freg;
 
-#if defined(JS_CODEGEN_MIPS32)
-    typedef uint32_t SetType;
-#elif defined(JS_CODEGEN_MIPS64)
     typedef uint64_t SetType;
-#endif
 };
 
 template <typename T>
 class TypedRegisterSet;
 
 class FloatRegisterMIPSShared
 {
   public:
     bool isSimd128() const { return false; }
 
     typedef FloatRegistersMIPSShared::SetType SetType;
 
-#if defined(JS_CODEGEN_MIPS32)
     static uint32_t SetSize(SetType x) {
-        static_assert(sizeof(SetType) == 4, "SetType must be 32 bits");
+        static_assert(sizeof(SetType) == 8, "SetType must be 64 bits");
         return mozilla::CountPopulation32(x);
     }
     static uint32_t FirstBit(SetType x) {
-        static_assert(sizeof(SetType) == 4, "SetType must be 32 bits");
-        return mozilla::CountTrailingZeroes32(x);
-    }
-    static uint32_t LastBit(SetType x) {
-        static_assert(sizeof(SetType) == 4, "SetType must be 32 bits");
-        return 31 - mozilla::CountLeadingZeroes32(x);
-    }
-#elif defined(JS_CODEGEN_MIPS64)
-    static uint32_t SetSize(SetType x) {
-        static_assert(sizeof(SetType) == 8, "SetType must be 64 bits");
-        return mozilla::CountPopulation64(x);
-    }
-    static uint32_t FirstBit(SetType x) {
-        static_assert(sizeof(SetType) == 8, "SetType must be 64 bits");
         return mozilla::CountTrailingZeroes64(x);
     }
     static uint32_t LastBit(SetType x) {
-        static_assert(sizeof(SetType) == 8, "SetType must be 64 bits");
         return 63 - mozilla::CountLeadingZeroes64(x);
     }
-#endif
 };
 
 namespace mips_private {
     extern uint32_t Flags;
     extern bool hasFPU;
     extern bool isLoongson;
     extern bool hasR2;
 }
@@ -344,20 +323,20 @@ inline bool isLoongson() { return mips_p
 inline bool hasR2() { return mips_private::hasR2; }
 
 // MIPS doesn't have double registers that can NOT be treated as float32.
 inline bool
 hasUnaliasedDouble() {
     return false;
 }
 
-// MIPS64 doesn't support it and on MIPS32 we don't allocate odd single fp
-// registers thus not exposing multi aliasing to the jit.
-// See comments in Arhitecture-mips32.h.
+// On MIPS, fn-double aliases both fn-float32 and fn+1-float32, so if you need
+// to convert a float32 to a double as a temporary, you need a temporary
+// double register.
 inline bool
 hasMultiAlias() {
-    return false;
+    return true;
 }
 
 } // namespace jit
 } // namespace js
 
 #endif /* jit_mips_shared_Architecture_mips_shared_h */
--- a/js/src/jit/mips-shared/Assembler-mips-shared.cpp
+++ b/js/src/jit/mips-shared/Assembler-mips-shared.cpp
@@ -53,23 +53,16 @@ js::jit::RZ(Register r)
 
 uint32_t
 js::jit::SA(uint32_t value)
 {
     MOZ_ASSERT(value < 32);
     return value << SAShift;
 }
 
-uint32_t
-js::jit::FS(uint32_t value)
-{
-    MOZ_ASSERT(value < 32);
-    return value << FSShift;
-}
-
 Register
 js::jit::toRS(Instruction& i)
 {
     return Register::FromCode((i.encode() & RSMask ) >> RSShift);
 }
 
 Register
 js::jit::toRT(Instruction& i)
@@ -1343,25 +1336,25 @@ AssemblerMIPSShared::as_movd(FloatRegist
 {
     spew("mov.d  %3s,%3s", fd.name(), fs.name());
     return writeInst(InstReg(op_cop1, rs_d, zero, fs, fd, ff_mov_fmt).encode());
 }
 
 BufferOffset
 AssemblerMIPSShared::as_ctc1(Register rt, FPControl fc)
 {
-    spew("ctc1   %3s,%d", rt.name(), fc);
-    return writeInst(InstReg(op_cop1, rs_ctc1, rt, (uint32_t)fc).encode());
+    spew("ctc1   %3s,%3s", rt.name(), FloatRegister(fc).name());
+    return writeInst(InstReg(op_cop1, rs_ctc1, rt, FloatRegister(fc)).encode());
 }
 
 BufferOffset
 AssemblerMIPSShared::as_cfc1(Register rt, FPControl fc)
 {
-    spew("cfc1   %3s,%d", rt.name(), fc);
-    return writeInst(InstReg(op_cop1, rs_cfc1, rt, (uint32_t)fc).encode());
+    spew("cfc1   %3s,%3s", rt.name(), FloatRegister(fc).name());
+    return writeInst(InstReg(op_cop1, rs_cfc1, rt, FloatRegister(fc)).encode());
 }
 
 BufferOffset
 AssemblerMIPSShared::as_mtc1(Register rt, FloatRegister fs)
 {
     spew("mtc1   %3s,%3s", rt.name(), fs.name());
     return writeInst(InstReg(op_cop1, rs_mtc1, rt, fs).encode());
 }
--- a/js/src/jit/mips-shared/Assembler-mips-shared.h
+++ b/js/src/jit/mips-shared/Assembler-mips-shared.h
@@ -214,24 +214,25 @@ static const uint32_t MAX_BREAK_CODE = 1
 
 class Instruction;
 class InstReg;
 class InstImm;
 class InstJump;
 
 uint32_t RS(Register r);
 uint32_t RT(Register r);
+uint32_t RT(uint32_t regCode);
 uint32_t RT(FloatRegister r);
 uint32_t RD(Register r);
 uint32_t RD(FloatRegister r);
+uint32_t RD(uint32_t regCode);
 uint32_t RZ(Register r);
 uint32_t RZ(FloatRegister r);
 uint32_t SA(uint32_t value);
 uint32_t SA(FloatRegister r);
-uint32_t FS(uint32_t value);
 
 Register toRS (Instruction& i);
 Register toRT (Instruction& i);
 Register toRD (Instruction& i);
 Register toR (Instruction& i);
 
 // MIPS enums for instruction fields
 enum Opcode {
@@ -1416,19 +1417,16 @@ class InstReg : public Instruction
     { }
     InstReg(Opcode op, Register rs, uint32_t cc, Register rd, uint32_t sa, FunctionField ff)
       : Instruction(op | RS(rs) | cc | RD(rd) | SA(sa) | ff)
     { }
     InstReg(Opcode op, uint32_t code, FunctionField ff)
       : Instruction(op | code | ff)
     { }
     // for float point
-    InstReg(Opcode op, RSField rs, Register rt, uint32_t fs)
-      : Instruction(op | rs | RT(rt) | FS(fs))
-    { }
     InstReg(Opcode op, RSField rs, Register rt, FloatRegister rd)
       : Instruction(op | rs | RT(rt) | RD(rd))
     { }
     InstReg(Opcode op, RSField rs, Register rt, FloatRegister rd, uint32_t sa, FunctionField ff)
       : Instruction(op | rs | RT(rt) | RD(rd) | SA(sa) | ff)
     { }
     InstReg(Opcode op, RSField rs, Register rt, FloatRegister fs, FloatRegister fd, FunctionField ff)
       : Instruction(op | rs | RT(rt) | RD(fs) | SA(fd) | ff)
--- a/js/src/jit/mips32/Architecture-mips32.cpp
+++ b/js/src/jit/mips32/Architecture-mips32.cpp
@@ -23,74 +23,80 @@ const Registers::SetType Registers::ArgR
 const Registers::SetType Registers::JSCallMask =
     (1 << Registers::a2) |
     (1 << Registers::a3);
 
 const Registers::SetType Registers::CallMask =
     (1 << Registers::v0) |
     (1 << Registers::v1);  // used for double-size returns
 
-FloatRegisters::Encoding
+FloatRegisters::Code
 FloatRegisters::FromName(const char* name)
 {
-    for (size_t i = 0; i < RegisterIdLimit; i++) {
+    for (size_t i = 0; i < Total; i++) {
         if (strcmp(GetName(i), name) == 0)
-            return Encoding(i);
+            return Code(i);
     }
 
     return Invalid;
 }
 
 FloatRegister
-FloatRegister::doubleOverlay() const
+FloatRegister::doubleOverlay(unsigned int which) const
 {
-    MOZ_ASSERT(isNotOdd());
-    if (isSingle())
-        return FloatRegister(code_, Double);
+    MOZ_ASSERT(!isInvalid());
+    if (kind_ != Double)
+        return FloatRegister(code_ & ~1, Double);
     return *this;
 }
 
 FloatRegister
-FloatRegister::singleOverlay() const
+FloatRegister::singleOverlay(unsigned int which) const
 {
-    MOZ_ASSERT(isNotOdd());
-    if (isDouble())
-        return FloatRegister(code_, Single);
-    return *this;
+    MOZ_ASSERT(!isInvalid());
+    if (kind_ == Double) {
+        // Only even registers are double
+        MOZ_ASSERT(code_ % 2 == 0);
+        MOZ_ASSERT(which < 2);
+        return FloatRegister(code_ + which, Single);
+    }
+    MOZ_ASSERT(which == 0);
+    return FloatRegister(code_, Single);
 }
 
 FloatRegisterSet
 FloatRegister::ReduceSetForPush(const FloatRegisterSet& s)
 {
     LiveFloatRegisterSet mod;
     for (FloatRegisterIterator iter(s); iter.more(); ++iter) {
-        // Even for single size registers save complete double register.
-        mod.addUnchecked((*iter).doubleOverlay());
+        if ((*iter).isSingle()) {
+            // Even for single size registers save complete double register.
+            mod.addUnchecked((*iter).doubleOverlay());
+        } else {
+            mod.addUnchecked(*iter);
+        }
     }
     return mod.set();
 }
 
 uint32_t
 FloatRegister::GetPushSizeInBytes(const FloatRegisterSet& s)
 {
     FloatRegisterSet ss = s.reduceSetForPush();
     uint64_t bits = ss.bits();
     // We are only pushing double registers.
-    MOZ_ASSERT((bits & 0xFFFF) == 0);
-    uint32_t ret =  mozilla::CountPopulation32(bits) * sizeof(double);
-
-    // Additional space needed by MacroAssembler::PushRegsInMask to ensure
-    // correct alignment of double values.
-    if (ret)
-        ret += sizeof(double);
-
+    MOZ_ASSERT((bits & 0xffffffff) == 0);
+    uint32_t ret =  mozilla::CountPopulation32(bits >> 32) * sizeof(double);
     return ret;
 }
 uint32_t
 FloatRegister::getRegisterDumpOffsetInBytes()
 {
-    MOZ_ASSERT(isNotOdd());
-    return id() * sizeof(float);
+    if (isSingle())
+        return id() * sizeof(float);
+    if (isDouble())
+        return id() * sizeof(double);
+    MOZ_CRASH();
 }
 
 } // namespace ion
 } // namespace js
 
--- a/js/src/jit/mips32/Architecture-mips32.h
+++ b/js/src/jit/mips32/Architecture-mips32.h
@@ -14,88 +14,111 @@
 
 #include "jit/mips-shared/Architecture-mips-shared.h"
 
 #include "js/Utility.h"
 
 namespace js {
 namespace jit {
 
+// Shadow stack space is not required on MIPS.
 static const uint32_t ShadowStackSpace = 4 * sizeof(uintptr_t);
 
 // These offsets are specific to nunboxing, and capture offsets into the
 // components of a js::Value.
 // Size of MIPS32 general purpose registers is 32 bits.
 static const int32_t NUNBOX32_TYPE_OFFSET = 4;
 static const int32_t NUNBOX32_PAYLOAD_OFFSET = 0;
 
 // Size of each bailout table entry.
 // For MIPS this is 2 instructions relative call.
 static const uint32_t BAILOUT_TABLE_ENTRY_SIZE = 2 * sizeof(void*);
 
-// MIPS32 can have two types of floating-point coprocessors modes:
-// - FR=0 mode/ 32-bit FPRs - Historical default, there are 32 single
+// MIPS32 can have two types of floating-point coprocessors:
+// - 32 bit floating-point coprocessor - In this case, there are 32 single
 // precision registers and pairs of even and odd float registers are used as
 // double precision registers. Example: f0 (double) is composed of
-// f0 and f1 (single). Loongson3A FPU running in this mode doesn't allow
-// use of odd registers for single precision arithmetic.
-// - FR=1 mode/ 64-bit FPRs - In this case, there are 32 double precision register
-// which can also be used as single precision registers.
-// More info https://dmz-portal.imgtec.com/wiki/MIPS_O32_ABI_-_FR0_and_FR1_Interlinking
+// f0 and f1 (single).
+// - 64 bit floating-point coprocessor - In this case, there are 32 double
+// precision register which can also be used as single precision registers.
 
-// Currently we enable 16 even single precision registers which can be also can be used
-// as double precision registers. It enables jit code to run even on Loongson3A.
-// It does not support FR=1 mode because MacroAssembler threats odd single precision
-// registers as high parts of even double precision registers.
-#ifdef __mips_fpr
-static_assert(__mips_fpr == 32, "MIPS32 jit only supports FR=0 fpu mode.");
-#endif
-
+// When using O32 ABI, floating-point coprocessor is 32 bit.
+// When using N32 ABI, floating-point coprocessor is 64 bit.
 class FloatRegisters : public FloatRegistersMIPSShared
 {
   public:
     static const char* GetName(uint32_t i) {
-        MOZ_ASSERT(i < RegisterIdLimit);
-        return FloatRegistersMIPSShared::GetName(Encoding(i % 32));
+        MOZ_ASSERT(i < Total);
+        return FloatRegistersMIPSShared::GetName(Code(i % 32));
     }
 
-    static Encoding FromName(const char* name);
-
-    static const uint32_t Total = 32;
-    static const uint32_t TotalDouble = 16;
-    static const uint32_t TotalSingle = 16;
+    static Code FromName(const char* name);
 
+    static const uint32_t Total = 64;
+    static const uint32_t TotalDouble = 16;
+    static const uint32_t RegisterIdLimit = 32;
+    // Workarounds: On Loongson CPU-s the odd FP registers behave differently
+    // in fp-32 mode than standard MIPS.
+#if defined(_MIPS_ARCH_LOONGSON3A)
+    static const uint32_t TotalSingle = 16;
     static const uint32_t Allocatable = 28;
-    static const SetType AllSingleMask = (1ULL << TotalSingle) - 1;
-
-    static const SetType AllDoubleMask = ((1ULL << TotalDouble) - 1) << TotalSingle;
-    static const SetType AllMask = AllDoubleMask | AllSingleMask;
-
+    static const SetType AllSingleMask = 0x55555555ULL;
+#else
+    static const uint32_t TotalSingle = 32;
+    static const uint32_t Allocatable = 42;
+    static const SetType AllSingleMask = (1ULL << 32) - 1;
+#endif
     // When saving all registers we only need to do is save double registers.
     static const uint32_t TotalPhys = 16;
-    static const uint32_t RegisterIdLimit = 32;
 
     static_assert(sizeof(SetType) * 8 >= Total,
                   "SetType should be large enough to enumerate all registers.");
 
+    static const SetType AllDoubleMask = 0x55555555ULL << 32;
+    static const SetType AllMask = AllDoubleMask | AllSingleMask;
+
+    static const SetType NonVolatileDoubleMask =
+        ((1ULL << FloatRegisters::f20) |
+         (1ULL << FloatRegisters::f22) |
+         (1ULL << FloatRegisters::f24) |
+         (1ULL << FloatRegisters::f26) |
+         (1ULL << FloatRegisters::f28) |
+         (1ULL << FloatRegisters::f30)) << 32;
+
+    // f20-single and f21-single alias f20-double ...
     static const SetType NonVolatileMask =
-        ((SetType(1) << (FloatRegisters::f20 >> 1)) |
-         (SetType(1) << (FloatRegisters::f22 >> 1)) |
-         (SetType(1) << (FloatRegisters::f24 >> 1)) |
-         (SetType(1) << (FloatRegisters::f26 >> 1)) |
-         (SetType(1) << (FloatRegisters::f28 >> 1)) |
-         (SetType(1) << (FloatRegisters::f30 >> 1))) * ((1 << TotalSingle) + 1);
+        NonVolatileDoubleMask |
+        (1ULL << FloatRegisters::f20) |
+        (1ULL << FloatRegisters::f21) |
+        (1ULL << FloatRegisters::f22) |
+        (1ULL << FloatRegisters::f23) |
+        (1ULL << FloatRegisters::f24) |
+        (1ULL << FloatRegisters::f25) |
+        (1ULL << FloatRegisters::f26) |
+        (1ULL << FloatRegisters::f27) |
+        (1ULL << FloatRegisters::f28) |
+        (1ULL << FloatRegisters::f29) |
+        (1ULL << FloatRegisters::f30) |
+        (1ULL << FloatRegisters::f31);
 
     static const SetType VolatileMask = AllMask & ~NonVolatileMask;
+    static const SetType VolatileDoubleMask = AllDoubleMask & ~NonVolatileDoubleMask;
 
     static const SetType WrapperMask = VolatileMask;
 
+    static const SetType NonAllocatableDoubleMask =
+        ((1ULL << FloatRegisters::f16) |
+         (1ULL << FloatRegisters::f18)) << 32;
+    // f16-single and f17-single alias f16-double ...
     static const SetType NonAllocatableMask =
-        ((SetType(1) << (FloatRegisters::f16 >> 1)) |
-         (SetType(1) << (FloatRegisters::f18 >> 1))) * ((1 << TotalSingle) + 1);
+        NonAllocatableDoubleMask |
+        (1ULL << FloatRegisters::f16) |
+        (1ULL << FloatRegisters::f17) |
+        (1ULL << FloatRegisters::f18) |
+        (1ULL << FloatRegisters::f19);
 
     // Registers that can be allocated without being saved, generally.
     static const SetType TempMask = VolatileMask & ~NonAllocatableMask;
 
     static const SetType AllocatableMask = AllMask & ~NonAllocatableMask;
 };
 
 class FloatRegister : public FloatRegisterMIPSShared
@@ -105,127 +128,148 @@ class FloatRegister : public FloatRegist
         Single = 0x0,
         Double = 0x1,
     };
 
     typedef FloatRegisters Codes;
     typedef Codes::Code Code;
     typedef Codes::Encoding Encoding;
 
-    Encoding code_ : 6;
+    uint32_t code_ : 6;
   protected:
     RegType kind_ : 1;
 
   public:
     constexpr FloatRegister(uint32_t code, RegType kind = Double)
-      : code_ (Encoding(code)), kind_(kind)
+      : code_ (Code(code)), kind_(kind)
     { }
     constexpr FloatRegister()
-      : code_(FloatRegisters::invalid_freg), kind_(Double)
+      : code_(Code(FloatRegisters::invalid_freg)), kind_(Double)
     { }
 
     bool operator==(const FloatRegister& other) const {
         MOZ_ASSERT(!isInvalid());
         MOZ_ASSERT(!other.isInvalid());
         return kind_ == other.kind_ && code_ == other.code_;
     }
     bool equiv(const FloatRegister& other) const { return other.kind_ == kind_; }
     size_t size() const { return (kind_ == Double) ? 8 : 4; }
     bool isInvalid() const {
         return code_ == FloatRegisters::invalid_freg;
     }
 
-    bool isNotOdd() const { return !isInvalid() && ((code_ & 1) == 0); }
-
     bool isSingle() const { return kind_ == Single; }
     bool isDouble() const { return kind_ == Double; }
 
-    FloatRegister doubleOverlay() const;
-    FloatRegister singleOverlay() const;
+    FloatRegister doubleOverlay(unsigned int which = 0) const;
+    FloatRegister singleOverlay(unsigned int which = 0) const;
+    FloatRegister sintOverlay(unsigned int which = 0) const;
+    FloatRegister uintOverlay(unsigned int which = 0) const;
 
     FloatRegister asSingle() const { return singleOverlay(); }
     FloatRegister asDouble() const { return doubleOverlay(); }
     FloatRegister asSimd128() const { MOZ_CRASH("NYI"); }
 
     Code code() const {
-        MOZ_ASSERT(isNotOdd());
-        return Code((code_ >> 1)  | (kind_ << 4));
+        MOZ_ASSERT(!isInvalid());
+        return Code(code_  | (kind_ << 5));
     }
     Encoding encoding() const {
         MOZ_ASSERT(!isInvalid());
-        return code_;
+        return Encoding(code_);
     }
     uint32_t id() const {
-        MOZ_ASSERT(!isInvalid());
         return code_;
     }
     static FloatRegister FromCode(uint32_t i) {
-        uint32_t code = i & 15;
-        uint32_t kind = i >> 4;
-        return FloatRegister(Encoding(code << 1), RegType(kind));
+        uint32_t code = i & 31;
+        uint32_t kind = i >> 5;
+        return FloatRegister(code, RegType(kind));
     }
-
+    // This is similar to FromCode except for double registers on O32.
     static FloatRegister FromIndex(uint32_t index, RegType kind) {
-        MOZ_ASSERT(index < 16);
-        return FloatRegister(Encoding(index << 1), kind);
+#if defined(USES_O32_ABI)
+        // Only even FP registers are avaiable for Loongson on O32.
+# if defined(_MIPS_ARCH_LOONGSON3A)
+        return FloatRegister(index * 2, kind);
+# else
+        if (kind == Double)
+            return FloatRegister(index * 2, kind);
+# endif
+#endif
+        return FloatRegister(index, kind);
     }
 
     bool volatile_() const {
-        return !!((SetType(1) << code()) & FloatRegisters::VolatileMask);
+        if (isDouble())
+            return !!((1ULL << code_) & FloatRegisters::VolatileMask);
+        return !!((1ULL << (code_ & ~1)) & FloatRegisters::VolatileMask);
     }
     const char* name() const {
         return FloatRegisters::GetName(code_);
     }
     bool operator != (const FloatRegister& other) const {
         return other.kind_ != kind_ || code_ != other.code_;
     }
     bool aliases(const FloatRegister& other) {
-        MOZ_ASSERT(isNotOdd());
-        return code_ == other.code_;
+        if (kind_ == other.kind_)
+            return code_ == other.code_;
+        return doubleOverlay() == other.doubleOverlay();
     }
     uint32_t numAliased() const {
-        MOZ_ASSERT(isNotOdd());
+        if (isDouble()) {
+            MOZ_ASSERT((code_ & 1) == 0);
+            return 3;
+        }
         return 2;
     }
     void aliased(uint32_t aliasIdx, FloatRegister* ret) {
-        MOZ_ASSERT(isNotOdd());
-
+        if (aliasIdx == 0) {
+            *ret = *this;
+            return;
+        }
+        if (isDouble()) {
+            MOZ_ASSERT((code_ & 1) == 0);
+            MOZ_ASSERT(aliasIdx <= 2);
+            *ret = singleOverlay(aliasIdx - 1);
+            return;
+        }
+        MOZ_ASSERT(aliasIdx == 1);
+        *ret = doubleOverlay(aliasIdx - 1);
+    }
+    uint32_t numAlignedAliased() const {
+        if (isDouble()) {
+            MOZ_ASSERT((code_ & 1) == 0);
+            return 2;
+        }
+        // f1-float32 has 0 other aligned aliases, 1 total.
+        // f0-float32 has 1 other aligned alias, 2 total.
+        return 2 - (code_ & 1);
+    }
+    // |        f0-double        |
+    // | f0-float32 | f1-float32 |
+    // We only push double registers on MIPS. So, if we've stored f0-double
+    // we also want to f0-float32 is stored there.
+    void alignedAliased(uint32_t aliasIdx, FloatRegister* ret) {
+        MOZ_ASSERT(isDouble());
+        MOZ_ASSERT((code_ & 1) == 0);
         if (aliasIdx == 0) {
             *ret = *this;
             return;
         }
         MOZ_ASSERT(aliasIdx == 1);
-        if (isDouble()) {
-            *ret = singleOverlay();
-        } else {
-            *ret = doubleOverlay();
-        }
-    }
-    uint32_t numAlignedAliased() const {
-        MOZ_ASSERT(isNotOdd());
-        return 2;
-    }
-    void alignedAliased(uint32_t aliasIdx, FloatRegister* ret) {
-        MOZ_ASSERT(isNotOdd());
-
-        if (aliasIdx == 0) {
-            *ret = *this;
-            return;
-        }
-        MOZ_ASSERT(aliasIdx == 1);
-        if (isDouble()) {
-            *ret = singleOverlay();
-        } else {
-            *ret = doubleOverlay();
-        }
+        *ret = singleOverlay(aliasIdx - 1);
     }
 
     SetType alignedOrDominatedAliasedSet() const {
-        MOZ_ASSERT(isNotOdd());
-        return (SetType(1) << (code_ >> 1)) * ((1 << FloatRegisters::TotalSingle) + 1);
+        if (isSingle())
+            return SetType(1) << code_;
+
+        MOZ_ASSERT(isDouble());
+        return SetType(0b11) << code_;
     }
 
     static constexpr RegTypeName DefaultType = RegTypeName::Float64;
 
     template <RegTypeName = DefaultType>
     static SetType LiveAsIndexableSet(SetType s) {
         return SetType(0);
     }
@@ -257,31 +301,16 @@ FloatRegister::LiveAsIndexableSet<RegTyp
 }
 
 template <> inline FloatRegister::SetType
 FloatRegister::LiveAsIndexableSet<RegTypeName::Any>(SetType set)
 {
     return set;
 }
 
-template <> inline FloatRegister::SetType
-FloatRegister::AllocatableAsIndexableSet<RegTypeName::Float32>(SetType set)
-{
-    // Single registers are not dominating any smaller registers, thus masking
-    // is enough to convert an allocatable set into a set of register list all
-    // single register available.
-    return set & FloatRegisters::AllSingleMask;
-}
-
-template <> inline FloatRegister::SetType
-FloatRegister::AllocatableAsIndexableSet<RegTypeName::Float64>(SetType set)
-{
-    return set & FloatRegisters::AllDoubleMask;
-}
-
 // In order to handle functions such as int(*)(int, double) where the first
 // argument is a general purpose register, and the second argument is a floating
 // point register, we have to store the double content into 2 general purpose
 // registers, namely a2 and a3.
 #define JS_CODEGEN_REGISTER_PAIR 1
 
 } // namespace jit
 } // namespace js
--- a/js/src/jit/mips32/Assembler-mips32.h
+++ b/js/src/jit/mips32/Assembler-mips32.h
@@ -152,19 +152,17 @@ class Assembler : public AssemblerMIPSSh
 
     static uintptr_t GetPointer(uint8_t*);
 
   protected:
     // This is used to access the odd register form the pair of single
     // precision registers that make one double register.
     FloatRegister getOddPair(FloatRegister reg) {
         MOZ_ASSERT(reg.isDouble());
-        MOZ_ASSERT(reg.id() % 2 == 0);
-        FloatRegister odd(reg.id() | 1, FloatRegister::Single);
-        return odd;
+        return reg.singleOverlay(1);
     }
 
   public:
     using AssemblerMIPSShared::bind;
 
     void bind(RepatchLabel* label);
     static void Bind(uint8_t* rawCode, CodeOffset label, CodeOffset target);
 
--- a/js/src/jit/mips32/CodeGenerator-mips32.cpp
+++ b/js/src/jit/mips32/CodeGenerator-mips32.cpp
@@ -821,10 +821,11 @@ CodeGeneratorMIPS::visitTestI64AndBranch
     emitBranch(input.low, Imm32(0), Assembler::NonZero, lir->ifTrue(), lir->ifFalse());
 }
 
 void
 CodeGeneratorMIPS::setReturnDoubleRegs(LiveRegisterSet* regs)
 {
     MOZ_ASSERT(ReturnFloat32Reg.code_ == ReturnDoubleReg.code_);
     regs->add(ReturnFloat32Reg);
+    regs->add(ReturnDoubleReg.singleOverlay(1));
     regs->add(ReturnDoubleReg);
 }
\ No newline at end of file
--- a/js/src/jit/mips32/MacroAssembler-mips32.cpp
+++ b/js/src/jit/mips32/MacroAssembler-mips32.cpp
@@ -746,25 +746,25 @@ MacroAssemblerMIPS::ma_ss(FloatRegister 
             as_ss(ft, ScratchRegister, 0);
         }
     }
 }
 
 void
 MacroAssemblerMIPS::ma_pop(FloatRegister fs)
 {
-    ma_ld(fs.doubleOverlay(), Address(StackPointer, 0));
+    ma_ld(fs.doubleOverlay(0), Address(StackPointer, 0));
     as_addiu(StackPointer, StackPointer, sizeof(double));
 }
 
 void
 MacroAssemblerMIPS::ma_push(FloatRegister fs)
 {
     as_addiu(StackPointer, StackPointer, -sizeof(double));
-    ma_sd(fs.doubleOverlay(), Address(StackPointer, 0));
+    ma_sd(fs.doubleOverlay(0), Address(StackPointer, 0));
 }
 
 bool
 MacroAssemblerMIPSCompat::buildOOLFakeExitFrame(void* fakeReturnAddr)
 {
     uint32_t descriptor = MakeFrameDescriptor(asMasm().framePushed(), JitFrame_IonJS,
                                               ExitFrameLayout::Size());
 
@@ -2105,97 +2105,92 @@ MacroAssembler::PushRegsInMask(LiveRegis
 
     reserveStack(diffG);
     for (GeneralRegisterBackwardIterator iter(set.gprs()); iter.more(); ++iter) {
         diffG -= sizeof(intptr_t);
         storePtr(*iter, Address(StackPointer, diffG));
     }
     MOZ_ASSERT(diffG == 0);
 
-    if (diffF > 0) {
-        // Double values have to be aligned. We reserve extra space so that we can
-        // start writing from the first aligned location.
-        // We reserve a whole extra double so that the buffer has even size.
-        ma_and(SecondScratchReg, sp, Imm32(~(ABIStackAlignment - 1)));
-        reserveStack(diffF);
+    // Double values have to be aligned. We reserve extra space so that we can
+    // start writing from the first aligned location.
+    // We reserve a whole extra double so that the buffer has even size.
+    ma_and(SecondScratchReg, sp, Imm32(~(ABIStackAlignment - 1)));
+    reserveStack(diffF + sizeof(double));
 
+    for (FloatRegisterForwardIterator iter(set.fpus().reduceSetForPush()); iter.more(); ++iter) {
+        if ((*iter).code() % 2 == 0)
+            as_sd(*iter, SecondScratchReg, -diffF);
         diffF -= sizeof(double);
-
-        for (FloatRegisterForwardIterator iter(set.fpus().reduceSetForPush()); iter.more(); ++iter) {
-            as_sd(*iter, SecondScratchReg, -diffF);
-            diffF -= sizeof(double);
-        }
-
-        MOZ_ASSERT(diffF == 0);
     }
+    MOZ_ASSERT(diffF == 0);
 }
 
 void
 MacroAssembler::PopRegsInMaskIgnore(LiveRegisterSet set, LiveRegisterSet ignore)
 {
     int32_t diffG = set.gprs().size() * sizeof(intptr_t);
     int32_t diffF = set.fpus().getPushSizeInBytes();
     const int32_t reservedG = diffG;
     const int32_t reservedF = diffF;
 
-    if (reservedF > 0) {
-        // Read the buffer form the first aligned location.
-        ma_addu(SecondScratchReg, sp, Imm32(reservedF));
-        ma_and(SecondScratchReg, SecondScratchReg, Imm32(~(ABIStackAlignment - 1)));
-
-        diffF -= sizeof(double);
+    // Read the buffer form the first aligned location.
+    ma_addu(SecondScratchReg, sp, Imm32(reservedF + sizeof(double)));
+    ma_and(SecondScratchReg, SecondScratchReg, Imm32(~(ABIStackAlignment - 1)));
 
-        LiveFloatRegisterSet fpignore(ignore.fpus().reduceSetForPush());
-        for (FloatRegisterForwardIterator iter(set.fpus().reduceSetForPush()); iter.more(); ++iter) {
-            if (!ignore.has(*iter))
-                as_ld(*iter, SecondScratchReg, -diffF);
-            diffF -= sizeof(double);
-        }
-        freeStack(reservedF);
-        MOZ_ASSERT(diffF == 0);
+    for (FloatRegisterForwardIterator iter(set.fpus().reduceSetForPush()); iter.more(); ++iter) {
+        if (!ignore.has(*iter) && ((*iter).code() % 2 == 0))
+            // Use assembly l.d because we have alligned the stack.
+            as_ld(*iter, SecondScratchReg, -diffF);
+        diffF -= sizeof(double);
     }
+    freeStack(reservedF + sizeof(double));
+    MOZ_ASSERT(diffF == 0);
 
     for (GeneralRegisterBackwardIterator iter(set.gprs()); iter.more(); ++iter) {
         diffG -= sizeof(intptr_t);
         if (!ignore.has(*iter))
             loadPtr(Address(StackPointer, diffG), *iter);
     }
     freeStack(reservedG);
     MOZ_ASSERT(diffG == 0);
 }
 
 void
-MacroAssembler::storeRegsInMask(LiveRegisterSet set, Address dest, Register scratch)
+MacroAssembler::storeRegsInMask(LiveRegisterSet set, Address dest, Register)
 {
-    int32_t diffF = set.fpus().getPushSizeInBytes();
+    FloatRegisterSet fpuSet(set.fpus().reduceSetForPush());
+    unsigned numFpu = fpuSet.size();
+    int32_t diffF = fpuSet.getPushSizeInBytes();
     int32_t diffG = set.gprs().size() * sizeof(intptr_t);
 
     MOZ_ASSERT(dest.offset >= diffG + diffF);
-    MOZ_ASSERT(dest.base == StackPointer);
 
     for (GeneralRegisterBackwardIterator iter(set.gprs()); iter.more(); ++iter) {
         diffG -= sizeof(intptr_t);
         dest.offset -= sizeof(intptr_t);
         storePtr(*iter, dest);
     }
     MOZ_ASSERT(diffG == 0);
 
-    if (diffF > 0) {
-
-        computeEffectiveAddress(dest, scratch);
-        ma_and(scratch, scratch, Imm32(~(ABIStackAlignment - 1)));
-
-        diffF -= sizeof(double);
-
-        for (FloatRegisterForwardIterator iter(set.fpus().reduceSetForPush()); iter.more(); ++iter) {
-            as_sd(*iter, scratch, -diffF);
-            diffF -= sizeof(double);
-        }
-        MOZ_ASSERT(diffF == 0);
+    for (FloatRegisterBackwardIterator iter(fpuSet); iter.more(); ++iter) {
+        FloatRegister reg = *iter;
+        diffF -= reg.size();
+        numFpu -= 1;
+        dest.offset -= reg.size();
+        if (reg.isDouble())
+            storeDouble(reg, dest);
+        else if (reg.isSingle())
+            storeFloat32(reg, dest);
+        else
+            MOZ_CRASH("Unknown register type.");
     }
+    MOZ_ASSERT(numFpu == 0);
+    diffF -= diffF % sizeof(uintptr_t);
+    MOZ_ASSERT(diffF == 0);
 }
 // ===============================================================
 // ABI function calls.
 
 void
 MacroAssembler::setupUnalignedABICall(Register scratch)
 {
     MOZ_ASSERT(!IsCompilingWasm(), "wasm should only use aligned ABI calls");
--- a/js/src/wasm/WasmStubs.cpp
+++ b/js/src/wasm/WasmStubs.cpp
@@ -234,17 +234,21 @@ static const LiveRegisterSet NonVolatile
                                      | (1ULL << FloatRegisters::d15)
                                      | (1ULL << FloatRegisters::s31)));
 #else
 static const LiveRegisterSet NonVolatileRegs =
     LiveRegisterSet(GeneralRegisterSet(Registers::NonVolatileMask),
                     FloatRegisterSet(FloatRegisters::NonVolatileMask));
 #endif
 
-#if defined(JS_CODEGEN_NONE)
+#if defined(JS_CODEGEN_MIPS32)
+static const unsigned NonVolatileRegsPushSize = NonVolatileRegs.gprs().size() * sizeof(intptr_t) +
+                                                NonVolatileRegs.fpus().getPushSizeInBytes() +
+                                                sizeof(double);
+#elif defined(JS_CODEGEN_NONE)
 static const unsigned NonVolatileRegsPushSize = 0;
 #else
 static const unsigned NonVolatileRegsPushSize = NonVolatileRegs.gprs().size() * sizeof(intptr_t) +
                                                 NonVolatileRegs.fpus().getPushSizeInBytes();
 #endif
 static const unsigned FramePushedBeforeAlign = NonVolatileRegsPushSize + sizeof(void*);
 
 // Generate a stub that enters wasm from a C++ caller via the native ABI. The