Bug 1517594 - Don't use mrs instruction in aarch64-windows r=nbp
authorDavid Major <dmajor@mozilla.com>
Fri, 04 Jan 2019 15:29:07 +0000
changeset 510028 bda1e52239227bb7b84a73cf0f3b2e6f2a31794c
parent 510027 9d3a199acc6e073a11ddecf4a6947586cfe46e9a
child 510029 e0a5cb126f2f084e5f7f3d5f0be0222a7fd67479
push id10547
push userffxbld-merge
push dateMon, 21 Jan 2019 13:03:58 +0000
treeherdermozilla-beta@24ec1916bffe [default view] [failures only]
perfherder[talos] [build metrics] [platform microbench] (compared to previous push)
reviewersnbp
bugs1517594
milestone66.0a1
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Bug 1517594 - Don't use mrs instruction in aarch64-windows r=nbp Differential Revision: https://phabricator.services.mozilla.com/D15680
js/src/jit/arm64/vixl/Cpu-vixl.cpp
js/src/jit/arm64/vixl/MozCpu-vixl.cpp
--- a/js/src/jit/arm64/vixl/Cpu-vixl.cpp
+++ b/js/src/jit/arm64/vixl/Cpu-vixl.cpp
@@ -51,26 +51,9 @@ void CPU::SetUp() {
       (cache_type_register & kDCacheLineSizeMask) >> kDCacheLineSizeShift;
   uint32_t icache_line_size_power_of_two =
       (cache_type_register & kICacheLineSizeMask) >> kICacheLineSizeShift;
 
   dcache_line_size_ = 4 << dcache_line_size_power_of_two;
   icache_line_size_ = 4 << icache_line_size_power_of_two;
 }
 
-
-uint32_t CPU::GetCacheType() {
-#ifdef __aarch64__
-  uint64_t cache_type_register;
-  // Copy the content of the cache type register to a core register.
-  __asm__ __volatile__ ("mrs %[ctr], ctr_el0"  // NOLINT
-                        : [ctr] "=r" (cache_type_register));
-  VIXL_ASSERT(is_uint32(cache_type_register));
-  return cache_type_register;
-#else
-  // This will lead to a cache with 1 byte long lines, which is fine since
-  // neither EnsureIAndDCacheCoherency nor the simulator will need this
-  // information.
-  return 0;
-#endif
-}
-
 }  // namespace vixl
--- a/js/src/jit/arm64/vixl/MozCpu-vixl.cpp
+++ b/js/src/jit/arm64/vixl/MozCpu-vixl.cpp
@@ -25,16 +25,33 @@
 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
 #include "jit/arm64/vixl/Cpu-vixl.h"
 #include "jit/arm64/vixl/Utils-vixl.h"
 #include "util/Windows.h"
 
 namespace vixl {
 
+uint32_t CPU::GetCacheType() {
+#if defined(__aarch64__) && !defined(_MSC_VER)
+  uint64_t cache_type_register;
+  // Copy the content of the cache type register to a core register.
+  __asm__ __volatile__ ("mrs %[ctr], ctr_el0"  // NOLINT
+                        : [ctr] "=r" (cache_type_register));
+  VIXL_ASSERT(is_uint32(cache_type_register));
+  return cache_type_register;
+#else
+  // This will lead to a cache with 1 byte long lines, which is fine since
+  // neither EnsureIAndDCacheCoherency nor the simulator will need this
+  // information.
+  return 0;
+#endif
+}
+
+
 void CPU::EnsureIAndDCacheCoherency(void *address, size_t length) {
 #if defined(_MSC_VER) && defined(_M_ARM64)
   FlushInstructionCache(GetCurrentProcess(), address, length);
 #elif defined(__aarch64__)
   // Implement the cache synchronisation for all targets where AArch64 is the
   // host, even if we're building the simulator for an AAarch64 host. This
   // allows for cases where the user wants to simulate code as well as run it
   // natively.