Bug 1010775 part 1 - Pass Register by value instead of const-ref. r=sunfish
authorJan de Mooij <jdemooij@mozilla.com>
Thu, 15 May 2014 17:42:30 +0200
changeset 202590 88201d0deed86502af6bd07f0e72f75cf76dfa2a
parent 202589 9ea8d902533f8dd5831cb0aabc6be796afaf7a62
child 202591 516dd2e509ac8b1fc56153c4cd9c43d522f93043
push id3741
push userasasaki@mozilla.com
push dateMon, 21 Jul 2014 20:25:18 +0000
treeherdermozilla-beta@4d6f46f5af68 [default view] [failures only]
perfherder[talos] [build metrics] [platform microbench] (compared to previous push)
reviewerssunfish
bugs1010775
milestone32.0a1
first release with
nightly linux32
nightly linux64
nightly mac
nightly win32
nightly win64
last release without
nightly linux32
nightly linux64
nightly mac
nightly win32
nightly win64
Bug 1010775 part 1 - Pass Register by value instead of const-ref. r=sunfish
js/src/jit/MoveResolver.h
js/src/jit/Registers.h
js/src/jit/Snapshots.h
js/src/jit/arm/Assembler-arm.cpp
js/src/jit/arm/CodeGenerator-arm.cpp
js/src/jit/arm/CodeGenerator-arm.h
js/src/jit/arm/MacroAssembler-arm.cpp
js/src/jit/arm/MacroAssembler-arm.h
js/src/jit/mips/CodeGenerator-mips.cpp
js/src/jit/mips/CodeGenerator-mips.h
js/src/jit/mips/MacroAssembler-mips.cpp
js/src/jit/mips/MacroAssembler-mips.h
js/src/jit/shared/Assembler-x86-shared.h
js/src/jit/shared/CodeGenerator-shared-inl.h
js/src/jit/shared/CodeGenerator-shared.cpp
js/src/jit/shared/CodeGenerator-shared.h
js/src/jit/shared/CodeGenerator-x86-shared.cpp
js/src/jit/shared/CodeGenerator-x86-shared.h
js/src/jit/shared/MacroAssembler-x86-shared.cpp
js/src/jit/shared/MacroAssembler-x86-shared.h
js/src/jit/x64/Assembler-x64.h
js/src/jit/x64/CodeGenerator-x64.cpp
js/src/jit/x64/CodeGenerator-x64.h
js/src/jit/x64/MacroAssembler-x64.cpp
js/src/jit/x64/MacroAssembler-x64.h
js/src/jit/x86/Assembler-x86.h
js/src/jit/x86/CodeGenerator-x86.cpp
js/src/jit/x86/CodeGenerator-x86.h
js/src/jit/x86/MacroAssembler-x86.cpp
js/src/jit/x86/MacroAssembler-x86.h
--- a/js/src/jit/MoveResolver.h
+++ b/js/src/jit/MoveResolver.h
@@ -33,21 +33,21 @@ class MoveOperand
   private:
     Kind kind_;
     uint32_t code_;
     int32_t disp_;
 
   public:
     MoveOperand()
     { }
-    explicit MoveOperand(const Register &reg) : kind_(REG), code_(reg.code())
+    explicit MoveOperand(Register reg) : kind_(REG), code_(reg.code())
     { }
     explicit MoveOperand(const FloatRegister &reg) : kind_(FLOAT_REG), code_(reg.code())
     { }
-    MoveOperand(const Register &reg, int32_t disp, Kind kind = MEMORY)
+    MoveOperand(Register reg, int32_t disp, Kind kind = MEMORY)
         : kind_(kind),
         code_(reg.code()),
         disp_(disp)
     {
         JS_ASSERT(isMemoryOrEffectiveAddress());
 
         // With a zero offset, this is a plain reg-to-reg move.
         if (disp == 0 && kind_ == EFFECTIVE_ADDRESS)
--- a/js/src/jit/Registers.h
+++ b/js/src/jit/Registers.h
@@ -42,20 +42,20 @@ struct Register {
     }
     Code code() const {
         JS_ASSERT((uint32_t)code_ < Registers::Total);
         return code_;
     }
     const char *name() const {
         return Registers::GetName(code());
     }
-    bool operator ==(const Register &other) const {
+    bool operator ==(Register other) const {
         return code_ == other.code_;
     }
-    bool operator !=(const Register &other) const {
+    bool operator !=(Register other) const {
         return code_ != other.code_;
     }
     bool volatile_() const {
         return !!((1 << code()) & Registers::VolatileMask);
     }
 };
 
 struct FloatRegister {
--- a/js/src/jit/Snapshots.h
+++ b/js/src/jit/Snapshots.h
@@ -168,17 +168,17 @@ class RValueAllocation
     static RValueAllocation Float32(const FloatRegister &reg) {
         return RValueAllocation(FLOAT32_REG, payloadOfFloatRegister(reg));
     }
     static RValueAllocation Float32(int32_t offset) {
         return RValueAllocation(FLOAT32_STACK, payloadOfStackOffset(offset));
     }
 
     // TYPED_REG or TYPED_STACK
-    static RValueAllocation Typed(JSValueType type, const Register &reg) {
+    static RValueAllocation Typed(JSValueType type, Register reg) {
         JS_ASSERT(type != JSVAL_TYPE_DOUBLE &&
                   type != JSVAL_TYPE_MAGIC &&
                   type != JSVAL_TYPE_NULL &&
                   type != JSVAL_TYPE_UNDEFINED);
         return RValueAllocation(TYPED_REG, payloadOfValueType(type),
                                 payloadOfRegister(reg));
     }
     static RValueAllocation Typed(JSValueType type, int32_t offset) {
@@ -186,42 +186,42 @@ class RValueAllocation
                   type != JSVAL_TYPE_NULL &&
                   type != JSVAL_TYPE_UNDEFINED);
         return RValueAllocation(TYPED_STACK, payloadOfValueType(type),
                                 payloadOfStackOffset(offset));
     }
 
     // UNTYPED
 #if defined(JS_NUNBOX32)
-    static RValueAllocation Untyped(const Register &type, const Register &payload) {
+    static RValueAllocation Untyped(Register type, Register payload) {
         return RValueAllocation(UNTYPED_REG_REG,
                                 payloadOfRegister(type),
                                 payloadOfRegister(payload));
     }
 
-    static RValueAllocation Untyped(const Register &type, int32_t payloadStackOffset) {
+    static RValueAllocation Untyped(Register type, int32_t payloadStackOffset) {
         return RValueAllocation(UNTYPED_REG_STACK,
                                 payloadOfRegister(type),
                                 payloadOfStackOffset(payloadStackOffset));
     }
 
-    static RValueAllocation Untyped(int32_t typeStackOffset, const Register &payload) {
+    static RValueAllocation Untyped(int32_t typeStackOffset, Register payload) {
         return RValueAllocation(UNTYPED_STACK_REG,
                                 payloadOfStackOffset(typeStackOffset),
                                 payloadOfRegister(payload));
     }
 
     static RValueAllocation Untyped(int32_t typeStackOffset, int32_t payloadStackOffset) {
         return RValueAllocation(UNTYPED_STACK_STACK,
                                 payloadOfStackOffset(typeStackOffset),
                                 payloadOfStackOffset(payloadStackOffset));
     }
 
 #elif defined(JS_PUNBOX64)
-    static RValueAllocation Untyped(const Register &reg) {
+    static RValueAllocation Untyped(Register reg) {
         return RValueAllocation(UNTYPED_REG, payloadOfRegister(reg));
     }
 
     static RValueAllocation Untyped(int32_t stackOffset) {
         return RValueAllocation(UNTYPED_STACK, payloadOfStackOffset(stackOffset));
     }
 #endif
 
--- a/js/src/jit/arm/Assembler-arm.cpp
+++ b/js/src/jit/arm/Assembler-arm.cpp
@@ -1562,17 +1562,17 @@ class PoolHintData {
     LoadType   loadType : 2;
     uint32_t   destReg  : 5;
     uint32_t   destType : 1;
     uint32_t   ONES     : 4;
 
     static const uint32_t expectedOnes = 0xfu;
 
   public:
-    void init(uint32_t index_, Assembler::Condition cond_, LoadType lt, const Register &destReg_) {
+    void init(uint32_t index_, Assembler::Condition cond_, LoadType lt, Register destReg_) {
         index = index_;
         JS_ASSERT(index == index_);
         cond = cond_ >> 28;
         JS_ASSERT(cond == cond_ >> 28);
         loadType = lt;
         ONES = expectedOnes;
         destReg = destReg_.code();
         destType = 0;
--- a/js/src/jit/arm/CodeGenerator-arm.cpp
+++ b/js/src/jit/arm/CodeGenerator-arm.cpp
@@ -1103,18 +1103,17 @@ CodeGeneratorARM::visitOutOfLineTableSwi
         if (!masm.addCodeLabel(cl))
             return false;
     }
 
     return true;
 }
 
 bool
-CodeGeneratorARM::emitTableSwitchDispatch(MTableSwitch *mir, const Register &index,
-                                          const Register &base)
+CodeGeneratorARM::emitTableSwitchDispatch(MTableSwitch *mir, Register index, Register base)
 {
     // the code generated by this is utter hax.
     // the end result looks something like:
     // SUBS index, input, #base
     // RSBSPL index, index, #max
     // LDRPL pc, pc, index lsl 2
     // B default
 
@@ -1265,17 +1264,17 @@ CodeGeneratorARM::visitRoundF(LRoundF *l
     // case.a
     masm.roundf(input, output, &bail, tmp);
     if (!bailoutFrom(&bail, lir->snapshot()))
         return false;
     return true;
 }
 
 void
-CodeGeneratorARM::emitRoundDouble(const FloatRegister &src, const Register &dest, Label *fail)
+CodeGeneratorARM::emitRoundDouble(const FloatRegister &src, Register dest, Label *fail)
 {
     masm.ma_vcvt_F64_I32(src, ScratchFloatReg);
     masm.ma_vxfer(ScratchFloatReg, dest);
     masm.ma_cmp(dest, Imm32(0x7fffffff));
     masm.ma_cmp(dest, Imm32(0x80000000), Assembler::NotEqual);
     masm.ma_b(fail, Assembler::Equal);
 }
 
@@ -1788,17 +1787,17 @@ CodeGeneratorARM::visitLoadElementT(LLoa
         }
     }
     JS_ASSERT(!load->mir()->needsHoleCheck());
     return true;
 }
 
 void
 CodeGeneratorARM::storeElementTyped(const LAllocation *value, MIRType valueType, MIRType elementType,
-                                    const Register &elements, const LAllocation *index)
+                                    Register elements, const LAllocation *index)
 {
     if (index->isConstant()) {
         Address dest = Address(elements, ToInt32(index) * sizeof(Value));
         if (valueType == MIRType_Double) {
             masm.ma_vstr(ToFloatRegister(value), Operand(dest));
             return;
         }
 
--- a/js/src/jit/arm/CodeGenerator-arm.h
+++ b/js/src/jit/arm/CodeGenerator-arm.h
@@ -70,17 +70,17 @@ class CodeGeneratorARM : public CodeGene
     }
 
   protected:
     bool generatePrologue();
     bool generateAsmJSPrologue(Label *stackOverflowLabel);
     bool generateEpilogue();
     bool generateOutOfLineCode();
 
-    void emitRoundDouble(const FloatRegister &src, const Register &dest, Label *fail);
+    void emitRoundDouble(const FloatRegister &src, Register dest, Label *fail);
 
     // Emits a branch that directs control flow to the true block if |cond| is
     // true, and the false block if |cond| is false.
     void emitBranch(Assembler::Condition cond, MBasicBlock *ifTrue, MBasicBlock *ifFalse);
 
     void testNullEmitBranch(Assembler::Condition cond, const ValueOperand &value,
                             MBasicBlock *ifTrue, MBasicBlock *ifFalse)
     {
@@ -89,17 +89,17 @@ class CodeGeneratorARM : public CodeGene
     }
     void testUndefinedEmitBranch(Assembler::Condition cond, const ValueOperand &value,
                                  MBasicBlock *ifTrue, MBasicBlock *ifFalse)
     {
         cond = masm.testUndefined(cond, value);
         emitBranch(cond, ifTrue, ifFalse);
     }
 
-    bool emitTableSwitchDispatch(MTableSwitch *mir, const Register &index, const Register &base);
+    bool emitTableSwitchDispatch(MTableSwitch *mir, Register index, Register base);
 
   public:
     // Instruction visitors.
     virtual bool visitMinMaxD(LMinMaxD *ins);
     virtual bool visitAbsD(LAbsD *ins);
     virtual bool visitAbsF(LAbsF *ins);
     virtual bool visitSqrtD(LSqrtD *ins);
     virtual bool visitSqrtF(LSqrtF *ins);
@@ -158,17 +158,17 @@ class CodeGeneratorARM : public CodeGene
     ValueOperand ToValue(LInstruction *ins, size_t pos);
     ValueOperand ToOutValue(LInstruction *ins);
     ValueOperand ToTempValue(LInstruction *ins, size_t pos);
 
     // Functions for LTestVAndBranch.
     Register splitTagForTest(const ValueOperand &value);
 
     void storeElementTyped(const LAllocation *value, MIRType valueType, MIRType elementType,
-                           const Register &elements, const LAllocation *index);
+                           Register elements, const LAllocation *index);
 
     bool divICommon(MDiv *mir, Register lhs, Register rhs, Register output, LSnapshot *snapshot,
                     Label &done);
     bool modICommon(MMod *mir, Register lhs, Register rhs, Register output, LSnapshot *snapshot,
                     Label &done);
 
   public:
     CodeGeneratorARM(MIRGenerator *gen, LIRGraph *graph, MacroAssembler *masm);
--- a/js/src/jit/arm/MacroAssembler-arm.cpp
+++ b/js/src/jit/arm/MacroAssembler-arm.cpp
@@ -39,43 +39,43 @@ void
 MacroAssemblerARM::convertBoolToInt32(Register source, Register dest)
 {
     // Note that C++ bool is only 1 byte, so zero extend it to clear the
     // higher-order bits.
     ma_and(Imm32(0xff), source, dest);
 }
 
 void
-MacroAssemblerARM::convertInt32ToDouble(const Register &src, const FloatRegister &dest_)
+MacroAssemblerARM::convertInt32ToDouble(Register src, const FloatRegister &dest_)
 {
     // direct conversions aren't possible.
     VFPRegister dest = VFPRegister(dest_);
     as_vxfer(src, InvalidReg, dest.sintOverlay(),
              CoreToFloat);
     as_vcvt(dest, dest.sintOverlay());
 }
 
 void
 MacroAssemblerARM::convertInt32ToDouble(const Address &src, FloatRegister dest)
 {
     ma_vldr(Operand(src), ScratchFloatReg);
     as_vcvt(dest, VFPRegister(ScratchFloatReg).sintOverlay());
 }
 
 void
-MacroAssemblerARM::convertUInt32ToDouble(const Register &src, const FloatRegister &dest_)
+MacroAssemblerARM::convertUInt32ToDouble(Register src, const FloatRegister &dest_)
 {
     // direct conversions aren't possible.
     VFPRegister dest = VFPRegister(dest_);
     as_vxfer(src, InvalidReg, dest.uintOverlay(), CoreToFloat);
     as_vcvt(dest, dest.uintOverlay());
 }
 
 void
-MacroAssemblerARM::convertUInt32ToFloat32(const Register &src, const FloatRegister &dest_)
+MacroAssemblerARM::convertUInt32ToFloat32(Register src, const FloatRegister &dest_)
 {
     // direct conversions aren't possible.
     VFPRegister dest = VFPRegister(dest_);
     as_vxfer(src, InvalidReg, dest.uintOverlay(), CoreToFloat);
     as_vcvt(VFPRegister(dest).singleOverlay(), dest.uintOverlay());
 }
 
 void MacroAssemblerARM::convertDoubleToFloat32(const FloatRegister &src, const FloatRegister &dest,
@@ -87,30 +87,30 @@ void MacroAssemblerARM::convertDoubleToF
 // there are two options for implementing emitTruncateDouble.
 // 1) convert the floating point value to an integer, if it did not fit,
 //        then it was clamped to INT_MIN/INT_MAX, and we can test it.
 //        NOTE: if the value really was supposed to be INT_MAX / INT_MIN
 //        then it will be wrong.
 // 2) convert the floating point value to an integer, if it did not fit,
 //        then it set one or two bits in the fpcsr.  Check those.
 void
-MacroAssemblerARM::branchTruncateDouble(const FloatRegister &src, const Register &dest, Label *fail)
+MacroAssemblerARM::branchTruncateDouble(const FloatRegister &src, Register dest, Label *fail)
 {
     ma_vcvt_F64_I32(src, ScratchFloatReg);
     ma_vxfer(ScratchFloatReg, dest);
     ma_cmp(dest, Imm32(0x7fffffff));
     ma_cmp(dest, Imm32(0x80000000), Assembler::NotEqual);
     ma_b(fail, Assembler::Equal);
 }
 
 // Checks whether a double is representable as a 32-bit integer. If so, the
 // integer is written to the output register. Otherwise, a bailout is taken to
 // the given snapshot. This function overwrites the scratch float register.
 void
-MacroAssemblerARM::convertDoubleToInt32(const FloatRegister &src, const Register &dest,
+MacroAssemblerARM::convertDoubleToInt32(const FloatRegister &src, Register dest,
                                         Label *fail, bool negativeZeroCheck)
 {
     // convert the floating point value to an integer, if it did not fit,
     //     then when we convert it *back* to  a float, it will have a
     //     different value, which we can test.
     ma_vcvt_F64_I32(src, ScratchFloatReg);
     // move the value into the dest register.
     ma_vxfer(ScratchFloatReg, dest);
@@ -129,17 +129,17 @@ MacroAssemblerARM::convertDoubleToInt32(
         ma_b(fail, Assembler::Equal);
     }
 }
 
 // Checks whether a float32 is representable as a 32-bit integer. If so, the
 // integer is written to the output register. Otherwise, a bailout is taken to
 // the given snapshot. This function overwrites the scratch float register.
 void
-MacroAssemblerARM::convertFloat32ToInt32(const FloatRegister &src, const Register &dest,
+MacroAssemblerARM::convertFloat32ToInt32(const FloatRegister &src, Register dest,
                                          Label *fail, bool negativeZeroCheck)
 {
     // convert the floating point value to an integer, if it did not fit,
     //     then when we convert it *back* to  a float, it will have a
     //     different value, which we can test.
     ma_vcvt_F32_I32(src, ScratchFloatReg);
     // move the value into the dest register.
     ma_vxfer(ScratchFloatReg, dest);
@@ -160,26 +160,26 @@ MacroAssemblerARM::convertFloat32ToInt32
 }
 
 void
 MacroAssemblerARM::convertFloat32ToDouble(const FloatRegister &src, const FloatRegister &dest) {
     as_vcvt(VFPRegister(dest), VFPRegister(src).singleOverlay());
 }
 
 void
-MacroAssemblerARM::branchTruncateFloat32(const FloatRegister &src, const Register &dest, Label *fail) {
+MacroAssemblerARM::branchTruncateFloat32(const FloatRegister &src, Register dest, Label *fail) {
     ma_vcvt_F32_I32(src, ScratchFloatReg);
     ma_vxfer(ScratchFloatReg, dest);
     ma_cmp(dest, Imm32(0x7fffffff));
     ma_cmp(dest, Imm32(0x80000000), Assembler::NotEqual);
     ma_b(fail, Assembler::Equal);
 }
 
 void
-MacroAssemblerARM::convertInt32ToFloat32(const Register &src, const FloatRegister &dest_) {
+MacroAssemblerARM::convertInt32ToFloat32(Register src, const FloatRegister &dest_) {
     // direct conversions aren't possible.
     VFPRegister dest = VFPRegister(dest_).singleOverlay();
     as_vxfer(src, InvalidReg, dest.sintOverlay(),
              CoreToFloat);
     as_vcvt(dest, dest.sintOverlay());
 }
 
 void
@@ -1703,17 +1703,17 @@ MacroAssemblerARM::ma_vstr(VFPRegister s
 BufferOffset
 MacroAssemblerARM::ma_vstr(VFPRegister src, Register base, Register index, int32_t shift, Condition cc)
 {
     as_add(ScratchRegister, base, lsl(index, shift), NoSetCond, cc);
     return ma_vstr(src, Operand(ScratchRegister, 0), cc);
 }
 
 bool
-MacroAssemblerARMCompat::buildFakeExitFrame(const Register &scratch, uint32_t *offset)
+MacroAssemblerARMCompat::buildFakeExitFrame(Register scratch, uint32_t *offset)
 {
     DebugOnly<uint32_t> initialDepth = framePushed();
     uint32_t descriptor = MakeFrameDescriptor(framePushed(), JitFrame_IonJS);
 
     Push(Imm32(descriptor)); // descriptor_
 
     enterNoPool();
     DebugOnly<uint32_t> offsetBeforePush = currentOffset();
@@ -1779,17 +1779,17 @@ MacroAssemblerARMCompat::callWithExitFra
     else
         rs = L_LDR;
 
     ma_movPatchable(ImmPtr(target->raw()), ScratchRegister, Always, rs);
     ma_callIonHalfPush(ScratchRegister);
 }
 
 void
-MacroAssemblerARMCompat::callIon(const Register &callee)
+MacroAssemblerARMCompat::callIon(Register callee)
 {
     JS_ASSERT((framePushed() & 3) == 0);
     if ((framePushed() & 7) == 4) {
         ma_callIonHalfPush(callee);
     } else {
         adjustFrame(sizeof(void*));
         ma_callIon(callee);
     }
@@ -1997,87 +1997,87 @@ MacroAssemblerARMCompat::andPtr(Imm32 im
 
 void
 MacroAssemblerARMCompat::andPtr(Register src, Register dest)
 {
     ma_and(src, dest);
 }
 
 void
-MacroAssemblerARMCompat::move32(const Imm32 &imm, const Register &dest)
+MacroAssemblerARMCompat::move32(const Imm32 &imm, Register dest)
 {
     ma_mov(imm, dest);
 }
 
 void
-MacroAssemblerARMCompat::move32(const Register &src, const Register &dest) {
+MacroAssemblerARMCompat::move32(Register src, Register dest) {
     ma_mov(src, dest);
 }
 
 void
-MacroAssemblerARMCompat::movePtr(const Register &src, const Register &dest)
+MacroAssemblerARMCompat::movePtr(Register src, Register dest)
 {
     ma_mov(src, dest);
 }
 void
-MacroAssemblerARMCompat::movePtr(const ImmWord &imm, const Register &dest)
+MacroAssemblerARMCompat::movePtr(const ImmWord &imm, Register dest)
 {
     ma_mov(Imm32(imm.value), dest);
 }
 void
-MacroAssemblerARMCompat::movePtr(const ImmGCPtr &imm, const Register &dest)
+MacroAssemblerARMCompat::movePtr(const ImmGCPtr &imm, Register dest)
 {
     ma_mov(imm, dest);
 }
 void
-MacroAssemblerARMCompat::movePtr(const ImmPtr &imm, const Register &dest)
+MacroAssemblerARMCompat::movePtr(const ImmPtr &imm, Register dest)
 {
     movePtr(ImmWord(uintptr_t(imm.value)), dest);
 }
 void
-MacroAssemblerARMCompat::movePtr(const AsmJSImmPtr &imm, const Register &dest)
+MacroAssemblerARMCompat::movePtr(const AsmJSImmPtr &imm, Register dest)
 {
     RelocStyle rs;
     if (hasMOVWT())
         rs = L_MOVWT;
     else
         rs = L_LDR;
 
     enoughMemory_ &= append(AsmJSAbsoluteLink(nextOffset().getOffset(), imm.kind()));
     ma_movPatchable(Imm32(-1), dest, Always, rs);
 }
 void
-MacroAssemblerARMCompat::load8ZeroExtend(const Address &address, const Register &dest)
+MacroAssemblerARMCompat::load8ZeroExtend(const Address &address, Register dest)
 {
     ma_dataTransferN(IsLoad, 8, false, address.base, Imm32(address.offset), dest);
 }
 
 void
-MacroAssemblerARMCompat::load8ZeroExtend(const BaseIndex &src, const Register &dest)
+MacroAssemblerARMCompat::load8ZeroExtend(const BaseIndex &src, Register dest)
 {
     Register base = src.base;
     uint32_t scale = Imm32::ShiftOf(src.scale).value;
 
     if (src.offset != 0) {
         ma_mov(base, ScratchRegister);
         base = ScratchRegister;
         ma_add(base, Imm32(src.offset), base);
     }
     ma_ldrb(DTRAddr(base, DtrRegImmShift(src.index, LSL, scale)), dest);
 
 }
 
 void
-MacroAssemblerARMCompat::load8SignExtend(const Address &address, const Register &dest)
+MacroAssemblerARMCompat::load8SignExtend(const Address &address, Register dest)
 {
     ma_dataTransferN(IsLoad, 8, true, address.base, Imm32(address.offset), dest);
 }
 
 void
-MacroAssemblerARMCompat::load8SignExtend(const BaseIndex &src, const Register &dest)
+MacroAssemblerARMCompat::load8SignExtend(const BaseIndex &src, Register dest)
 {
     Register index = src.index;
 
     // ARMv7 does not have LSL on an index register with an extended load.
     if (src.scale != TimesOne) {
         ma_lsl(Imm32::ShiftOf(src.scale), index, ScratchRegister);
         index = ScratchRegister;
     }
@@ -2088,23 +2088,23 @@ MacroAssemblerARMCompat::load8SignExtend
             index = ScratchRegister;
         }
         ma_add(Imm32(src.offset), index);
     }
     ma_ldrsb(EDtrAddr(src.base, EDtrOffReg(index)), dest);
 }
 
 void
-MacroAssemblerARMCompat::load16ZeroExtend(const Address &address, const Register &dest)
+MacroAssemblerARMCompat::load16ZeroExtend(const Address &address, Register dest)
 {
     ma_dataTransferN(IsLoad, 16, false, address.base, Imm32(address.offset), dest);
 }
 
 void
-MacroAssemblerARMCompat::load16ZeroExtend(const BaseIndex &src, const Register &dest)
+MacroAssemblerARMCompat::load16ZeroExtend(const BaseIndex &src, Register dest)
 {
     Register index = src.index;
 
     // ARMv7 does not have LSL on an index register with an extended load.
     if (src.scale != TimesOne) {
         ma_lsl(Imm32::ShiftOf(src.scale), index, ScratchRegister);
         index = ScratchRegister;
     }
@@ -2115,23 +2115,23 @@ MacroAssemblerARMCompat::load16ZeroExten
             index = ScratchRegister;
         }
         ma_add(Imm32(src.offset), index);
     }
     ma_ldrh(EDtrAddr(src.base, EDtrOffReg(index)), dest);
 }
 
 void
-MacroAssemblerARMCompat::load16SignExtend(const Address &address, const Register &dest)
+MacroAssemblerARMCompat::load16SignExtend(const Address &address, Register dest)
 {
     ma_dataTransferN(IsLoad, 16, true, address.base, Imm32(address.offset), dest);
 }
 
 void
-MacroAssemblerARMCompat::load16SignExtend(const BaseIndex &src, const Register &dest)
+MacroAssemblerARMCompat::load16SignExtend(const BaseIndex &src, Register dest)
 {
     Register index = src.index;
 
     // We don't have LSL on index register yet.
     if (src.scale != TimesOne) {
         ma_lsl(Imm32::ShiftOf(src.scale), index, ScratchRegister);
         index = ScratchRegister;
     }
@@ -2142,73 +2142,73 @@ MacroAssemblerARMCompat::load16SignExten
             index = ScratchRegister;
         }
         ma_add(Imm32(src.offset), index);
     }
     ma_ldrsh(EDtrAddr(src.base, EDtrOffReg(index)), dest);
 }
 
 void
-MacroAssemblerARMCompat::load32(const Address &address, const Register &dest)
+MacroAssemblerARMCompat::load32(const Address &address, Register dest)
 {
     loadPtr(address, dest);
 }
 
 void
-MacroAssemblerARMCompat::load32(const BaseIndex &address, const Register &dest)
+MacroAssemblerARMCompat::load32(const BaseIndex &address, Register dest)
 {
     loadPtr(address, dest);
 }
 
 void
-MacroAssemblerARMCompat::load32(const AbsoluteAddress &address, const Register &dest)
+MacroAssemblerARMCompat::load32(const AbsoluteAddress &address, Register dest)
 {
     loadPtr(address, dest);
 }
 void
-MacroAssemblerARMCompat::loadPtr(const Address &address, const Register &dest)
+MacroAssemblerARMCompat::loadPtr(const Address &address, Register dest)
 {
     ma_ldr(Operand(address), dest);
 }
 
 void
-MacroAssemblerARMCompat::loadPtr(const BaseIndex &src, const Register &dest)
+MacroAssemblerARMCompat::loadPtr(const BaseIndex &src, Register dest)
 {
     Register base = src.base;
     uint32_t scale = Imm32::ShiftOf(src.scale).value;
 
     if (src.offset != 0) {
         ma_mov(base, ScratchRegister);
         base = ScratchRegister;
         ma_add(Imm32(src.offset), base);
     }
     ma_ldr(DTRAddr(base, DtrRegImmShift(src.index, LSL, scale)), dest);
 }
 void
-MacroAssemblerARMCompat::loadPtr(const AbsoluteAddress &address, const Register &dest)
+MacroAssemblerARMCompat::loadPtr(const AbsoluteAddress &address, Register dest)
 {
     movePtr(ImmWord(uintptr_t(address.addr)), ScratchRegister);
     loadPtr(Address(ScratchRegister, 0x0), dest);
 }
 void
-MacroAssemblerARMCompat::loadPtr(const AsmJSAbsoluteAddress &address, const Register &dest)
+MacroAssemblerARMCompat::loadPtr(const AsmJSAbsoluteAddress &address, Register dest)
 {
     movePtr(AsmJSImmPtr(address.kind()), ScratchRegister);
     loadPtr(Address(ScratchRegister, 0x0), dest);
 }
 
 Operand payloadOf(const Address &address) {
     return Operand(address.base, address.offset);
 }
 Operand tagOf(const Address &address) {
     return Operand(address.base, address.offset + 4);
 }
 
 void
-MacroAssemblerARMCompat::loadPrivate(const Address &address, const Register &dest)
+MacroAssemblerARMCompat::loadPrivate(const Address &address, Register dest)
 {
     ma_ldr(payloadOf(address), dest);
 }
 
 void
 MacroAssemblerARMCompat::loadDouble(const Address &address, const FloatRegister &dest)
 {
     ma_vldr(Operand(address), dest);
@@ -2275,30 +2275,30 @@ MacroAssemblerARMCompat::loadFloat32(con
 void
 MacroAssemblerARMCompat::store8(const Imm32 &imm, const Address &address)
 {
     ma_mov(imm, secondScratchReg_);
     store8(secondScratchReg_, address);
 }
 
 void
-MacroAssemblerARMCompat::store8(const Register &src, const Address &address)
+MacroAssemblerARMCompat::store8(Register src, const Address &address)
 {
     ma_dataTransferN(IsStore, 8, false, address.base, Imm32(address.offset), src);
 }
 
 void
 MacroAssemblerARMCompat::store8(const Imm32 &imm, const BaseIndex &dest)
 {
     ma_mov(imm, secondScratchReg_);
     store8(secondScratchReg_, dest);
 }
 
 void
-MacroAssemblerARMCompat::store8(const Register &src, const BaseIndex &dest)
+MacroAssemblerARMCompat::store8(Register src, const BaseIndex &dest)
 {
     Register base = dest.base;
     uint32_t scale = Imm32::ShiftOf(dest.scale).value;
 
     if (dest.offset != 0) {
         ma_add(base, Imm32(dest.offset), ScratchRegister);
         base = ScratchRegister;
     }
@@ -2308,52 +2308,52 @@ MacroAssemblerARMCompat::store8(const Re
 void
 MacroAssemblerARMCompat::store16(const Imm32 &imm, const Address &address)
 {
     ma_mov(imm, secondScratchReg_);
     store16(secondScratchReg_, address);
 }
 
 void
-MacroAssemblerARMCompat::store16(const Register &src, const Address &address)
+MacroAssemblerARMCompat::store16(Register src, const Address &address)
 {
     ma_dataTransferN(IsStore, 16, false, address.base, Imm32(address.offset), src);
 }
 
 void
 MacroAssemblerARMCompat::store16(const Imm32 &imm, const BaseIndex &dest)
 {
     ma_mov(imm, secondScratchReg_);
     store16(secondScratchReg_, dest);
 }
 void
-MacroAssemblerARMCompat::store16(const Register &src, const BaseIndex &address)
+MacroAssemblerARMCompat::store16(Register src, const BaseIndex &address)
 {
     Register index = address.index;
 
     // We don't have LSL on index register yet.
     if (address.scale != TimesOne) {
         ma_lsl(Imm32::ShiftOf(address.scale), index, ScratchRegister);
         index = ScratchRegister;
     }
 
     if (address.offset != 0) {
         ma_add(index, Imm32(address.offset), ScratchRegister);
         index = ScratchRegister;
     }
     ma_strh(src, EDtrAddr(address.base, EDtrOffReg(index)));
 }
 void
-MacroAssemblerARMCompat::store32(const Register &src, const AbsoluteAddress &address)
+MacroAssemblerARMCompat::store32(Register src, const AbsoluteAddress &address)
 {
     storePtr(src, address);
 }
 
 void
-MacroAssemblerARMCompat::store32(const Register &src, const Address &address)
+MacroAssemblerARMCompat::store32(Register src, const Address &address)
 {
     storePtr(src, address);
 }
 
 void
 MacroAssemblerARMCompat::store32(const Imm32 &src, const Address &address)
 {
     move32(src, secondScratchReg_);
@@ -2363,17 +2363,17 @@ MacroAssemblerARMCompat::store32(const I
 void
 MacroAssemblerARMCompat::store32(const Imm32 &imm, const BaseIndex &dest)
 {
     ma_mov(imm, secondScratchReg_);
     store32(secondScratchReg_, dest);
 }
 
 void
-MacroAssemblerARMCompat::store32(const Register &src, const BaseIndex &dest)
+MacroAssemblerARMCompat::store32(Register src, const BaseIndex &dest)
 {
     Register base = dest.base;
     uint32_t scale = Imm32::ShiftOf(dest.scale).value;
 
     if (dest.offset != 0) {
         ma_add(base, Imm32(dest.offset), ScratchRegister);
         base = ScratchRegister;
     }
@@ -2402,17 +2402,17 @@ MacroAssemblerARMCompat::storePtr(ImmGCP
 
 void
 MacroAssemblerARMCompat::storePtr(Register src, const Address &address)
 {
     ma_str(src, Operand(address));
 }
 
 void
-MacroAssemblerARMCompat::storePtr(const Register &src, const AbsoluteAddress &dest)
+MacroAssemblerARMCompat::storePtr(Register src, const AbsoluteAddress &dest)
 {
     movePtr(ImmWord(uintptr_t(dest.addr)), ScratchRegister);
     storePtr(src, Address(ScratchRegister, 0x0));
 }
 
 // Note: this function clobbers the input register.
 void
 MacroAssembler::clampDoubleToUint8(FloatRegister input, Register output)
@@ -2463,74 +2463,74 @@ MacroAssembler::clampDoubleToUint8(Float
         as_vcmp(ScratchFloatReg, input);
         as_vmrs(pc);
         ma_bic(Imm32(1), output, NoSetCond, Zero);
         bind(&outOfRange);
     }
 }
 
 void
-MacroAssemblerARMCompat::cmp32(const Register &lhs, const Imm32 &rhs)
+MacroAssemblerARMCompat::cmp32(Register lhs, const Imm32 &rhs)
 {
     JS_ASSERT(lhs != ScratchRegister);
     ma_cmp(lhs, rhs);
 }
 
 void
-MacroAssemblerARMCompat::cmp32(const Operand &lhs, const Register &rhs)
+MacroAssemblerARMCompat::cmp32(const Operand &lhs, Register rhs)
 {
     ma_cmp(lhs.toReg(), rhs);
 }
 
 void
 MacroAssemblerARMCompat::cmp32(const Operand &lhs, const Imm32 &rhs)
 {
     JS_ASSERT(lhs.toReg() != ScratchRegister);
     ma_cmp(lhs.toReg(), rhs);
 }
 
 void
-MacroAssemblerARMCompat::cmp32(const Register &lhs, const Register &rhs)
+MacroAssemblerARMCompat::cmp32(Register lhs, Register rhs)
 {
     ma_cmp(lhs, rhs);
 }
 
 void
-MacroAssemblerARMCompat::cmpPtr(const Register &lhs, const ImmWord &rhs)
+MacroAssemblerARMCompat::cmpPtr(Register lhs, const ImmWord &rhs)
 {
     JS_ASSERT(lhs != ScratchRegister);
     ma_cmp(lhs, Imm32(rhs.value));
 }
 
 void
-MacroAssemblerARMCompat::cmpPtr(const Register &lhs, const ImmPtr &rhs)
+MacroAssemblerARMCompat::cmpPtr(Register lhs, const ImmPtr &rhs)
 {
     return cmpPtr(lhs, ImmWord(uintptr_t(rhs.value)));
 }
 
 void
-MacroAssemblerARMCompat::cmpPtr(const Register &lhs, const Register &rhs)
+MacroAssemblerARMCompat::cmpPtr(Register lhs, Register rhs)
 {
     ma_cmp(lhs, rhs);
 }
 
 void
-MacroAssemblerARMCompat::cmpPtr(const Register &lhs, const ImmGCPtr &rhs)
+MacroAssemblerARMCompat::cmpPtr(Register lhs, const ImmGCPtr &rhs)
 {
     ma_cmp(lhs, rhs);
 }
 
 void
-MacroAssemblerARMCompat::cmpPtr(const Register &lhs, const Imm32 &rhs)
+MacroAssemblerARMCompat::cmpPtr(Register lhs, const Imm32 &rhs)
 {
     ma_cmp(lhs, rhs);
 }
 
 void
-MacroAssemblerARMCompat::cmpPtr(const Address &lhs, const Register &rhs)
+MacroAssemblerARMCompat::cmpPtr(const Address &lhs, Register rhs)
 {
     loadPtr(lhs, ScratchRegister);
     cmpPtr(ScratchRegister, rhs);
 }
 
 void
 MacroAssemblerARMCompat::cmpPtr(const Address &lhs, const ImmWord &rhs)
 {
@@ -2540,17 +2540,17 @@ MacroAssemblerARMCompat::cmpPtr(const Ad
 
 void
 MacroAssemblerARMCompat::cmpPtr(const Address &lhs, const ImmPtr &rhs)
 {
     cmpPtr(lhs, ImmWord(uintptr_t(rhs.value)));
 }
 
 void
-MacroAssemblerARMCompat::setStackArg(const Register &reg, uint32_t arg)
+MacroAssemblerARMCompat::setStackArg(Register reg, uint32_t arg)
 {
     ma_dataTransferN(IsStore, 32, true, sp, Imm32(arg * sizeof(intptr_t)), reg);
 
 }
 
 void
 MacroAssemblerARMCompat::subPtr(Imm32 imm, const Register dest)
 {
@@ -2560,23 +2560,23 @@ MacroAssemblerARMCompat::subPtr(Imm32 im
 void
 MacroAssemblerARMCompat::subPtr(const Address &addr, const Register dest)
 {
     loadPtr(addr, ScratchRegister);
     ma_sub(ScratchRegister, dest);
 }
 
 void
-MacroAssemblerARMCompat::subPtr(const Register &src, const Register &dest)
+MacroAssemblerARMCompat::subPtr(Register src, Register dest)
 {
     ma_sub(src, dest);
 }
 
 void
-MacroAssemblerARMCompat::subPtr(const Register &src, const Address &dest)
+MacroAssemblerARMCompat::subPtr(Register src, const Address &dest)
 {
     loadPtr(dest, ScratchRegister);
     ma_sub(src, ScratchRegister);
     storePtr(ScratchRegister, dest);
 }
 
 void
 MacroAssemblerARMCompat::addPtr(Imm32 imm, const Register dest)
@@ -2733,70 +2733,70 @@ MacroAssemblerARMCompat::testMagic(Assem
 Assembler::Condition
 MacroAssemblerARMCompat::testPrimitive(Assembler::Condition cond, const ValueOperand &value)
 {
     return testPrimitive(cond, value.typeReg());
 }
 
 // Register-based tests.
 Assembler::Condition
-MacroAssemblerARMCompat::testInt32(Assembler::Condition cond, const Register &tag)
+MacroAssemblerARMCompat::testInt32(Assembler::Condition cond, Register tag)
 {
     JS_ASSERT(cond == Equal || cond == NotEqual);
     ma_cmp(tag, ImmTag(JSVAL_TAG_INT32));
     return cond;
 }
 
 Assembler::Condition
-MacroAssemblerARMCompat::testBoolean(Assembler::Condition cond, const Register &tag)
+MacroAssemblerARMCompat::testBoolean(Assembler::Condition cond, Register tag)
 {
     JS_ASSERT(cond == Equal || cond == NotEqual);
     ma_cmp(tag, ImmTag(JSVAL_TAG_BOOLEAN));
     return cond;
 }
 
 Assembler::Condition
-MacroAssemblerARMCompat::testNull(Assembler::Condition cond, const Register &tag) {
+MacroAssemblerARMCompat::testNull(Assembler::Condition cond, Register tag) {
     JS_ASSERT(cond == Equal || cond == NotEqual);
     ma_cmp(tag, ImmTag(JSVAL_TAG_NULL));
     return cond;
 }
 
 Assembler::Condition
-MacroAssemblerARMCompat::testUndefined(Assembler::Condition cond, const Register &tag) {
+MacroAssemblerARMCompat::testUndefined(Assembler::Condition cond, Register tag) {
     JS_ASSERT(cond == Equal || cond == NotEqual);
     ma_cmp(tag, ImmTag(JSVAL_TAG_UNDEFINED));
     return cond;
 }
 
 Assembler::Condition
-MacroAssemblerARMCompat::testString(Assembler::Condition cond, const Register &tag) {
+MacroAssemblerARMCompat::testString(Assembler::Condition cond, Register tag) {
     JS_ASSERT(cond == Equal || cond == NotEqual);
     ma_cmp(tag, ImmTag(JSVAL_TAG_STRING));
     return cond;
 }
 
 Assembler::Condition
-MacroAssemblerARMCompat::testObject(Assembler::Condition cond, const Register &tag)
+MacroAssemblerARMCompat::testObject(Assembler::Condition cond, Register tag)
 {
     JS_ASSERT(cond == Equal || cond == NotEqual);
     ma_cmp(tag, ImmTag(JSVAL_TAG_OBJECT));
     return cond;
 }
 
 Assembler::Condition
-MacroAssemblerARMCompat::testMagic(Assembler::Condition cond, const Register &tag)
+MacroAssemblerARMCompat::testMagic(Assembler::Condition cond, Register tag)
 {
     JS_ASSERT(cond == Equal || cond == NotEqual);
     ma_cmp(tag, ImmTag(JSVAL_TAG_MAGIC));
     return cond;
 }
 
 Assembler::Condition
-MacroAssemblerARMCompat::testPrimitive(Assembler::Condition cond, const Register &tag)
+MacroAssemblerARMCompat::testPrimitive(Assembler::Condition cond, Register tag)
 {
     JS_ASSERT(cond == Equal || cond == NotEqual);
     ma_cmp(tag, ImmTag(JSVAL_UPPER_EXCL_TAG_OF_PRIMITIVE_SET));
     return cond == Equal ? Below : AboveOrEqual;
 }
 
 Assembler::Condition
 MacroAssemblerARMCompat::testGCThing(Assembler::Condition cond, const Address &address)
@@ -2877,26 +2877,26 @@ Assembler::Condition
 MacroAssemblerARMCompat::testNumber(Condition cond, const Address &address)
 {
     JS_ASSERT(cond == Equal || cond == NotEqual);
     extractTag(address, ScratchRegister);
     return testNumber(cond, ScratchRegister);
 }
 
 Assembler::Condition
-MacroAssemblerARMCompat::testDouble(Condition cond, const Register &tag)
+MacroAssemblerARMCompat::testDouble(Condition cond, Register tag)
 {
     JS_ASSERT(cond == Assembler::Equal || cond == Assembler::NotEqual);
     Condition actual = (cond == Equal) ? Below : AboveOrEqual;
     ma_cmp(tag, ImmTag(JSVAL_TAG_CLEAR));
     return actual;
 }
 
 Assembler::Condition
-MacroAssemblerARMCompat::testNumber(Condition cond, const Register &tag)
+MacroAssemblerARMCompat::testNumber(Condition cond, Register tag)
 {
     JS_ASSERT(cond == Equal || cond == NotEqual);
     ma_cmp(tag, ImmTag(JSVAL_UPPER_INCL_TAG_OF_NUMBER_SET));
     return cond == Equal ? BelowOrEqual : Above;
 }
 
 Assembler::Condition
 MacroAssemblerARMCompat::testUndefined(Condition cond, const BaseIndex &src)
@@ -3024,35 +3024,35 @@ MacroAssemblerARMCompat::branchTestValue
         branchPtr(Equal, ScratchRegister, value.typeReg(), label);
 
         bind(&fallthrough);
     }
 }
 
 // unboxing code
 void
-MacroAssemblerARMCompat::unboxInt32(const ValueOperand &operand, const Register &dest)
+MacroAssemblerARMCompat::unboxInt32(const ValueOperand &operand, Register dest)
 {
     ma_mov(operand.payloadReg(), dest);
 }
 
 void
-MacroAssemblerARMCompat::unboxInt32(const Address &src, const Register &dest)
+MacroAssemblerARMCompat::unboxInt32(const Address &src, Register dest)
 {
     ma_ldr(payloadOf(src), dest);
 }
 
 void
-MacroAssemblerARMCompat::unboxBoolean(const ValueOperand &operand, const Register &dest)
+MacroAssemblerARMCompat::unboxBoolean(const ValueOperand &operand, Register dest)
 {
     ma_mov(operand.payloadReg(), dest);
 }
 
 void
-MacroAssemblerARMCompat::unboxBoolean(const Address &src, const Register &dest)
+MacroAssemblerARMCompat::unboxBoolean(const Address &src, Register dest)
 {
     ma_ldr(payloadOf(src), dest);
 }
 
 void
 MacroAssemblerARMCompat::unboxDouble(const ValueOperand &operand, const FloatRegister &dest)
 {
     JS_ASSERT(dest != ScratchFloatReg);
@@ -3062,29 +3062,29 @@ MacroAssemblerARMCompat::unboxDouble(con
 
 void
 MacroAssemblerARMCompat::unboxDouble(const Address &src, const FloatRegister &dest)
 {
     ma_vldr(Operand(src), dest);
 }
 
 void
-MacroAssemblerARMCompat::unboxString(const ValueOperand &operand, const Register &dest)
+MacroAssemblerARMCompat::unboxString(const ValueOperand &operand, Register dest)
 {
     ma_mov(operand.payloadReg(), dest);
 }
 
 void
-MacroAssemblerARMCompat::unboxString(const Address &src, const Register &dest)
+MacroAssemblerARMCompat::unboxString(const Address &src, Register dest)
 {
     ma_ldr(payloadOf(src), dest);
 }
 
 void
-MacroAssemblerARMCompat::unboxObject(const ValueOperand &src, const Register &dest)
+MacroAssemblerARMCompat::unboxObject(const ValueOperand &src, Register dest)
 {
     ma_mov(src.payloadReg(), dest);
 }
 
 void
 MacroAssemblerARMCompat::unboxValue(const ValueOperand &src, AnyRegister dest)
 {
     if (dest.isFloat()) {
@@ -3108,17 +3108,17 @@ MacroAssemblerARMCompat::unboxPrivate(co
 
 void
 MacroAssemblerARMCompat::boxDouble(const FloatRegister &src, const ValueOperand &dest)
 {
     as_vxfer(dest.payloadReg(), dest.typeReg(), VFPRegister(src), FloatToCore);
 }
 
 void
-MacroAssemblerARMCompat::boxNonDouble(JSValueType type, const Register &src, const ValueOperand &dest) {
+MacroAssemblerARMCompat::boxNonDouble(JSValueType type, Register src, const ValueOperand &dest) {
     if (src != dest.payloadReg())
         ma_mov(src, dest.payloadReg());
     ma_mov(ImmType(type), dest.typeReg());
 }
 
 void
 MacroAssemblerARMCompat::boolValueToDouble(const ValueOperand &operand, const FloatRegister &dest)
 {
@@ -3506,17 +3506,17 @@ void
 MacroAssemblerARMCompat::linkExitFrame()
 {
     uint8_t *dest = (uint8_t*)GetIonContext()->runtime->addressOfJitTop();
     movePtr(ImmPtr(dest), ScratchRegister);
     ma_str(StackPointer, Operand(ScratchRegister, 0));
 }
 
 void
-MacroAssemblerARMCompat::linkParallelExitFrame(const Register &pt)
+MacroAssemblerARMCompat::linkParallelExitFrame(Register pt)
 {
     ma_str(StackPointer, Operand(pt, offsetof(PerThreadData, jitTop)));
 }
 
 // ARM says that all reads of pc will return 8 higher than the
 // address of the currently executing instruction.  This means we are
 // correctly storing the address of the instruction after the call
 // in the register.
@@ -3634,17 +3634,17 @@ void
 MacroAssemblerARMCompat::setupAlignedABICall(uint32_t args)
 {
     setupABICall(args);
 
     dynamicAlignment_ = false;
 }
 
 void
-MacroAssemblerARMCompat::setupUnalignedABICall(uint32_t args, const Register &scratch)
+MacroAssemblerARMCompat::setupUnalignedABICall(uint32_t args, Register scratch)
 {
     setupABICall(args);
     dynamicAlignment_ = true;
 
     ma_mov(sp, scratch);
 
     // Force sp to be aligned
     ma_and(Imm32(~(StackAlignment - 1)), sp, sp);
@@ -3785,17 +3785,17 @@ MacroAssemblerARMCompat::passABIArg(cons
 #elif defined(JS_CODEGEN_ARM_HARDFP)
     MacroAssemblerARMCompat::passHardFpABIArg(from, type);
 #else
     MacroAssemblerARMCompat::passSoftFpABIArg(from, type);
 #endif
 }
 
 void
-MacroAssemblerARMCompat::passABIArg(const Register &reg)
+MacroAssemblerARMCompat::passABIArg(Register reg)
 {
     passABIArg(MoveOperand(reg), MoveOp::GENERAL);
 }
 
 void
 MacroAssemblerARMCompat::passABIArg(const FloatRegister &freg, MoveOp::Type type)
 {
     passABIArg(MoveOperand(freg), type);
--- a/js/src/jit/arm/MacroAssembler-arm.h
+++ b/js/src/jit/arm/MacroAssembler-arm.h
@@ -55,31 +55,31 @@ class MacroAssemblerARM : public Assembl
     { }
 
     void setSecondScratchReg(Register reg) {
         JS_ASSERT(reg != ScratchRegister);
         secondScratchReg_ = reg;
     }
 
     void convertBoolToInt32(Register source, Register dest);
-    void convertInt32ToDouble(const Register &src, const FloatRegister &dest);
+    void convertInt32ToDouble(Register src, const FloatRegister &dest);
     void convertInt32ToDouble(const Address &src, FloatRegister dest);
-    void convertUInt32ToFloat32(const Register &src, const FloatRegister &dest);
-    void convertUInt32ToDouble(const Register &src, const FloatRegister &dest);
+    void convertUInt32ToFloat32(Register src, const FloatRegister &dest);
+    void convertUInt32ToDouble(Register src, const FloatRegister &dest);
     void convertDoubleToFloat32(const FloatRegister &src, const FloatRegister &dest,
                                 Condition c = Always);
-    void branchTruncateDouble(const FloatRegister &src, const Register &dest, Label *fail);
-    void convertDoubleToInt32(const FloatRegister &src, const Register &dest, Label *fail,
+    void branchTruncateDouble(const FloatRegister &src, Register dest, Label *fail);
+    void convertDoubleToInt32(const FloatRegister &src, Register dest, Label *fail,
                               bool negativeZeroCheck = true);
-    void convertFloat32ToInt32(const FloatRegister &src, const Register &dest, Label *fail,
+    void convertFloat32ToInt32(const FloatRegister &src, Register dest, Label *fail,
                                bool negativeZeroCheck = true);
 
     void convertFloat32ToDouble(const FloatRegister &src, const FloatRegister &dest);
-    void branchTruncateFloat32(const FloatRegister &src, const Register &dest, Label *fail);
-    void convertInt32ToFloat32(const Register &src, const FloatRegister &dest);
+    void branchTruncateFloat32(const FloatRegister &src, Register dest, Label *fail);
+    void convertInt32ToFloat32(Register src, const FloatRegister &dest);
     void convertInt32ToFloat32(const Address &src, FloatRegister dest);
 
     void addDouble(FloatRegister src, FloatRegister dest);
     void subDouble(FloatRegister src, FloatRegister dest);
     void mulDouble(FloatRegister src, FloatRegister dest);
     void divDouble(FloatRegister src, FloatRegister dest);
 
     void negateDouble(FloatRegister reg);
@@ -643,42 +643,42 @@ class MacroAssemblerARMCompat : public M
     void push(ImmGCPtr imm) {
         ma_mov(imm, ScratchRegister);
         ma_push(ScratchRegister);
     }
     void push(const Address &address) {
         ma_ldr(Operand(address.base, address.offset), ScratchRegister);
         ma_push(ScratchRegister);
     }
-    void push(const Register &reg) {
+    void push(Register reg) {
         ma_push(reg);
     }
     void push(const FloatRegister &reg) {
         ma_vpush(VFPRegister(reg));
     }
-    void pushWithPadding(const Register &reg, const Imm32 extraSpace) {
+    void pushWithPadding(Register reg, const Imm32 extraSpace) {
         Imm32 totSpace = Imm32(extraSpace.value + 4);
         ma_dtr(IsStore, sp, totSpace, reg, PreIndex);
     }
     void pushWithPadding(const Imm32 &imm, const Imm32 extraSpace) {
         Imm32 totSpace = Imm32(extraSpace.value + 4);
         // ma_dtr may need the scratch register to adjust the stack, so use the
         // second scratch register.
         ma_mov(imm, secondScratchReg_);
         ma_dtr(IsStore, sp, totSpace, secondScratchReg_, PreIndex);
     }
 
-    void pop(const Register &reg) {
+    void pop(Register reg) {
         ma_pop(reg);
     }
     void pop(const FloatRegister &reg) {
         ma_vpop(VFPRegister(reg));
     }
 
-    void popN(const Register &reg, Imm32 extraSpace) {
+    void popN(Register reg, Imm32 extraSpace) {
         Imm32 totSpace = Imm32(extraSpace.value + 4);
         ma_dtr(IsLoad, sp, totSpace, reg, PostIndex);
     }
 
     CodeOffsetLabel toggledJump(Label *label);
 
     // Emit a BLX or NOP instruction. ToggleCall can be used to patch
     // this instruction.
@@ -752,26 +752,26 @@ class MacroAssemblerARMCompat : public M
     Condition testString(Condition cond, const ValueOperand &value);
     Condition testObject(Condition cond, const ValueOperand &value);
     Condition testNumber(Condition cond, const ValueOperand &value);
     Condition testMagic(Condition cond, const ValueOperand &value);
 
     Condition testPrimitive(Condition cond, const ValueOperand &value);
 
     // register-based tests
-    Condition testInt32(Condition cond, const Register &tag);
-    Condition testBoolean(Condition cond, const Register &tag);
-    Condition testNull(Condition cond, const Register &tag);
-    Condition testUndefined(Condition cond, const Register &tag);
-    Condition testString(Condition cond, const Register &tag);
-    Condition testObject(Condition cond, const Register &tag);
-    Condition testDouble(Condition cond, const Register &tag);
-    Condition testNumber(Condition cond, const Register &tag);
-    Condition testMagic(Condition cond, const Register &tag);
-    Condition testPrimitive(Condition cond, const Register &tag);
+    Condition testInt32(Condition cond, Register tag);
+    Condition testBoolean(Condition cond, Register tag);
+    Condition testNull(Condition cond, Register tag);
+    Condition testUndefined(Condition cond, Register tag);
+    Condition testString(Condition cond, Register tag);
+    Condition testObject(Condition cond, Register tag);
+    Condition testDouble(Condition cond, Register tag);
+    Condition testNumber(Condition cond, Register tag);
+    Condition testMagic(Condition cond, Register tag);
+    Condition testPrimitive(Condition cond, Register tag);
 
     Condition testGCThing(Condition cond, const Address &address);
     Condition testMagic(Condition cond, const Address &address);
     Condition testInt32(Condition cond, const Address &address);
     Condition testDouble(Condition cond, const Address &address);
     Condition testBoolean(Condition cond, const Address &address);
     Condition testNull(Condition cond, const Address &address);
     Condition testUndefined(Condition cond, const Address &address);
@@ -800,35 +800,35 @@ class MacroAssemblerARMCompat : public M
         ma_b(label, c);
     }
 
     void branchTestValue(Condition cond, const ValueOperand &value, const Value &v, Label *label);
     void branchTestValue(Condition cond, const Address &valaddr, const ValueOperand &value,
                          Label *label);
 
     // unboxing code
-    void unboxInt32(const ValueOperand &operand, const Register &dest);
-    void unboxInt32(const Address &src, const Register &dest);
-    void unboxBoolean(const ValueOperand &operand, const Register &dest);
-    void unboxBoolean(const Address &src, const Register &dest);
+    void unboxInt32(const ValueOperand &operand, Register dest);
+    void unboxInt32(const Address &src, Register dest);
+    void unboxBoolean(const ValueOperand &operand, Register dest);
+    void unboxBoolean(const Address &src, Register dest);
     void unboxDouble(const ValueOperand &operand, const FloatRegister &dest);
     void unboxDouble(const Address &src, const FloatRegister &dest);
-    void unboxString(const ValueOperand &operand, const Register &dest);
-    void unboxString(const Address &src, const Register &dest);
-    void unboxObject(const ValueOperand &src, const Register &dest);
+    void unboxString(const ValueOperand &operand, Register dest);
+    void unboxString(const Address &src, Register dest);
+    void unboxObject(const ValueOperand &src, Register dest);
     void unboxValue(const ValueOperand &src, AnyRegister dest);
     void unboxPrivate(const ValueOperand &src, Register dest);
 
     void notBoolean(const ValueOperand &val) {
         ma_eor(Imm32(1), val.payloadReg());
     }
 
     // boxing code
     void boxDouble(const FloatRegister &src, const ValueOperand &dest);
-    void boxNonDouble(JSValueType type, const Register &src, const ValueOperand &dest);
+    void boxNonDouble(JSValueType type, Register src, const ValueOperand &dest);
 
     // Extended unboxing API. If the payload is already in a register, returns
     // that register. Otherwise, provides a move to the given scratch register,
     // and returns that.
     Register extractObject(const Address &address, Register scratch);
     Register extractObject(const ValueOperand &value, Register scratch) {
         return value.payloadReg();
     }
@@ -975,37 +975,37 @@ class MacroAssemblerARMCompat : public M
     void branchTestDoubleTruthy(bool truthy, const FloatRegister &reg, Label *label) {
         Condition c = testDoubleTruthy(truthy, reg);
         ma_b(label, c);
     }
     void branchTestStringTruthy(bool truthy, const ValueOperand &value, Label *label) {
         Condition c = testStringTruthy(truthy, value);
         ma_b(label, c);
     }
-    void branchTest32(Condition cond, const Register &lhs, const Register &rhs, Label *label) {
+    void branchTest32(Condition cond, Register lhs, Register rhs, Label *label) {
         // x86 likes test foo, foo rather than cmp foo, #0.
         // Convert the former into the latter.
         if (lhs == rhs && (cond == Zero || cond == NonZero))
             ma_cmp(lhs, Imm32(0));
         else
             ma_tst(lhs, rhs);
         ma_b(label, cond);
     }
-    void branchTest32(Condition cond, const Register &lhs, Imm32 imm, Label *label) {
+    void branchTest32(Condition cond, Register lhs, Imm32 imm, Label *label) {
         ma_tst(lhs, imm);
         ma_b(label, cond);
     }
     void branchTest32(Condition cond, const Address &address, Imm32 imm, Label *label) {
         ma_ldr(Operand(address.base, address.offset), ScratchRegister);
         branchTest32(cond, ScratchRegister, imm, label);
     }
-    void branchTestPtr(Condition cond, const Register &lhs, const Register &rhs, Label *label) {
+    void branchTestPtr(Condition cond, Register lhs, Register rhs, Label *label) {
         branchTest32(cond, lhs, rhs, label);
     }
-    void branchTestPtr(Condition cond, const Register &lhs, const Imm32 rhs, Label *label) {
+    void branchTestPtr(Condition cond, Register lhs, const Imm32 rhs, Label *label) {
         branchTest32(cond, lhs, rhs, label);
     }
     void branchTestPtr(Condition cond, const Address &lhs, Imm32 imm, Label *label) {
         branchTest32(cond, lhs, imm, label);
     }
     void branchPtr(Condition cond, Register lhs, Register rhs, Label *label) {
         branch32(cond, lhs, rhs, label);
     }
@@ -1021,17 +1021,17 @@ class MacroAssemblerARMCompat : public M
     }
     void branchPtr(Condition cond, Register lhs, AsmJSImmPtr imm, Label *label) {
         movePtr(imm, ScratchRegister);
         branchPtr(cond, lhs, ScratchRegister, label);
     }
     void branchPtr(Condition cond, Register lhs, Imm32 imm, Label *label) {
         branch32(cond, lhs, imm, label);
     }
-    void decBranchPtr(Condition cond, const Register &lhs, Imm32 imm, Label *label) {
+    void decBranchPtr(Condition cond, Register lhs, Imm32 imm, Label *label) {
         subPtr(imm, lhs);
         branch32(cond, lhs, Imm32(0), label);
     }
     void moveValue(const Value &val, Register type, Register data);
 
     CodeOffsetJump jumpWithPatch(RepatchLabel *label, Condition cond = Always);
     template <typename T>
     CodeOffsetJump branchPtrWithPatch(Condition cond, Register reg, T ptr, RepatchLabel *label) {
@@ -1052,32 +1052,32 @@ class MacroAssemblerARMCompat : public M
     void branchPtr(Condition cond, Address addr, ImmWord ptr, Label *label) {
         ma_ldr(addr, secondScratchReg_);
         ma_cmp(secondScratchReg_, ptr);
         ma_b(label, cond);
     }
     void branchPtr(Condition cond, Address addr, ImmPtr ptr, Label *label) {
         branchPtr(cond, addr, ImmWord(uintptr_t(ptr.value)), label);
     }
-    void branchPtr(Condition cond, const AbsoluteAddress &addr, const Register &ptr, Label *label) {
+    void branchPtr(Condition cond, const AbsoluteAddress &addr, Register ptr, Label *label) {
         loadPtr(addr, ScratchRegister);
         ma_cmp(ScratchRegister, ptr);
         ma_b(label, cond);
     }
-    void branchPtr(Condition cond, const AsmJSAbsoluteAddress &addr, const Register &ptr, Label *label) {
+    void branchPtr(Condition cond, const AsmJSAbsoluteAddress &addr, Register ptr, Label *label) {
         loadPtr(addr, ScratchRegister);
         ma_cmp(ScratchRegister, ptr);
         ma_b(label, cond);
     }
     void branch32(Condition cond, const AbsoluteAddress &lhs, Imm32 rhs, Label *label) {
         loadPtr(lhs, secondScratchReg_); // ma_cmp will use the scratch register.
         ma_cmp(secondScratchReg_, rhs);
         ma_b(label, cond);
     }
-    void branch32(Condition cond, const AbsoluteAddress &lhs, const Register &rhs, Label *label) {
+    void branch32(Condition cond, const AbsoluteAddress &lhs, Register rhs, Label *label) {
         loadPtr(lhs, secondScratchReg_); // ma_cmp will use the scratch register.
         ma_cmp(secondScratchReg_, rhs);
         ma_b(label, cond);
     }
 
     void loadUnboxedValue(Address address, MIRType type, AnyRegister dest) {
         if (dest.isFloat())
             loadInt32OrDouble(Operand(address), dest.fpu());
@@ -1192,26 +1192,26 @@ class MacroAssemblerARMCompat : public M
     void storeTypeTag(ImmTag tag, Register base, Register index, int32_t shift = defaultShift);
 
     void makeFrameDescriptor(Register frameSizeReg, FrameType type) {
         ma_lsl(Imm32(FRAMESIZE_SHIFT), frameSizeReg, frameSizeReg);
         ma_orr(Imm32(type), frameSizeReg);
     }
 
     void linkExitFrame();
-    void linkParallelExitFrame(const Register &pt);
+    void linkParallelExitFrame(Register pt);
     void handleFailureWithHandler(void *handler);
     void handleFailureWithHandlerTail();
 
     /////////////////////////////////////////////////////////////////
     // Common interface.
     /////////////////////////////////////////////////////////////////
   public:
     // The following functions are exposed for use in platform-shared code.
-    void Push(const Register &reg) {
+    void Push(Register reg) {
         ma_push(reg);
         adjustFrame(sizeof(intptr_t));
     }
     void Push(const Imm32 imm) {
         push(imm);
         adjustFrame(sizeof(intptr_t));
     }
     void Push(const ImmWord imm) {
@@ -1234,50 +1234,50 @@ class MacroAssemblerARMCompat : public M
     CodeOffsetLabel PushWithPatch(const ImmWord &word) {
         framePushed_ += sizeof(word.value);
         return pushWithPatch(word);
     }
     CodeOffsetLabel PushWithPatch(const ImmPtr &imm) {
         return PushWithPatch(ImmWord(uintptr_t(imm.value)));
     }
 
-    void PushWithPadding(const Register &reg, const Imm32 extraSpace) {
+    void PushWithPadding(Register reg, const Imm32 extraSpace) {
         pushWithPadding(reg, extraSpace);
         adjustFrame(sizeof(intptr_t) + extraSpace.value);
     }
     void PushWithPadding(const Imm32 imm, const Imm32 extraSpace) {
         pushWithPadding(imm, extraSpace);
         adjustFrame(sizeof(intptr_t) + extraSpace.value);
     }
 
-    void Pop(const Register &reg) {
+    void Pop(Register reg) {
         ma_pop(reg);
         adjustFrame(-sizeof(intptr_t));
     }
     void implicitPop(uint32_t args) {
         JS_ASSERT(args % sizeof(intptr_t) == 0);
         adjustFrame(-args);
     }
     uint32_t framePushed() const {
         return framePushed_;
     }
     void setFramePushed(uint32_t framePushed) {
         framePushed_ = framePushed;
     }
 
     // Builds an exit frame on the stack, with a return address to an internal
     // non-function. Returns offset to be passed to markSafepointAt().
-    bool buildFakeExitFrame(const Register &scratch, uint32_t *offset);
+    bool buildFakeExitFrame(Register scratch, uint32_t *offset);
 
     void callWithExitFrame(JitCode *target);
     void callWithExitFrame(JitCode *target, Register dynStack);
 
     // Makes an Ion call using the only two methods that it is sane for
     // indep code to make a call
-    void callIon(const Register &callee);
+    void callIon(Register callee);
 
     void reserveStack(uint32_t amount);
     void freeStack(uint32_t amount);
     void freeStack(Register amount);
 
     void add32(Register src, Register dest);
     void add32(Imm32 imm, Register dest);
     void add32(Imm32 imm, const Address &dest);
@@ -1303,79 +1303,79 @@ class MacroAssemblerARMCompat : public M
     void orPtr(Imm32 imm, Register dest);
     void orPtr(Register src, Register dest);
     void andPtr(Imm32 imm, Register dest);
     void andPtr(Register src, Register dest);
     void addPtr(Register src, Register dest);
     void addPtr(const Address &src, Register dest);
     void not32(Register reg);
 
-    void move32(const Imm32 &imm, const Register &dest);
-    void move32(const Register &src, const Register &dest);
+    void move32(const Imm32 &imm, Register dest);
+    void move32(Register src, Register dest);
 
-    void movePtr(const Register &src, const Register &dest);
-    void movePtr(const ImmWord &imm, const Register &dest);
-    void movePtr(const ImmPtr &imm, const Register &dest);
-    void movePtr(const AsmJSImmPtr &imm, const Register &dest);
-    void movePtr(const ImmGCPtr &imm, const Register &dest);
+    void movePtr(Register src, Register dest);
+    void movePtr(const ImmWord &imm, Register dest);
+    void movePtr(const ImmPtr &imm, Register dest);
+    void movePtr(const AsmJSImmPtr &imm, Register dest);
+    void movePtr(const ImmGCPtr &imm, Register dest);
 
-    void load8SignExtend(const Address &address, const Register &dest);
-    void load8SignExtend(const BaseIndex &src, const Register &dest);
+    void load8SignExtend(const Address &address, Register dest);
+    void load8SignExtend(const BaseIndex &src, Register dest);
 
-    void load8ZeroExtend(const Address &address, const Register &dest);
-    void load8ZeroExtend(const BaseIndex &src, const Register &dest);
+    void load8ZeroExtend(const Address &address, Register dest);
+    void load8ZeroExtend(const BaseIndex &src, Register dest);
 
-    void load16SignExtend(const Address &address, const Register &dest);
-    void load16SignExtend(const BaseIndex &src, const Register &dest);
+    void load16SignExtend(const Address &address, Register dest);
+    void load16SignExtend(const BaseIndex &src, Register dest);
 
-    void load16ZeroExtend(const Address &address, const Register &dest);
-    void load16ZeroExtend(const BaseIndex &src, const Register &dest);
+    void load16ZeroExtend(const Address &address, Register dest);
+    void load16ZeroExtend(const BaseIndex &src, Register dest);
 
-    void load32(const Address &address, const Register &dest);
-    void load32(const BaseIndex &address, const Register &dest);
-    void load32(const AbsoluteAddress &address, const Register &dest);
+    void load32(const Address &address, Register dest);
+    void load32(const BaseIndex &address, Register dest);
+    void load32(const AbsoluteAddress &address, Register dest);
 
-    void loadPtr(const Address &address, const Register &dest);
-    void loadPtr(const BaseIndex &src, const Register &dest);
-    void loadPtr(const AbsoluteAddress &address, const Register &dest);
-    void loadPtr(const AsmJSAbsoluteAddress &address, const Register &dest);
+    void loadPtr(const Address &address, Register dest);
+    void loadPtr(const BaseIndex &src, Register dest);
+    void loadPtr(const AbsoluteAddress &address, Register dest);
+    void loadPtr(const AsmJSAbsoluteAddress &address, Register dest);
 
-    void loadPrivate(const Address &address, const Register &dest);
+    void loadPrivate(const Address &address, Register dest);
 
     void loadDouble(const Address &addr, const FloatRegister &dest);
     void loadDouble(const BaseIndex &src, const FloatRegister &dest);
 
     // Load a float value into a register, then expand it to a double.
     void loadFloatAsDouble(const Address &addr, const FloatRegister &dest);
     void loadFloatAsDouble(const BaseIndex &src, const FloatRegister &dest);
 
     void loadFloat32(const Address &addr, const FloatRegister &dest);
     void loadFloat32(const BaseIndex &src, const FloatRegister &dest);
 
-    void store8(const Register &src, const Address &address);
+    void store8(Register src, const Address &address);
     void store8(const Imm32 &imm, const Address &address);
-    void store8(const Register &src, const BaseIndex &address);
+    void store8(Register src, const BaseIndex &address);
     void store8(const Imm32 &imm, const BaseIndex &address);
 
-    void store16(const Register &src, const Address &address);
+    void store16(Register src, const Address &address);
     void store16(const Imm32 &imm, const Address &address);
-    void store16(const Register &src, const BaseIndex &address);
+    void store16(Register src, const BaseIndex &address);
     void store16(const Imm32 &imm, const BaseIndex &address);
 
-    void store32(const Register &src, const AbsoluteAddress &address);
-    void store32(const Register &src, const Address &address);
-    void store32(const Register &src, const BaseIndex &address);
+    void store32(Register src, const AbsoluteAddress &address);
+    void store32(Register src, const Address &address);
+    void store32(Register src, const BaseIndex &address);
     void store32(const Imm32 &src, const Address &address);
     void store32(const Imm32 &src, const BaseIndex &address);
 
     void storePtr(ImmWord imm, const Address &address);
     void storePtr(ImmPtr imm, const Address &address);
     void storePtr(ImmGCPtr imm, const Address &address);
     void storePtr(Register src, const Address &address);
-    void storePtr(const Register &src, const AbsoluteAddress &dest);
+    void storePtr(Register src, const AbsoluteAddress &dest);
     void storeDouble(FloatRegister src, Address addr) {
         ma_vstr(src, Operand(addr));
     }
     void storeDouble(FloatRegister src, BaseIndex addr) {
         // Harder cases not handled yet.
         JS_ASSERT(addr.offset == 0);
         uint32_t scale = Imm32::ShiftOf(addr.scale).value;
         ma_vstr(src, addr.base, addr.index, scale);
@@ -1401,44 +1401,44 @@ class MacroAssemblerARMCompat : public M
         ma_mov(Imm32(0xff), reg, NoSetCond, NotEqual);
         ma_mov(Imm32(0), reg, NoSetCond, Signed);
     }
 
     void incrementInt32Value(const Address &addr) {
         add32(Imm32(1), ToPayload(addr));
     }
 
-    void cmp32(const Register &lhs, const Imm32 &rhs);
-    void cmp32(const Register &lhs, const Register &rhs);
+    void cmp32(Register lhs, const Imm32 &rhs);
+    void cmp32(Register lhs, Register rhs);
     void cmp32(const Operand &lhs, const Imm32 &rhs);
-    void cmp32(const Operand &lhs, const Register &rhs);
+    void cmp32(const Operand &lhs, Register rhs);
 
-    void cmpPtr(const Register &lhs, const ImmWord &rhs);
-    void cmpPtr(const Register &lhs, const ImmPtr &rhs);
-    void cmpPtr(const Register &lhs, const Register &rhs);
-    void cmpPtr(const Register &lhs, const ImmGCPtr &rhs);
-    void cmpPtr(const Register &lhs, const Imm32 &rhs);
-    void cmpPtr(const Address &lhs, const Register &rhs);
+    void cmpPtr(Register lhs, const ImmWord &rhs);
+    void cmpPtr(Register lhs, const ImmPtr &rhs);
+    void cmpPtr(Register lhs, Register rhs);
+    void cmpPtr(Register lhs, const ImmGCPtr &rhs);
+    void cmpPtr(Register lhs, const Imm32 &rhs);
+    void cmpPtr(const Address &lhs, Register rhs);
     void cmpPtr(const Address &lhs, const ImmWord &rhs);
     void cmpPtr(const Address &lhs, const ImmPtr &rhs);
 
     void subPtr(Imm32 imm, const Register dest);
     void subPtr(const Address &addr, const Register dest);
-    void subPtr(const Register &src, const Register &dest);
-    void subPtr(const Register &src, const Address &dest);
+    void subPtr(Register src, Register dest);
+    void subPtr(Register src, const Address &dest);
     void addPtr(Imm32 imm, const Register dest);
     void addPtr(Imm32 imm, const Address &dest);
     void addPtr(ImmWord imm, const Register dest) {
         addPtr(Imm32(imm.value), dest);
     }
     void addPtr(ImmPtr imm, const Register dest) {
         addPtr(ImmWord(uintptr_t(imm.value)), dest);
     }
 
-    void setStackArg(const Register &reg, uint32_t arg);
+    void setStackArg(Register reg, uint32_t arg);
 
     void breakpoint();
     // conditional breakpoint
     void breakpoint(Condition cc);
 
     void compareDouble(FloatRegister lhs, FloatRegister rhs);
     void branchDouble(DoubleCondition cond, const FloatRegister &lhs, const FloatRegister &rhs,
                       Label *label);
@@ -1456,30 +1456,30 @@ class MacroAssemblerARMCompat : public M
         ma_lsl(imm, dest, dest);
     }
 
     // If source is a double, load it into dest. If source is int32,
     // convert it to double. Else, branch to failure.
     void ensureDouble(const ValueOperand &source, FloatRegister dest, Label *failure);
 
     void
-    emitSet(Assembler::Condition cond, const Register &dest)
+    emitSet(Assembler::Condition cond, Register dest)
     {
         ma_mov(Imm32(0), dest);
         ma_mov(Imm32(1), dest, NoSetCond, cond);
     }
 
     template <typename T1, typename T2>
-    void cmpPtrSet(Assembler::Condition cond, T1 lhs, T2 rhs, const Register &dest)
+    void cmpPtrSet(Assembler::Condition cond, T1 lhs, T2 rhs, Register dest)
     {
         cmpPtr(lhs, rhs);
         emitSet(cond, dest);
     }
     template <typename T1, typename T2>
-    void cmp32Set(Assembler::Condition cond, T1 lhs, T2 rhs, const Register &dest)
+    void cmp32Set(Assembler::Condition cond, T1 lhs, T2 rhs, Register dest)
     {
         cmp32(lhs, rhs);
         emitSet(cond, dest);
     }
 
     void testNullSet(Condition cond, const ValueOperand &value, Register dest) {
         cond = testNull(cond, value);
         emitSet(cond, dest);
@@ -1495,25 +1495,25 @@ class MacroAssemblerARMCompat : public M
     // In order for alignment to work correctly, the MacroAssembler must have a
     // consistent view of the stack displacement. It is okay to call "push"
     // manually, however, if the stack alignment were to change, the macro
     // assembler should be notified before starting a call.
     void setupAlignedABICall(uint32_t args);
 
     // Sets up an ABI call for when the alignment is not known. This may need a
     // scratch register.
-    void setupUnalignedABICall(uint32_t args, const Register &scratch);
+    void setupUnalignedABICall(uint32_t args, Register scratch);
 
     // Arguments must be assigned in a left-to-right order. This process may
     // temporarily use more stack, in which case esp-relative addresses will be
     // automatically adjusted. It is extremely important that esp-relative
     // addresses are computed *after* setupABICall(). Furthermore, no
     // operations should be emitted while setting arguments.
     void passABIArg(const MoveOperand &from, MoveOp::Type type);
-    void passABIArg(const Register &reg);
+    void passABIArg(Register reg);
     void passABIArg(const FloatRegister &reg, MoveOp::Type type);
     void passABIArg(const ValueOperand &regs);
 
   private:
     void passHardFpABIArg(const MoveOperand &from, MoveOp::Type type);
     void passSoftFpABIArg(const MoveOperand &from, MoveOp::Type type);
 
   protected:
--- a/js/src/jit/mips/CodeGenerator-mips.cpp
+++ b/js/src/jit/mips/CodeGenerator-mips.cpp
@@ -1028,18 +1028,18 @@ CodeGeneratorMIPS::visitOutOfLineTableSw
         if (!masm.addCodeLabel(cl))
             return false;
     }
 
     return true;
 }
 
 bool
-CodeGeneratorMIPS::emitTableSwitchDispatch(MTableSwitch *mir, const Register &index,
-                                           const Register &address)
+CodeGeneratorMIPS::emitTableSwitchDispatch(MTableSwitch *mir, Register index,
+                                           Register address)
 {
     Label *defaultcase = mir->getDefault()->lir()->label();
 
     // Lower value with low value
     if (mir->low() != 0)
         masm.subPtr(Imm32(mir->low()), index);
 
     // Jump to default case if input is out of range
@@ -1834,17 +1834,17 @@ CodeGeneratorMIPS::visitLoadElementT(LLo
         }
     }
     MOZ_ASSERT(!load->mir()->needsHoleCheck());
     return true;
 }
 
 void
 CodeGeneratorMIPS::storeElementTyped(const LAllocation *value, MIRType valueType,
-                                     MIRType elementType, const Register &elements,
+                                     MIRType elementType, Register elements,
                                      const LAllocation *index)
 {
     if (index->isConstant()) {
         Address dest = Address(elements, ToInt32(index) * sizeof(Value));
         if (valueType == MIRType_Double) {
             masm.storeDouble(ToFloatRegister(value), Address(dest.base, dest.offset));
             return;
         }
--- a/js/src/jit/mips/CodeGenerator-mips.h
+++ b/js/src/jit/mips/CodeGenerator-mips.h
@@ -158,17 +158,17 @@ class CodeGeneratorMIPS : public CodeGen
         emitBranch(value.typeReg(), (Imm32)ImmType(JSVAL_TYPE_NULL), cond, ifTrue, ifFalse);
     }
     void testUndefinedEmitBranch(Assembler::Condition cond, const ValueOperand &value,
                                  MBasicBlock *ifTrue, MBasicBlock *ifFalse)
     {
         emitBranch(value.typeReg(), (Imm32)ImmType(JSVAL_TYPE_UNDEFINED), cond, ifTrue, ifFalse);
     }
 
-    bool emitTableSwitchDispatch(MTableSwitch *mir, const Register &index, const Register &base);
+    bool emitTableSwitchDispatch(MTableSwitch *mir, Register index, Register base);
 
   public:
     // Instruction visitors.
     virtual bool visitMinMaxD(LMinMaxD *ins);
     virtual bool visitAbsD(LAbsD *ins);
     virtual bool visitAbsF(LAbsF *ins);
     virtual bool visitSqrtD(LSqrtD *ins);
     virtual bool visitSqrtF(LSqrtF *ins);
@@ -225,17 +225,17 @@ class CodeGeneratorMIPS : public CodeGen
     ValueOperand ToValue(LInstruction *ins, size_t pos);
     ValueOperand ToOutValue(LInstruction *ins);
     ValueOperand ToTempValue(LInstruction *ins, size_t pos);
 
     // Functions for LTestVAndBranch.
     Register splitTagForTest(const ValueOperand &value);
 
     void storeElementTyped(const LAllocation *value, MIRType valueType, MIRType elementType,
-                           const Register &elements, const LAllocation *index);
+                           Register elements, const LAllocation *index);
 
   public:
     CodeGeneratorMIPS(MIRGenerator *gen, LIRGraph *graph, MacroAssembler *masm);
 
   public:
     bool visitBox(LBox *box);
     bool visitBoxFloatingPoint(LBoxFloatingPoint *box);
     bool visitUnbox(LUnbox *unbox);
--- a/js/src/jit/mips/MacroAssembler-mips.cpp
+++ b/js/src/jit/mips/MacroAssembler-mips.cpp
@@ -30,32 +30,32 @@ void
 MacroAssemblerMIPS::convertBoolToInt32(Register src, Register dest)
 {
     // Note that C++ bool is only 1 byte, so zero extend it to clear the
     // higher-order bits.
     ma_and(dest, src, Imm32(0xff));
 }
 
 void
-MacroAssemblerMIPS::convertInt32ToDouble(const Register &src, const FloatRegister &dest)
+MacroAssemblerMIPS::convertInt32ToDouble(Register src, const FloatRegister &dest)
 {
     as_mtc1(src, dest);
     as_cvtdw(dest, dest);
 }
 
 void
 MacroAssemblerMIPS::convertInt32ToDouble(const Address &src, FloatRegister dest)
 {
     ma_lw(ScratchRegister, src);
     as_mtc1(ScratchRegister, dest);
     as_cvtdw(dest, dest);
 }
 
 void
-MacroAssemblerMIPS::convertUInt32ToDouble(const Register &src, const FloatRegister &dest)
+MacroAssemblerMIPS::convertUInt32ToDouble(Register src, const FloatRegister &dest)
 {
     // We use SecondScratchFloatReg because MacroAssembler::loadFromTypedArray
     // calls with ScratchFloatReg as dest.
     MOZ_ASSERT(dest != SecondScratchFloatReg);
 
     // Subtract INT32_MIN to get a positive number
     ma_subu(ScratchRegister, src, Imm32(INT32_MIN));
 
@@ -64,17 +64,17 @@ MacroAssemblerMIPS::convertUInt32ToDoubl
     as_cvtdw(dest, dest);
 
     // Add unsigned value of INT32_MIN
     ma_lid(SecondScratchFloatReg, 2147483648.0);
     as_addd(dest, dest, SecondScratchFloatReg);
 }
 
 void
-MacroAssemblerMIPS::convertUInt32ToFloat32(const Register &src, const FloatRegister &dest)
+MacroAssemblerMIPS::convertUInt32ToFloat32(Register src, const FloatRegister &dest)
 {
     Label positive, done;
     ma_b(src, src, &positive, NotSigned, ShortJump);
 
     // We cannot do the same as convertUInt32ToDouble because float32 doesn't
     // have enough precision.
     convertUInt32ToDouble(src, dest);
     convertDoubleToFloat32(dest, dest);
@@ -92,31 +92,31 @@ MacroAssemblerMIPS::convertDoubleToFloat
     as_cvtsd(dest, src);
 }
 
 // Convert the floating point value to an integer, if it did not fit, then it
 // was clamped to INT32_MIN/INT32_MAX, and we can test it.
 // NOTE: if the value really was supposed to be INT32_MAX / INT32_MIN then it
 // will be wrong.
 void
-MacroAssemblerMIPS::branchTruncateDouble(const FloatRegister &src, const Register &dest,
+MacroAssemblerMIPS::branchTruncateDouble(const FloatRegister &src, Register dest,
                                          Label *fail)
 {
     Label test, success;
     as_truncwd(ScratchFloatReg, src);
     as_mfc1(dest, ScratchFloatReg);
 
     ma_b(dest, Imm32(INT32_MAX), fail, Assembler::Equal);
 }
 
 // Checks whether a double is representable as a 32-bit integer. If so, the
 // integer is written to the output register. Otherwise, a bailout is taken to
 // the given snapshot. This function overwrites the scratch float register.
 void
-MacroAssemblerMIPS::convertDoubleToInt32(const FloatRegister &src, const Register &dest,
+MacroAssemblerMIPS::convertDoubleToInt32(const FloatRegister &src, Register dest,
                                          Label *fail, bool negativeZeroCheck)
 {
     // Convert double to int, then convert back and check if we have the
     // same number.
     as_cvtwd(ScratchFloatReg, src);
     as_mfc1(dest, ScratchFloatReg);
     as_cvtdw(ScratchFloatReg, ScratchFloatReg);
     ma_bc1d(src, ScratchFloatReg, fail, Assembler::DoubleNotEqualOrUnordered);
@@ -132,17 +132,17 @@ MacroAssemblerMIPS::convertDoubleToInt32
         bind(&notZero);
     }
 }
 
 // Checks whether a float32 is representable as a 32-bit integer. If so, the
 // integer is written to the output register. Otherwise, a bailout is taken to
 // the given snapshot. This function overwrites the scratch float register.
 void
-MacroAssemblerMIPS::convertFloat32ToInt32(const FloatRegister &src, const Register &dest,
+MacroAssemblerMIPS::convertFloat32ToInt32(const FloatRegister &src, Register dest,
                                           Label *fail, bool negativeZeroCheck)
 {
     // convert the floating point value to an integer, if it did not fit, then
     // when we convert it *back* to  a float, it will have a different value,
     // which we can test.
     as_cvtws(ScratchFloatReg, src);
     as_mfc1(dest, ScratchFloatReg);
     as_cvtsw(ScratchFloatReg, ScratchFloatReg);
@@ -162,28 +162,28 @@ MacroAssemblerMIPS::convertFloat32ToInt3
 
 void
 MacroAssemblerMIPS::convertFloat32ToDouble(const FloatRegister &src, const FloatRegister &dest)
 {
     as_cvtds(dest, src);
 }
 
 void
-MacroAssemblerMIPS::branchTruncateFloat32(const FloatRegister &src, const Register &dest,
+MacroAssemblerMIPS::branchTruncateFloat32(const FloatRegister &src, Register dest,
                                           Label *fail)
 {
     Label test, success;
     as_truncws(ScratchFloatReg, src);
     as_mfc1(dest, ScratchFloatReg);
 
     ma_b(dest, Imm32(INT32_MAX), fail, Assembler::Equal);
 }
 
 void
-MacroAssemblerMIPS::convertInt32ToFloat32(const Register &src, const FloatRegister &dest)
+MacroAssemblerMIPS::convertInt32ToFloat32(Register src, const FloatRegister &dest)
 {
     as_mtc1(src, dest);
     as_cvtsw(dest, dest);
 }
 
 void
 MacroAssemblerMIPS::convertInt32ToFloat32(const Address &src, FloatRegister dest)
 {
@@ -249,17 +249,17 @@ MacroAssemblerMIPS::ma_move(Register rd,
 void
 MacroAssemblerMIPS::ma_li(Register dest, const ImmGCPtr &ptr)
 {
     writeDataRelocation(ptr);
     ma_liPatchable(dest, Imm32(ptr.value));
 }
 
 void
-MacroAssemblerMIPS::ma_li(const Register &dest, AbsoluteLabel *label)
+MacroAssemblerMIPS::ma_li(Register dest, AbsoluteLabel *label)
 {
     MOZ_ASSERT(!label->bound());
     // Thread the patch list through the unpatched address word in the
     // instruction stream.
     BufferOffset bo = m_buffer.nextOffset();
     ma_liPatchable(dest, Imm32(label->prev()));
     label->setPrev(bo.getOffset());
 }
@@ -693,17 +693,17 @@ MacroAssemblerMIPS::ma_mod_mask(Register
     }
 
     bind(&done);
 }
 
 // Memory.
 
 void
-MacroAssemblerMIPS::ma_load(const Register &dest, Address address,
+MacroAssemblerMIPS::ma_load(Register dest, Address address,
                             LoadStoreSize size, LoadStoreExtension extension)
 {
     int16_t encodedOffset;
     Register base;
     if (!Imm16::isInSignedRange(address.offset)) {
         ma_li(ScratchRegister, Imm32(address.offset));
         as_addu(ScratchRegister, address.base, ScratchRegister);
         base = ScratchRegister;
@@ -731,25 +731,25 @@ MacroAssemblerMIPS::ma_load(const Regist
         break;
       default:
         MOZ_ASSUME_UNREACHABLE("Invalid argument for ma_load");
         break;
     }
 }
 
 void
-MacroAssemblerMIPS::ma_load(const Register &dest, const BaseIndex &src,
+MacroAssemblerMIPS::ma_load(Register dest, const BaseIndex &src,
                             LoadStoreSize size, LoadStoreExtension extension)
 {
     computeScaledAddress(src, SecondScratchReg);
     ma_load(dest, Address(SecondScratchReg, src.offset), size, extension);
 }
 
 void
-MacroAssemblerMIPS::ma_store(const Register &data, Address address, LoadStoreSize size,
+MacroAssemblerMIPS::ma_store(Register data, Address address, LoadStoreSize size,
                              LoadStoreExtension extension)
 {
     int16_t encodedOffset;
     Register base;
     if (!Imm16::isInSignedRange(address.offset)) {
         ma_li(ScratchRegister, Imm32(address.offset));
         as_addu(ScratchRegister, address.base, ScratchRegister);
         base = ScratchRegister;
@@ -771,17 +771,17 @@ MacroAssemblerMIPS::ma_store(const Regis
         break;
       default:
         MOZ_ASSUME_UNREACHABLE("Invalid argument for ma_store");
         break;
     }
 }
 
 void
-MacroAssemblerMIPS::ma_store(const Register &data, const BaseIndex &dest,
+MacroAssemblerMIPS::ma_store(Register data, const BaseIndex &dest,
                              LoadStoreSize size, LoadStoreExtension extension)
 {
     computeScaledAddress(dest, SecondScratchReg);
     ma_store(data, Address(SecondScratchReg, dest.offset), size, extension);
 }
 
 void
 MacroAssemblerMIPS::ma_store(const Imm32 &imm, const BaseIndex &dest,
@@ -1457,17 +1457,17 @@ MacroAssemblerMIPS::ma_bc1d(FloatRegiste
                             DoubleCondition c, JumpKind jumpKind, FPConditionBit fcc)
 {
     FloatTestKind testKind;
     compareFloatingPoint(DoubleFloat, lhs, rhs, c, &testKind, fcc);
     branchWithCode(getBranchCode(testKind, fcc), label, jumpKind);
 }
 
 bool
-MacroAssemblerMIPSCompat::buildFakeExitFrame(const Register &scratch, uint32_t *offset)
+MacroAssemblerMIPSCompat::buildFakeExitFrame(Register scratch, uint32_t *offset)
 {
     mozilla::DebugOnly<uint32_t> initialDepth = framePushed();
 
     CodeLabel cl;
     ma_li(scratch, cl.dest());
 
     uint32_t descriptor = MakeFrameDescriptor(framePushed(), JitFrame_IonJS);
     Push(Imm32(descriptor));
@@ -1510,17 +1510,17 @@ MacroAssemblerMIPSCompat::callWithExitFr
     Push(dynStack); // descriptor
 
     addPendingJump(m_buffer.nextOffset(), ImmPtr(target->raw()), Relocation::JITCODE);
     ma_liPatchable(ScratchRegister, ImmPtr(target->raw()));
     ma_callIonHalfPush(ScratchRegister);
 }
 
 void
-MacroAssemblerMIPSCompat::callIon(const Register &callee)
+MacroAssemblerMIPSCompat::callIon(Register callee)
 {
     MOZ_ASSERT((framePushed() & 3) == 0);
     if ((framePushed() & 7) == 4) {
         ma_callIonHalfPush(callee);
     } else {
         adjustFrame(sizeof(uint32_t));
         ma_callIon(callee);
     }
@@ -1734,148 +1734,148 @@ MacroAssemblerMIPSCompat::andPtr(Imm32 i
 
 void
 MacroAssemblerMIPSCompat::andPtr(Register src, Register dest)
 {
     ma_and(dest, src);
 }
 
 void
-MacroAssemblerMIPSCompat::move32(const Imm32 &imm, const Register &dest)
+MacroAssemblerMIPSCompat::move32(const Imm32 &imm, Register dest)
 {
     ma_li(dest, imm);
 }
 
 void
-MacroAssemblerMIPSCompat::move32(const Register &src, const Register &dest)
+MacroAssemblerMIPSCompat::move32(Register src, Register dest)
 {
     ma_move(dest, src);
 }
 
 void
-MacroAssemblerMIPSCompat::movePtr(const Register &src, const Register &dest)
+MacroAssemblerMIPSCompat::movePtr(Register src, Register dest)
 {
     ma_move(dest, src);
 }
 void
-MacroAssemblerMIPSCompat::movePtr(const ImmWord &imm, const Register &dest)
+MacroAssemblerMIPSCompat::movePtr(const ImmWord &imm, Register dest)
 {
     ma_li(dest, Imm32(imm.value));
 }
 
 void
-MacroAssemblerMIPSCompat::movePtr(const ImmGCPtr &imm, const Register &dest)
+MacroAssemblerMIPSCompat::movePtr(const ImmGCPtr &imm, Register dest)
 {
     ma_li(dest, imm);
 }
 void
-MacroAssemblerMIPSCompat::movePtr(const ImmPtr &imm, const Register &dest)
+MacroAssemblerMIPSCompat::movePtr(const ImmPtr &imm, Register dest)
 {
     movePtr(ImmWord(uintptr_t(imm.value)), dest);
 }
 void
-MacroAssemblerMIPSCompat::movePtr(const AsmJSImmPtr &imm, const Register &dest)
+MacroAssemblerMIPSCompat::movePtr(const AsmJSImmPtr &imm, Register dest)
 {
     MOZ_ASSUME_UNREACHABLE("NYI");
 }
 
 void
-MacroAssemblerMIPSCompat::load8ZeroExtend(const Address &address, const Register &dest)
+MacroAssemblerMIPSCompat::load8ZeroExtend(const Address &address, Register dest)
 {
     ma_load(dest, address, SizeByte, ZeroExtend);
 }
 
 void
-MacroAssemblerMIPSCompat::load8ZeroExtend(const BaseIndex &src, const Register &dest)
+MacroAssemblerMIPSCompat::load8ZeroExtend(const BaseIndex &src, Register dest)
 {
     ma_load(dest, src, SizeByte, ZeroExtend);
 }
 
 void
-MacroAssemblerMIPSCompat::load8SignExtend(const Address &address, const Register &dest)
+MacroAssemblerMIPSCompat::load8SignExtend(const Address &address, Register dest)
 {
     ma_load(dest, address, SizeByte, SignExtend);
 }
 
 void
-MacroAssemblerMIPSCompat::load8SignExtend(const BaseIndex &src, const Register &dest)
+MacroAssemblerMIPSCompat::load8SignExtend(const BaseIndex &src, Register dest)
 {
     ma_load(dest, src, SizeByte, SignExtend);
 }
 
 void
-MacroAssemblerMIPSCompat::load16ZeroExtend(const Address &address, const Register &dest)
+MacroAssemblerMIPSCompat::load16ZeroExtend(const Address &address, Register dest)
 {
     ma_load(dest, address, SizeHalfWord, ZeroExtend);
 }
 
 void
-MacroAssemblerMIPSCompat::load16ZeroExtend(const BaseIndex &src, const Register &dest)
+MacroAssemblerMIPSCompat::load16ZeroExtend(const BaseIndex &src, Register dest)
 {
     ma_load(dest, src, SizeHalfWord, ZeroExtend);
 }
 
 void
-MacroAssemblerMIPSCompat::load16SignExtend(const Address &address, const Register &dest)
+MacroAssemblerMIPSCompat::load16SignExtend(const Address &address, Register dest)
 {
     ma_load(dest, address, SizeHalfWord, SignExtend);
 }
 
 void
-MacroAssemblerMIPSCompat::load16SignExtend(const BaseIndex &src, const Register &dest)
+MacroAssemblerMIPSCompat::load16SignExtend(const BaseIndex &src, Register dest)
 {
     ma_load(dest, src, SizeHalfWord, SignExtend);
 }
 
 void
-MacroAssemblerMIPSCompat::load32(const Address &address, const Register &dest)
+MacroAssemblerMIPSCompat::load32(const Address &address, Register dest)
 {
     ma_lw(dest, address);
 }
 
 void
-MacroAssemblerMIPSCompat::load32(const BaseIndex &address, const Register &dest)
+MacroAssemblerMIPSCompat::load32(const BaseIndex &address, Register dest)
 {
     ma_load(dest, address, SizeWord);
 }
 
 void
-MacroAssemblerMIPSCompat::load32(const AbsoluteAddress &address, const Register &dest)
+MacroAssemblerMIPSCompat::load32(const AbsoluteAddress &address, Register dest)
 {
     ma_li(ScratchRegister, Imm32((uint32_t)address.addr));
     as_lw(dest, ScratchRegister, 0);
 }
 
 void
-MacroAssemblerMIPSCompat::loadPtr(const Address &address, const Register &dest)
+MacroAssemblerMIPSCompat::loadPtr(const Address &address, Register dest)
 {
     ma_lw(dest, address);
 }
 
 void
-MacroAssemblerMIPSCompat::loadPtr(const BaseIndex &src, const Register &dest)
+MacroAssemblerMIPSCompat::loadPtr(const BaseIndex &src, Register dest)
 {
     load32(src, dest);
 }
 
 void
-MacroAssemblerMIPSCompat::loadPtr(const AbsoluteAddress &address, const Register &dest)
+MacroAssemblerMIPSCompat::loadPtr(const AbsoluteAddress &address, Register dest)
 {
     ma_li(ScratchRegister, Imm32((uint32_t)address.addr));
     as_lw(dest, ScratchRegister, 0);
 }
 void
-MacroAssemblerMIPSCompat::loadPtr(const AsmJSAbsoluteAddress &address, const Register &dest)
+MacroAssemblerMIPSCompat::loadPtr(const AsmJSAbsoluteAddress &address, Register dest)
 {
     movePtr(AsmJSImmPtr(address.kind()), ScratchRegister);
     loadPtr(Address(ScratchRegister, 0x0), dest);
 }
 
 void
-MacroAssemblerMIPSCompat::loadPrivate(const Address &address, const Register &dest)
+MacroAssemblerMIPSCompat::loadPrivate(const Address &address, Register dest)
 {
     ma_lw(dest, Address(address.base, address.offset + PAYLOAD_OFFSET));
 }
 
 void
 MacroAssemblerMIPSCompat::loadDouble(const Address &address, const FloatRegister &dest)
 {
     ma_ld(dest, address);
@@ -1918,66 +1918,66 @@ MacroAssemblerMIPSCompat::loadFloat32(co
 void
 MacroAssemblerMIPSCompat::store8(const Imm32 &imm, const Address &address)
 {
     ma_li(SecondScratchReg, imm);
     ma_store(SecondScratchReg, address, SizeByte);
 }
 
 void
-MacroAssemblerMIPSCompat::store8(const Register &src, const Address &address)
+MacroAssemblerMIPSCompat::store8(Register src, const Address &address)
 {
     ma_store(src, address, SizeByte);
 }
 
 void
 MacroAssemblerMIPSCompat::store8(const Imm32 &imm, const BaseIndex &dest)
 {
     ma_store(imm, dest, SizeByte);
 }
 
 void
-MacroAssemblerMIPSCompat::store8(const Register &src, const BaseIndex &dest)
+MacroAssemblerMIPSCompat::store8(Register src, const BaseIndex &dest)
 {
     ma_store(src, dest, SizeByte);
 }
 
 void
 MacroAssemblerMIPSCompat::store16(const Imm32 &imm, const Address &address)
 {
     ma_li(SecondScratchReg, imm);
     ma_store(SecondScratchReg, address, SizeHalfWord);
 }
 
 void
-MacroAssemblerMIPSCompat::store16(const Register &src, const Address &address)
+MacroAssemblerMIPSCompat::store16(Register src, const Address &address)
 {
     ma_store(src, address, SizeHalfWord);
 }
 
 void
 MacroAssemblerMIPSCompat::store16(const Imm32 &imm, const BaseIndex &dest)
 {
     ma_store(imm, dest, SizeHalfWord);
 }
 
 void
-MacroAssemblerMIPSCompat::store16(const Register &src, const BaseIndex &address)
+MacroAssemblerMIPSCompat::store16(Register src, const BaseIndex &address)
 {
     ma_store(src, address, SizeHalfWord);
 }
 
 void
-MacroAssemblerMIPSCompat::store32(const Register &src, const AbsoluteAddress &address)
+MacroAssemblerMIPSCompat::store32(Register src, const AbsoluteAddress &address)
 {
     storePtr(src, address);
 }
 
 void
-MacroAssemblerMIPSCompat::store32(const Register &src, const Address &address)
+MacroAssemblerMIPSCompat::store32(Register src, const Address &address)
 {
     storePtr(src, address);
 }
 
 void
 MacroAssemblerMIPSCompat::store32(const Imm32 &src, const Address &address)
 {
     move32(src, ScratchRegister);
@@ -1986,17 +1986,17 @@ MacroAssemblerMIPSCompat::store32(const 
 
 void
 MacroAssemblerMIPSCompat::store32(const Imm32 &imm, const BaseIndex &dest)
 {
     ma_store(imm, dest, SizeWord);
 }
 
 void
-MacroAssemblerMIPSCompat::store32(const Register &src, const BaseIndex &dest)
+MacroAssemblerMIPSCompat::store32(Register src, const BaseIndex &dest)
 {
     ma_store(src, dest, SizeWord);
 }
 
 void
 MacroAssemblerMIPSCompat::storePtr(ImmWord imm, const Address &address)
 {
     ma_li(ScratchRegister, Imm32(imm.value));
@@ -2018,17 +2018,17 @@ MacroAssemblerMIPSCompat::storePtr(ImmGC
 
 void
 MacroAssemblerMIPSCompat::storePtr(Register src, const Address &address)
 {
     ma_sw(src, address);
 }
 
 void
-MacroAssemblerMIPSCompat::storePtr(const Register &src, const AbsoluteAddress &dest)
+MacroAssemblerMIPSCompat::storePtr(Register src, const AbsoluteAddress &dest)
 {
     ma_li(ScratchRegister, Imm32((uint32_t)dest.addr));
     as_sw(src, ScratchRegister, 0);
 }
 
 // Note: this function clobbers the input register.
 void
 MacroAssembler::clampDoubleToUint8(FloatRegister input, Register output)
@@ -2076,17 +2076,17 @@ MacroAssembler::clampDoubleToUint8(Float
 
 void
 MacroAssemblerMIPSCompat::subPtr(Imm32 imm, const Register dest)
 {
     ma_subu(dest, dest, imm);
 }
 
 void
-MacroAssemblerMIPSCompat::subPtr(const Register &src, const Address &dest)
+MacroAssemblerMIPSCompat::subPtr(Register src, const Address &dest)
 {
     loadPtr(dest, SecondScratchReg);
     subPtr(src, SecondScratchReg);
     storePtr(SecondScratchReg, dest);
 }
 
 void
 MacroAssemblerMIPSCompat::addPtr(Imm32 imm, const Register dest)
@@ -2148,32 +2148,32 @@ MacroAssemblerMIPSCompat::branchTestGCTh
 
 void
 MacroAssemblerMIPSCompat::branchTestPrimitive(Condition cond, const ValueOperand &value,
                                               Label *label)
 {
     branchTestPrimitive(cond, value.typeReg(), label);
 }
 void
-MacroAssemblerMIPSCompat::branchTestPrimitive(Condition cond, const Register &tag, Label *label)
+MacroAssemblerMIPSCompat::branchTestPrimitive(Condition cond, Register tag, Label *label)
 {
     MOZ_ASSERT(cond == Equal || cond == NotEqual);
     ma_b(tag, ImmTag(JSVAL_UPPER_EXCL_TAG_OF_PRIMITIVE_SET), label,
          (cond == Equal) ? Below : AboveOrEqual);
 }
 
 void
 MacroAssemblerMIPSCompat::branchTestInt32(Condition cond, const ValueOperand &value, Label *label)
 {
     MOZ_ASSERT(cond == Assembler::Equal || cond == Assembler::NotEqual);
     ma_b(value.typeReg(), ImmType(JSVAL_TYPE_INT32), label, cond);
 }
 
 void
-MacroAssemblerMIPSCompat::branchTestInt32(Condition cond, const Register &tag, Label *label)
+MacroAssemblerMIPSCompat::branchTestInt32(Condition cond, Register tag, Label *label)
 {
     MOZ_ASSERT(cond == Equal || cond == NotEqual);
     ma_b(tag, ImmTag(JSVAL_TAG_INT32), label, cond);
 }
 
 void
 MacroAssemblerMIPSCompat::branchTestInt32(Condition cond, const Address &address, Label *label)
 {
@@ -2194,17 +2194,17 @@ void
 MacroAssemblerMIPSCompat:: branchTestBoolean(Condition cond, const ValueOperand &value,
                                              Label *label)
 {
     MOZ_ASSERT(cond == Assembler::Equal || cond == Assembler::NotEqual);
     ma_b(value.typeReg(), ImmType(JSVAL_TYPE_BOOLEAN), label, cond);
 }
 
 void
-MacroAssemblerMIPSCompat:: branchTestBoolean(Condition cond, const Register &tag, Label *label)
+MacroAssemblerMIPSCompat:: branchTestBoolean(Condition cond, Register tag, Label *label)
 {
     MOZ_ASSERT(cond == Assembler::Equal || cond == Assembler::NotEqual);
     ma_b(tag, ImmType(JSVAL_TYPE_BOOLEAN), label, cond);
 }
 
 void
 MacroAssemblerMIPSCompat::branchTestBoolean(Condition cond, const BaseIndex &src, Label *label)
 {
@@ -2217,17 +2217,17 @@ void
 MacroAssemblerMIPSCompat::branchTestDouble(Condition cond, const ValueOperand &value, Label *label)
 {
     MOZ_ASSERT(cond == Assembler::Equal || cond == Assembler::NotEqual);
     Assembler::Condition actual = (cond == Equal) ? Below : AboveOrEqual;
     ma_b(value.typeReg(), ImmTag(JSVAL_TAG_CLEAR), label, actual);
 }
 
 void
-MacroAssemblerMIPSCompat::branchTestDouble(Condition cond, const Register &tag, Label *label)
+MacroAssemblerMIPSCompat::branchTestDouble(Condition cond, Register tag, Label *label)
 {
     MOZ_ASSERT(cond == Assembler::Equal || cond == NotEqual);
     Condition actual = (cond == Equal) ? Below : AboveOrEqual;
     ma_b(tag, ImmTag(JSVAL_TAG_CLEAR), label, actual);
 }
 
 void
 MacroAssemblerMIPSCompat::branchTestDouble(Condition cond, const Address &address, Label *label)
@@ -2249,17 +2249,17 @@ MacroAssemblerMIPSCompat::branchTestDoub
 void
 MacroAssemblerMIPSCompat::branchTestNull(Condition cond, const ValueOperand &value, Label *label)
 {
     MOZ_ASSERT(cond == Equal || cond == NotEqual);
     ma_b(value.typeReg(), ImmType(JSVAL_TYPE_NULL), label, cond);
 }
 
 void
-MacroAssemblerMIPSCompat::branchTestNull(Condition cond, const Register &tag, Label *label)
+MacroAssemblerMIPSCompat::branchTestNull(Condition cond, Register tag, Label *label)
 {
     MOZ_ASSERT(cond == Equal || cond == NotEqual);
     ma_b(tag, ImmTag(JSVAL_TAG_NULL), label, cond);
 }
 
 void
 MacroAssemblerMIPSCompat::branchTestNull(Condition cond, const BaseIndex &src, Label *label)
 {
@@ -2277,17 +2277,17 @@ MacroAssemblerMIPSCompat::testNullSet(Co
 
 void
 MacroAssemblerMIPSCompat::branchTestObject(Condition cond, const ValueOperand &value, Label *label)
 {
     branchTestObject(cond, value.typeReg(), label);
 }
 
 void
-MacroAssemblerMIPSCompat::branchTestObject(Condition cond, const Register &tag, Label *label)
+MacroAssemblerMIPSCompat::branchTestObject(Condition cond, Register tag, Label *label)
 {
     MOZ_ASSERT(cond == Equal || cond == NotEqual);
     ma_b(tag, ImmTag(JSVAL_TAG_OBJECT), label, cond);
 }
 
 void
 MacroAssemblerMIPSCompat::branchTestObject(Condition cond, const BaseIndex &src, Label *label)
 {
@@ -2299,17 +2299,17 @@ MacroAssemblerMIPSCompat::branchTestObje
 
 void
 MacroAssemblerMIPSCompat::branchTestString(Condition cond, const ValueOperand &value, Label *label)
 {
     branchTestString(cond, value.typeReg(), label);
 }
 
 void
-MacroAssemblerMIPSCompat::branchTestString(Condition cond, const Register &tag, Label *label)
+MacroAssemblerMIPSCompat::branchTestString(Condition cond, Register tag, Label *label)
 {
     MOZ_ASSERT(cond == Equal || cond == NotEqual);
     ma_b(tag, ImmTag(JSVAL_TAG_STRING), label, cond);
 }
 
 void
 MacroAssemblerMIPSCompat::branchTestString(Condition cond, const BaseIndex &src, Label *label)
 {
@@ -2322,17 +2322,17 @@ void
 MacroAssemblerMIPSCompat::branchTestUndefined(Condition cond, const ValueOperand &value,
                                               Label *label)
 {
     MOZ_ASSERT(cond == Equal || cond == NotEqual);
     ma_b(value.typeReg(), ImmType(JSVAL_TYPE_UNDEFINED), label, cond);
 }
 
 void
-MacroAssemblerMIPSCompat::branchTestUndefined(Condition cond, const Register &tag, Label *label)
+MacroAssemblerMIPSCompat::branchTestUndefined(Condition cond, Register tag, Label *label)
 {
     MOZ_ASSERT(cond == Equal || cond == NotEqual);
     ma_b(tag, ImmTag(JSVAL_TAG_UNDEFINED), label, cond);
 }
 
 void
 MacroAssemblerMIPSCompat::branchTestUndefined(Condition cond, const BaseIndex &src, Label *label)
 {
@@ -2358,31 +2358,31 @@ MacroAssemblerMIPSCompat::testUndefinedS
 
 void
 MacroAssemblerMIPSCompat::branchTestNumber(Condition cond, const ValueOperand &value, Label *label)
 {
     branchTestNumber(cond, value.typeReg(), label);
 }
 
 void
-MacroAssemblerMIPSCompat::branchTestNumber(Condition cond, const Register &tag, Label *label)
+MacroAssemblerMIPSCompat::branchTestNumber(Condition cond, Register tag, Label *label)
 {
     MOZ_ASSERT(cond == Equal || cond == NotEqual);
     ma_b(tag, ImmTag(JSVAL_UPPER_INCL_TAG_OF_NUMBER_SET), label,
          cond == Equal ? BelowOrEqual : Above);
 }
 
 void
 MacroAssemblerMIPSCompat::branchTestMagic(Condition cond, const ValueOperand &value, Label *label)
 {
     branchTestMagic(cond, value.typeReg(), label);
 }
 
 void
-MacroAssemblerMIPSCompat::branchTestMagic(Condition cond, const Register &tag, Label *label)
+MacroAssemblerMIPSCompat::branchTestMagic(Condition cond, Register tag, Label *label)
 {
     MOZ_ASSERT(cond == Equal || cond == NotEqual);
     ma_b(tag, ImmTag(JSVAL_TAG_MAGIC), label, cond);
 }
 
 void
 MacroAssemblerMIPSCompat::branchTestMagic(Condition cond, const Address &address, Label *label)
 {
@@ -2432,35 +2432,35 @@ MacroAssemblerMIPSCompat::branchTestValu
 
     // Load payload
     ma_lw(ScratchRegister, Address(valaddr.base, valaddr.offset + PAYLOAD_OFFSET));
     branchPtr(cond, ScratchRegister, value.payloadReg(), label);
 }
 
 // unboxing code
 void
-MacroAssemblerMIPSCompat::unboxInt32(const ValueOperand &operand, const Register &dest)
+MacroAssemblerMIPSCompat::unboxInt32(const ValueOperand &operand, Register dest)
 {
     ma_move(dest, operand.payloadReg());
 }
 
 void
-MacroAssemblerMIPSCompat::unboxInt32(const Address &src, const Register &dest)
+MacroAssemblerMIPSCompat::unboxInt32(const Address &src, Register dest)
 {
     ma_lw(dest, Address(src.base, src.offset + PAYLOAD_OFFSET));
 }
 
 void
-MacroAssemblerMIPSCompat::unboxBoolean(const ValueOperand &operand, const Register &dest)
+MacroAssemblerMIPSCompat::unboxBoolean(const ValueOperand &operand, Register dest)
 {
     ma_move(dest, operand.payloadReg());
 }
 
 void
-MacroAssemblerMIPSCompat::unboxBoolean(const Address &src, const Register &dest)
+MacroAssemblerMIPSCompat::unboxBoolean(const Address &src, Register dest)
 {
     ma_lw(dest, Address(src.base, src.offset + PAYLOAD_OFFSET));
 }
 
 void
 MacroAssemblerMIPSCompat::unboxDouble(const ValueOperand &operand, const FloatRegister &dest)
 {
     MOZ_ASSERT(dest != ScratchFloatReg);
@@ -2473,29 +2473,29 @@ MacroAssemblerMIPSCompat::unboxDouble(co
 {
     ma_lw(ScratchRegister, Address(src.base, src.offset + PAYLOAD_OFFSET));
     moveToDoubleLo(ScratchRegister, dest);
     ma_lw(ScratchRegister, Address(src.base, src.offset + TAG_OFFSET));
     moveToDoubleHi(ScratchRegister, dest);
 }
 
 void
-MacroAssemblerMIPSCompat::unboxString(const ValueOperand &operand, const Register &dest)
+MacroAssemblerMIPSCompat::unboxString(const ValueOperand &operand, Register dest)
 {
     ma_move(dest, operand.payloadReg());
 }
 
 void
-MacroAssemblerMIPSCompat::unboxString(const Address &src, const Register &dest)
+MacroAssemblerMIPSCompat::unboxString(const Address &src, Register dest)
 {
     ma_lw(dest, Address(src.base, src.offset + PAYLOAD_OFFSET));
 }
 
 void
-MacroAssemblerMIPSCompat::unboxObject(const ValueOperand &src, const Register &dest)
+MacroAssemblerMIPSCompat::unboxObject(const ValueOperand &src, Register dest)
 {
     ma_move(dest, src.payloadReg());
 }
 
 void
 MacroAssemblerMIPSCompat::unboxValue(const ValueOperand &src, AnyRegister dest)
 {
     if (dest.isFloat()) {
@@ -2520,17 +2520,17 @@ MacroAssemblerMIPSCompat::unboxPrivate(c
 void
 MacroAssemblerMIPSCompat::boxDouble(const FloatRegister &src, const ValueOperand &dest)
 {
     moveFromDoubleLo(src, dest.payloadReg());
     moveFromDoubleHi(src, dest.typeReg());
 }
 
 void
-MacroAssemblerMIPSCompat::boxNonDouble(JSValueType type, const Register &src,
+MacroAssemblerMIPSCompat::boxNonDouble(JSValueType type, Register src,
                                        const ValueOperand &dest)
 {
     if (src != dest.payloadReg())
         ma_move(dest.payloadReg(), src);
     ma_li(dest.typeReg(), ImmType(type));
 }
 
 void
@@ -2909,17 +2909,17 @@ void
 MacroAssemblerMIPSCompat::linkExitFrame()
 {
     uint8_t *dest = (uint8_t*)GetIonContext()->runtime->addressOfJitTop();
     movePtr(ImmPtr(dest), ScratchRegister);
     ma_sw(StackPointer, Address(ScratchRegister, 0));
 }
 
 void
-MacroAssemblerMIPSCompat::linkParallelExitFrame(const Register &pt)
+MacroAssemblerMIPSCompat::linkParallelExitFrame(Register pt)
 {
     ma_sw(StackPointer, Address(pt, offsetof(PerThreadData, jitTop)));
 }
 
 // This macrosintruction calls the ion code and pushes the return address to
 // the stack in the case when stack is alligned.
 void
 MacroAssemblerMIPS::ma_callIon(const Register r)
@@ -2997,17 +2997,17 @@ void
 MacroAssemblerMIPSCompat::setupAlignedABICall(uint32_t args)
 {
     setupABICall(args);
 
     dynamicAlignment_ = false;
 }
 
 void
-MacroAssemblerMIPSCompat::setupUnalignedABICall(uint32_t args, const Register &scratch)
+MacroAssemblerMIPSCompat::setupUnalignedABICall(uint32_t args, Register scratch)
 {
     setupABICall(args);
     dynamicAlignment_ = true;
 
     ma_move(scratch, StackPointer);
 
     // Force sp to be aligned
     ma_subu(StackPointer, StackPointer, Imm32(sizeof(uint32_t)));
@@ -3091,17 +3091,17 @@ MacroAssemblerMIPSCompat::passABIArg(con
         passedArgTypes_ = (passedArgTypes_ << ArgType_Shift) | ArgType_General;
         break;
       default:
         MOZ_ASSUME_UNREACHABLE("Unexpected argument type");
     }
 }
 
 void
-MacroAssemblerMIPSCompat::passABIArg(const Register &reg)
+MacroAssemblerMIPSCompat::passABIArg(Register reg)
 {
     passABIArg(MoveOperand(reg), MoveOp::GENERAL);
 }
 
 void
 MacroAssemblerMIPSCompat::passABIArg(const FloatRegister &freg, MoveOp::Type type)
 {
     passABIArg(MoveOperand(freg), type);
--- a/js/src/jit/mips/MacroAssembler-mips.h
+++ b/js/src/jit/mips/MacroAssembler-mips.h
@@ -69,30 +69,30 @@ class MacroAssemblerMIPS : public Assemb
     Operand ToType(Operand base);
     Address ToType(Address base) {
         return ToType(Operand(base)).toAddress();
     }
 
   public:
 
     void convertBoolToInt32(Register source, Register dest);
-    void convertInt32ToDouble(const Register &src, const FloatRegister &dest);
+    void convertInt32ToDouble(Register src, const FloatRegister &dest);
     void convertInt32ToDouble(const Address &src, FloatRegister dest);
-    void convertUInt32ToDouble(const Register &src, const FloatRegister &dest);
-    void convertUInt32ToFloat32(const Register &src, const FloatRegister &dest);
+    void convertUInt32ToDouble(Register src, const FloatRegister &dest);
+    void convertUInt32ToFloat32(Register src, const FloatRegister &dest);
     void convertDoubleToFloat32(const FloatRegister &src, const FloatRegister &dest);
-    void branchTruncateDouble(const FloatRegister &src, const Register &dest, Label *fail);
-    void convertDoubleToInt32(const FloatRegister &src, const Register &dest, Label *fail,
+    void branchTruncateDouble(const FloatRegister &src, Register dest, Label *fail);
+    void convertDoubleToInt32(const FloatRegister &src, Register dest, Label *fail,
                               bool negativeZeroCheck = true);
-    void convertFloat32ToInt32(const FloatRegister &src, const Register &dest, Label *fail,
+    void convertFloat32ToInt32(const FloatRegister &src, Register dest, Label *fail,
                                bool negativeZeroCheck = true);
 
     void convertFloat32ToDouble(const FloatRegister &src, const FloatRegister &dest);
-    void branchTruncateFloat32(const FloatRegister &src, const Register &dest, Label *fail);
-    void convertInt32ToFloat32(const Register &src, const FloatRegister &dest);
+    void branchTruncateFloat32(const FloatRegister &src, Register dest, Label *fail);
+    void convertInt32ToFloat32(Register src, const FloatRegister &dest);
     void convertInt32ToFloat32(const Address &src, FloatRegister dest);
 
 
     void addDouble(FloatRegister src, FloatRegister dest);
     void subDouble(FloatRegister src, FloatRegister dest);
     void mulDouble(FloatRegister src, FloatRegister dest);
     void divDouble(FloatRegister src, FloatRegister dest);
 
@@ -100,17 +100,17 @@ class MacroAssemblerMIPS : public Assemb
     void inc64(AbsoluteAddress dest);
 
   public:
 
     void ma_move(Register rd, Register rs);
 
     void ma_li(Register dest, const ImmGCPtr &ptr);
 
-    void ma_li(const Register &dest, AbsoluteLabel *label);
+    void ma_li(Register dest, AbsoluteLabel *label);
 
     void ma_li(Register dest, Imm32 imm);
     void ma_liPatchable(Register dest, Imm32 imm);
     void ma_liPatchable(Register dest, ImmPtr imm);
 
     // Shift operations
     void ma_sll(Register rd, Register rt, Imm32 shift);
     void ma_srl(Register rd, Register rt, Imm32 shift);
@@ -143,25 +143,25 @@ class MacroAssemblerMIPS : public Assemb
 
     // xor
     void ma_xor(Register rd, Register rs);
     void ma_xor(Register rd, Register rs, Register rt);
     void ma_xor(Register rd, Imm32 imm);
     void ma_xor(Register rd, Register rs, Imm32 imm);
 
     // load
-    void ma_load(const Register &dest, Address address, LoadStoreSize size = SizeWord,
+    void ma_load(Register dest, Address address, LoadStoreSize size = SizeWord,
                  LoadStoreExtension extension = SignExtend);
-    void ma_load(const Register &dest, const BaseIndex &src, LoadStoreSize size = SizeWord,
+    void ma_load(Register dest, const BaseIndex &src, LoadStoreSize size = SizeWord,
                  LoadStoreExtension extension = SignExtend);
 
     // store
-    void ma_store(const Register &data, Address address, LoadStoreSize size = SizeWord,
+    void ma_store(Register data, Address address, LoadStoreSize size = SizeWord,
                   LoadStoreExtension extension = SignExtend);
-    void ma_store(const Register &data, const BaseIndex &dest, LoadStoreSize size = SizeWord,
+    void ma_store(Register data, const BaseIndex &dest, LoadStoreSize size = SizeWord,
                   LoadStoreExtension extension = SignExtend);
     void ma_store(const Imm32 &imm, const BaseIndex &dest, LoadStoreSize size = SizeWord,
                   LoadStoreExtension extension = SignExtend);
 
     void computeScaledAddress(const BaseIndex &address, Register dest);
 
     void computeEffectiveAddress(const Address &address, Register dest) {
         ma_addu(dest, address.base, Imm32(address.offset));
@@ -455,23 +455,23 @@ class MacroAssemblerMIPSCompat : public 
     void push(ImmGCPtr imm) {
         ma_li(ScratchRegister, imm);
         ma_push(ScratchRegister);
     }
     void push(const Address &address) {
         ma_lw(ScratchRegister, address);
         ma_push(ScratchRegister);
     }
-    void push(const Register &reg) {
+    void push(Register reg) {
         ma_push(reg);
     }
     void push(const FloatRegister &reg) {
         ma_push(reg);
     }
-    void pop(const Register &reg) {
+    void pop(Register reg) {
         ma_pop(reg);
     }
     void pop(const FloatRegister &reg) {
         ma_pop(reg);
     }
 
     // Emit a branch that can be toggled to a non-operation. On MIPS we use
     // "andi" instruction to toggle the branch.
@@ -526,42 +526,42 @@ class MacroAssemblerMIPSCompat : public 
     Register splitTagForTest(const ValueOperand &value) {
         return value.typeReg();
     }
 
     void branchTestGCThing(Condition cond, const Address &address, Label *label);
     void branchTestGCThing(Condition cond, const BaseIndex &src, Label *label);
 
     void branchTestPrimitive(Condition cond, const ValueOperand &value, Label *label);
-    void branchTestPrimitive(Condition cond, const Register &tag, Label *label);
+    void branchTestPrimitive(Condition cond, Register tag, Label *label);
 
     void branchTestValue(Condition cond, const ValueOperand &value, const Value &v, Label *label);
     void branchTestValue(Condition cond, const Address &valaddr, const ValueOperand &value,
                          Label *label);
 
     // unboxing code
-    void unboxInt32(const ValueOperand &operand, const Register &dest);
-    void unboxInt32(const Address &src, const Register &dest);
-    void unboxBoolean(const ValueOperand &operand, const Register &dest);
-    void unboxBoolean(const Address &src, const Register &dest);
+    void unboxInt32(const ValueOperand &operand, Register dest);
+    void unboxInt32(const Address &src, Register dest);
+    void unboxBoolean(const ValueOperand &operand, Register dest);
+    void unboxBoolean(const Address &src, Register dest);
     void unboxDouble(const ValueOperand &operand, const FloatRegister &dest);
     void unboxDouble(const Address &src, const FloatRegister &dest);
-    void unboxString(const ValueOperand &operand, const Register &dest);
-    void unboxString(const Address &src, const Register &dest);
-    void unboxObject(const ValueOperand &src, const Register &dest);
+    void unboxString(const ValueOperand &operand, Register dest);
+    void unboxString(const Address &src, Register dest);
+    void unboxObject(const ValueOperand &src, Register dest);
     void unboxValue(const ValueOperand &src, AnyRegister dest);
     void unboxPrivate(const ValueOperand &src, Register dest);
 
     void notBoolean(const ValueOperand &val) {
         as_xori(val.payloadReg(), val.payloadReg(), 1);
     }
 
     // boxing code
     void boxDouble(const FloatRegister &src, const ValueOperand &dest);
-    void boxNonDouble(JSValueType type, const Register &src, const ValueOperand &dest);
+    void boxNonDouble(JSValueType type, Register src, const ValueOperand &dest);
 
     // Extended unboxing API. If the payload is already in a register, returns
     // that register. Otherwise, provides a move to the given scratch register,
     // and returns that.
     Register extractObject(const Address &address, Register scratch);
     Register extractObject(const ValueOperand &value, Register scratch) {
         return value.payloadReg();
     }
@@ -584,22 +584,22 @@ class MacroAssemblerMIPSCompat : public 
                            const FloatRegister &dest, int32_t shift = defaultShift);
     void loadConstantDouble(double dp, const FloatRegister &dest);
 
     void boolValueToFloat32(const ValueOperand &operand, const FloatRegister &dest);
     void int32ValueToFloat32(const ValueOperand &operand, const FloatRegister &dest);
     void loadConstantFloat32(float f, const FloatRegister &dest);
 
     void branchTestInt32(Condition cond, const ValueOperand &value, Label *label);
-    void branchTestInt32(Condition cond, const Register &tag, Label *label);
+    void branchTestInt32(Condition cond, Register tag, Label *label);
     void branchTestInt32(Condition cond, const Address &address, Label *label);
     void branchTestInt32(Condition cond, const BaseIndex &src, Label *label);
 
     void branchTestBoolean(Condition cond, const ValueOperand &value, Label *label);
-    void branchTestBoolean(Condition cond, const Register &tag, Label *label);
+    void branchTestBoolean(Condition cond, Register tag, Label *label);
     void branchTestBoolean(Condition cond, const BaseIndex &src, Label *label);
 
     void branch32(Condition cond, Register lhs, Register rhs, Label *label) {
         ma_b(lhs, rhs, label, cond);
     }
     void branch32(Condition cond, Register lhs, Imm32 imm, Label *label) {
         ma_b(lhs, imm, label, cond);
     }
@@ -637,44 +637,44 @@ class MacroAssemblerMIPSCompat : public 
         branchPtr(cond, lhs, ptr, label);
     }
 
     void branchPrivatePtr(Condition cond, Register lhs, ImmWord ptr, Label *label) {
         branchPtr(cond, lhs, ptr, label);
     }
 
     void branchTestDouble(Condition cond, const ValueOperand &value, Label *label);
-    void branchTestDouble(Condition cond, const Register &tag, Label *label);
+    void branchTestDouble(Condition cond, Register tag, Label *label);
     void branchTestDouble(Condition cond, const Address &address, Label *label);
     void branchTestDouble(Condition cond, const BaseIndex &src, Label *label);
 
     void branchTestNull(Condition cond, const ValueOperand &value, Label *label);
-    void branchTestNull(Condition cond, const Register &tag, Label *label);
+    void branchTestNull(Condition cond, Register tag, Label *label);
     void branchTestNull(Condition cond, const BaseIndex &src, Label *label);
     void testNullSet(Condition cond, const ValueOperand &value, Register dest);
 
     void branchTestObject(Condition cond, const ValueOperand &value, Label *label);
-    void branchTestObject(Condition cond, const Register &tag, Label *label);
+    void branchTestObject(Condition cond, Register tag, Label *label);
     void branchTestObject(Condition cond, const BaseIndex &src, Label *label);
 
     void branchTestString(Condition cond, const ValueOperand &value, Label *label);
-    void branchTestString(Condition cond, const Register &tag, Label *label);
+    void branchTestString(Condition cond, Register tag, Label *label);
     void branchTestString(Condition cond, const BaseIndex &src, Label *label);
 
     void branchTestUndefined(Condition cond, const ValueOperand &value, Label *label);
-    void branchTestUndefined(Condition cond, const Register &tag, Label *label);
+    void branchTestUndefined(Condition cond, Register tag, Label *label);
     void branchTestUndefined(Condition cond, const BaseIndex &src, Label *label);
     void branchTestUndefined(Condition cond, const Address &address, Label *label);
     void testUndefinedSet(Condition cond, const ValueOperand &value, Register dest);
 
     void branchTestNumber(Condition cond, const ValueOperand &value, Label *label);
-    void branchTestNumber(Condition cond, const Register &tag, Label *label);
+    void branchTestNumber(Condition cond, Register tag, Label *label);
 
     void branchTestMagic(Condition cond, const ValueOperand &value, Label *label);
-    void branchTestMagic(Condition cond, const Register &tag, Label *label);
+    void branchTestMagic(Condition cond, Register tag, Label *label);
     void branchTestMagic(Condition cond, const Address &address, Label *label);
     void branchTestMagic(Condition cond, const BaseIndex &src, Label *label);
 
     void branchTestMagicValue(Condition cond, const ValueOperand &val, JSWhyMagic why,
                               Label *label) {
         MOZ_ASSERT(cond == Equal || cond == NotEqual);
         // Test for magic
         Label notmagic;
@@ -687,37 +687,37 @@ class MacroAssemblerMIPSCompat : public 
     void branchTestInt32Truthy(bool b, const ValueOperand &value, Label *label);
 
     void branchTestStringTruthy(bool b, const ValueOperand &value, Label *label);
 
     void branchTestDoubleTruthy(bool b, const FloatRegister &value, Label *label);
 
     void branchTestBooleanTruthy(bool b, const ValueOperand &operand, Label *label);
 
-    void branchTest32(Condition cond, const Register &lhs, const Register &rhs, Label *label) {
+    void branchTest32(Condition cond, Register lhs, Register rhs, Label *label) {
         MOZ_ASSERT(cond == Zero || cond == NonZero || cond == Signed || cond == NotSigned);
         if (lhs == rhs) {
             ma_b(lhs, rhs, label, cond);
         } else {
             as_and(ScratchRegister, lhs, rhs);
             ma_b(ScratchRegister, ScratchRegister, label, cond);
         }
     }
-    void branchTest32(Condition cond, const Register &lhs, Imm32 imm, Label *label) {
+    void branchTest32(Condition cond, Register lhs, Imm32 imm, Label *label) {
         ma_li(ScratchRegister, imm);
         branchTest32(cond, lhs, ScratchRegister, label);
     }
     void branchTest32(Condition cond, const Address &address, Imm32 imm, Label *label) {
         ma_lw(SecondScratchReg, address);
         branchTest32(cond, SecondScratchReg, imm, label);
     }
-    void branchTestPtr(Condition cond, const Register &lhs, const Register &rhs, Label *label) {
+    void branchTestPtr(Condition cond, Register lhs, Register rhs, Label *label) {
         branchTest32(cond, lhs, rhs, label);
     }
-    void branchTestPtr(Condition cond, const Register &lhs, const Imm32 rhs, Label *label) {
+    void branchTestPtr(Condition cond, Register lhs, const Imm32 rhs, Label *label) {
         branchTest32(cond, lhs, rhs, label);
     }
     void branchTestPtr(Condition cond, const Address &lhs, Imm32 imm, Label *label) {
         branchTest32(cond, lhs, imm, label);
     }
     void branchPtr(Condition cond, Register lhs, Register rhs, Label *label) {
         ma_b(lhs, rhs, label, cond);
     }
@@ -733,17 +733,17 @@ class MacroAssemblerMIPSCompat : public 
     }
     void branchPtr(Condition cond, Register lhs, AsmJSImmPtr imm, Label *label) {
         movePtr(imm, ScratchRegister);
         branchPtr(cond, lhs, ScratchRegister, label);
     }
     void branchPtr(Condition cond, Register lhs, Imm32 imm, Label *label) {
         ma_b(lhs, imm, label, cond);
     }
-    void decBranchPtr(Condition cond, const Register &lhs, Imm32 imm, Label *label) {
+    void decBranchPtr(Condition cond, Register lhs, Imm32 imm, Label *label) {
         subPtr(imm, lhs);
         branch32(cond, lhs, Imm32(0), label);
     }
 
 protected:
     uint32_t getType(const Value &val);
     void moveData(const Value &val, Register data);
 public:
@@ -778,30 +778,30 @@ public:
     }
     void branchPtr(Condition cond, Address addr, ImmWord ptr, Label *label) {
         ma_lw(SecondScratchReg, addr);
         ma_b(SecondScratchReg, Imm32(ptr.value), label, cond);
     }
     void branchPtr(Condition cond, Address addr, ImmPtr ptr, Label *label) {
         branchPtr(cond, addr, ImmWord(uintptr_t(ptr.value)), label);
     }
-    void branchPtr(Condition cond, const AbsoluteAddress &addr, const Register &ptr, Label *label) {
+    void branchPtr(Condition cond, const AbsoluteAddress &addr, Register ptr, Label *label) {
         loadPtr(addr, ScratchRegister);
         ma_b(ScratchRegister, ptr, label, cond);
     }
-    void branchPtr(Condition cond, const AsmJSAbsoluteAddress &addr, const Register &ptr,
+    void branchPtr(Condition cond, const AsmJSAbsoluteAddress &addr, Register ptr,
                    Label *label) {
         loadPtr(addr, ScratchRegister);
         ma_b(ScratchRegister, ptr, label, cond);
     }
     void branch32(Condition cond, const AbsoluteAddress &lhs, Imm32 rhs, Label *label) {
         loadPtr(lhs, SecondScratchReg); // ma_b might use scratch
         ma_b(SecondScratchReg, rhs, label, cond);
     }
-    void branch32(Condition cond, const AbsoluteAddress &lhs, const Register &rhs, Label *label) {
+    void branch32(Condition cond, const AbsoluteAddress &lhs, Register rhs, Label *label) {
         loadPtr(lhs, ScratchRegister);
         ma_b(ScratchRegister, rhs, label, cond);
     }
 
     void loadUnboxedValue(Address address, MIRType type, AnyRegister dest) {
         if (dest.isFloat())
             loadInt32OrDouble(address, dest.fpu());
         else
@@ -890,26 +890,26 @@ public:
     void storeTypeTag(ImmTag tag, Register base, Register index, int32_t shift = defaultShift);
 
     void makeFrameDescriptor(Register frameSizeReg, FrameType type) {
         ma_sll(frameSizeReg, frameSizeReg, Imm32(FRAMESIZE_SHIFT));
         ma_or(frameSizeReg, frameSizeReg, Imm32(type));
     }
 
     void linkExitFrame();
-    void linkParallelExitFrame(const Register &pt);
+    void linkParallelExitFrame(Register pt);
     void handleFailureWithHandler(void *handler);
     void handleFailureWithHandlerTail();
 
     /////////////////////////////////////////////////////////////////
     // Common interface.
     /////////////////////////////////////////////////////////////////
   public:
     // The following functions are exposed for use in platform-shared code.
-    void Push(const Register &reg) {
+    void Push(Register reg) {
         ma_push(reg);
         adjustFrame(sizeof(intptr_t));
     }
     void Push(const Imm32 imm) {
         ma_li(ScratchRegister, imm);
         ma_push(ScratchRegister);
         adjustFrame(sizeof(intptr_t));
     }
@@ -934,41 +934,41 @@ public:
     CodeOffsetLabel PushWithPatch(const ImmWord &word) {
         framePushed_ += sizeof(word.value);
         return pushWithPatch(word);
     }
     CodeOffsetLabel PushWithPatch(const ImmPtr &imm) {
         return PushWithPatch(ImmWord(uintptr_t(imm.value)));
     }
 
-    void Pop(const Register &reg) {
+    void Pop(Register reg) {
         ma_pop(reg);
         adjustFrame(-sizeof(intptr_t));
     }
     void implicitPop(uint32_t args) {
         MOZ_ASSERT(args % sizeof(intptr_t) == 0);
         adjustFrame(-args);
     }
     uint32_t framePushed() const {
         return framePushed_;
     }
     void setFramePushed(uint32_t framePushed) {
         framePushed_ = framePushed;
     }
 
     // Builds an exit frame on the stack, with a return address to an internal
     // non-function. Returns offset to be passed to markSafepointAt().
-    bool buildFakeExitFrame(const Register &scratch, uint32_t *offset);
+    bool buildFakeExitFrame(Register scratch, uint32_t *offset);
 
     void callWithExitFrame(JitCode *target);
     void callWithExitFrame(JitCode *target, Register dynStack);
 
     // Makes an Ion call using the only two methods that it is sane for
     // indep code to make a call
-    void callIon(const Register &callee);
+    void callIon(Register callee);
 
     void reserveStack(uint32_t amount);
     void freeStack(uint32_t amount);
     void freeStack(Register amount);
 
     void add32(Register src, Register dest);
     void add32(Imm32 imm, Register dest);
     void add32(Imm32 imm, const Address &dest);
@@ -1015,79 +1015,79 @@ public:
     void orPtr(Register src, Register dest);
     void andPtr(Imm32 imm, Register dest);
     void andPtr(Register src, Register dest);
     void addPtr(Register src, Register dest);
     void subPtr(Register src, Register dest);
     void addPtr(const Address &src, Register dest);
     void not32(Register reg);
 
-    void move32(const Imm32 &imm, const Register &dest);
-    void move32(const Register &src, const Register &dest);
+    void move32(const Imm32 &imm, Register dest);
+    void move32(Register src, Register dest);
 
-    void movePtr(const Register &src, const Register &dest);
-    void movePtr(const ImmWord &imm, const Register &dest);
-    void movePtr(const ImmPtr &imm, const Register &dest);
-    void movePtr(const AsmJSImmPtr &imm, const Register &dest);
-    void movePtr(const ImmGCPtr &imm, const Register &dest);
+    void movePtr(Register src, Register dest);
+    void movePtr(const ImmWord &imm, Register dest);
+    void movePtr(const ImmPtr &imm, Register dest);
+    void movePtr(const AsmJSImmPtr &imm, Register dest);
+    void movePtr(const ImmGCPtr &imm, Register dest);
 
-    void load8SignExtend(const Address &address, const Register &dest);
-    void load8SignExtend(const BaseIndex &src, const Register &dest);
+    void load8SignExtend(const Address &address, Register dest);
+    void load8SignExtend(const BaseIndex &src, Register dest);
 
-    void load8ZeroExtend(const Address &address, const Register &dest);
-    void load8ZeroExtend(const BaseIndex &src, const Register &dest);
+    void load8ZeroExtend(const Address &address, Register dest);
+    void load8ZeroExtend(const BaseIndex &src, Register dest);
 
-    void load16SignExtend(const Address &address, const Register &dest);
-    void load16SignExtend(const BaseIndex &src, const Register &dest);
+    void load16SignExtend(const Address &address, Register dest);
+    void load16SignExtend(const BaseIndex &src, Register dest);
 
-    void load16ZeroExtend(const Address &address, const Register &dest);
-    void load16ZeroExtend(const BaseIndex &src, const Register &dest);
+    void load16ZeroExtend(const Address &address, Register dest);
+    void load16ZeroExtend(const BaseIndex &src, Register dest);
 
-    void load32(const Address &address, const Register &dest);
-    void load32(const BaseIndex &address, const Register &dest);
-    void load32(const AbsoluteAddress &address, const Register &dest);
+    void load32(const Address &address, Register dest);
+    void load32(const BaseIndex &address, Register dest);
+    void load32(const AbsoluteAddress &address, Register dest);
 
-    void loadPtr(const Address &address, const Register &dest);
-    void loadPtr(const BaseIndex &src, const Register &dest);
-    void loadPtr(const AbsoluteAddress &address, const Register &dest);
-    void loadPtr(const AsmJSAbsoluteAddress &address, const Register &dest);
+    void loadPtr(const Address &address, Register dest);
+    void loadPtr(const BaseIndex &src, Register dest);
+    void loadPtr(const AbsoluteAddress &address, Register dest);
+    void loadPtr(const AsmJSAbsoluteAddress &address, Register dest);
 
-    void loadPrivate(const Address &address, const Register &dest);
+    void loadPrivate(const Address &address, Register dest);
 
     void loadDouble(const Address &addr, const FloatRegister &dest);
     void loadDouble(const BaseIndex &src, const FloatRegister &dest);
 
     // Load a float value into a register, then expand it to a double.
     void loadFloatAsDouble(const Address &addr, const FloatRegister &dest);
     void loadFloatAsDouble(const BaseIndex &src, const FloatRegister &dest);
 
     void loadFloat32(const Address &addr, const FloatRegister &dest);
     void loadFloat32(const BaseIndex &src, const FloatRegister &dest);
 
-    void store8(const Register &src, const Address &address);
+    void store8(Register src, const Address &address);
     void store8(const Imm32 &imm, const Address &address);
-    void store8(const Register &src, const BaseIndex &address);
+    void store8(Register src, const BaseIndex &address);
     void store8(const Imm32 &imm, const BaseIndex &address);
 
-    void store16(const Register &src, const Address &address);
+    void store16(Register src, const Address &address);
     void store16(const Imm32 &imm, const Address &address);
-    void store16(const Register &src, const BaseIndex &address);
+    void store16(Register src, const BaseIndex &address);
     void store16(const Imm32 &imm, const BaseIndex &address);
 
-    void store32(const Register &src, const AbsoluteAddress &address);
-    void store32(const Register &src, const Address &address);
-    void store32(const Register &src, const BaseIndex &address);
+    void store32(Register src, const AbsoluteAddress &address);
+    void store32(Register src, const Address &address);
+    void store32(Register src, const BaseIndex &address);
     void store32(const Imm32 &src, const Address &address);
     void store32(const Imm32 &src, const BaseIndex &address);
 
     void storePtr(ImmWord imm, const Address &address);
     void storePtr(ImmPtr imm, const Address &address);
     void storePtr(ImmGCPtr imm, const Address &address);
     void storePtr(Register src, const Address &address);
-    void storePtr(const Register &src, const AbsoluteAddress &dest);
+    void storePtr(Register src, const AbsoluteAddress &dest);
     void storeDouble(FloatRegister src, Address addr) {
         ma_sd(src, addr);
     }
     void storeDouble(FloatRegister src, BaseIndex addr) {
         MOZ_ASSERT(addr.offset == 0);
         ma_sd(src, addr);
     }
     void moveDouble(FloatRegister src, FloatRegister dest) {
@@ -1126,17 +1126,17 @@ public:
             {
                 ma_move(reg, zero);
             }
         }
         bind(&done);
     }
 
     void subPtr(Imm32 imm, const Register dest);
-    void subPtr(const Register &src, const Address &dest);
+    void subPtr(Register src, const Address &dest);
     void addPtr(Imm32 imm, const Register dest);
     void addPtr(Imm32 imm, const Address &dest);
     void addPtr(ImmWord imm, const Register dest) {
         addPtr(Imm32(imm.value), dest);
     }
     void addPtr(ImmPtr imm, const Register dest) {
         addPtr(ImmWord(uintptr_t(imm.value)), dest);
     }
@@ -1160,47 +1160,47 @@ public:
         ma_sll(dest, dest, imm);
     }
 
     // If source is a double, load it into dest. If source is int32,
     // convert it to double. Else, branch to failure.
     void ensureDouble(const ValueOperand &source, FloatRegister dest, Label *failure);
 
     template <typename T1, typename T2>
-    void cmpPtrSet(Assembler::Condition cond, T1 lhs, T2 rhs, const Register &dest)
+    void cmpPtrSet(Assembler::Condition cond, T1 lhs, T2 rhs, Register dest)
     {
         ma_cmp_set(dest, lhs, rhs, cond);
     }
 
     template <typename T1, typename T2>
-    void cmp32Set(Assembler::Condition cond, T1 lhs, T2 rhs, const Register &dest)
+    void cmp32Set(Assembler::Condition cond, T1 lhs, T2 rhs, Register dest)
     {
         ma_cmp_set(dest, lhs, rhs, cond);
     }
 
     // Setup a call to C/C++ code, given the number of general arguments it
     // takes. Note that this only supports cdecl.
     //
     // In order for alignment to work correctly, the MacroAssembler must have a
     // consistent view of the stack displacement. It is okay to call "push"
     // manually, however, if the stack alignment were to change, the macro
     // assembler should be notified before starting a call.
     void setupAlignedABICall(uint32_t args);
 
     // Sets up an ABI call for when the alignment is not known. This may need a
     // scratch register.
-    void setupUnalignedABICall(uint32_t args, const Register &scratch);
+    void setupUnalignedABICall(uint32_t args, Register scratch);
 
     // Arguments must be assigned in a left-to-right order. This process may
     // temporarily use more stack, in which case sp-relative addresses will be
     // automatically adjusted. It is extremely important that sp-relative
     // addresses are computed *after* setupABICall(). Furthermore, no
     // operations should be emitted while setting arguments.
     void passABIArg(const MoveOperand &from, MoveOp::Type type);
-    void passABIArg(const Register &reg);
+    void passABIArg(Register reg);
     void passABIArg(const FloatRegister &reg, MoveOp::Type type);
     void passABIArg(const ValueOperand &regs);
 
   protected:
     bool buildOOLFakeExitFrame(void *fakeReturnAddr);
 
   private:
     void callWithABIPre(uint32_t *stackAdjust);
--- a/js/src/jit/shared/Assembler-x86-shared.h
+++ b/js/src/jit/shared/Assembler-x86-shared.h
@@ -328,23 +328,23 @@ class AssemblerX86Shared : public Assemb
     void writeDoubleConstant(double d, Label *label) {
         label->bind(masm.size());
         masm.doubleConstant(d);
     }
     void writeFloatConstant(float f, Label *label) {
         label->bind(masm.size());
         masm.floatConstant(f);
     }
-    void movl(const Imm32 &imm32, const Register &dest) {
+    void movl(const Imm32 &imm32, Register dest) {
         masm.movl_i32r(imm32.value, dest.code());
     }
-    void movl(const Register &src, const Register &dest) {
+    void movl(Register src, Register dest) {
         masm.movl_rr(src.code(), dest.code());
     }
-    void movl(const Operand &src, const Register &dest) {
+    void movl(const Operand &src, Register dest) {
         switch (src.kind()) {
           case Operand::REG:
             masm.movl_rr(src.reg(), dest.code());
             break;
           case Operand::MEM_REG_DISP:
             masm.movl_mr(src.disp(), src.base(), dest.code());
             break;
           case Operand::MEM_SCALE:
@@ -352,17 +352,17 @@ class AssemblerX86Shared : public Assemb
             break;
           case Operand::MEM_ADDRESS32:
             masm.movl_mr(src.address(), dest.code());
             break;
           default:
             MOZ_ASSUME_UNREACHABLE("unexpected operand kind");
         }
     }
-    void movl(const Register &src, const Operand &dest) {
+    void movl(Register src, const Operand &dest) {
         switch (dest.kind()) {
           case Operand::REG:
             masm.movl_rr(src.code(), dest.reg());
             break;
           case Operand::MEM_REG_DISP:
             masm.movl_rm(src.code(), dest.disp(), dest.base());
             break;
           case Operand::MEM_SCALE:
@@ -386,17 +386,17 @@ class AssemblerX86Shared : public Assemb
           case Operand::MEM_SCALE:
             masm.movl_i32m(imm32.value, dest.disp(), dest.base(), dest.index(), dest.scale());
             break;
           default:
             MOZ_ASSUME_UNREACHABLE("unexpected operand kind");
         }
     }
 
-    void xchgl(const Register &src, const Register &dest) {
+    void xchgl(Register src, Register dest) {
         masm.xchgl_rr(src.code(), dest.code());
     }
 
     // Eventually movapd and movaps should be overloaded to support loads and
     // stores too.
     void movapd(const FloatRegister &src, const FloatRegister &dest) {
         JS_ASSERT(HasSSE2());
         masm.movapd_rr(src.code(), dest.code());
@@ -462,41 +462,41 @@ class AssemblerX86Shared : public Assemb
     void cvtss2sd(const FloatRegister &src, const FloatRegister &dest) {
         JS_ASSERT(HasSSE2());
         masm.cvtss2sd_rr(src.code(), dest.code());
     }
     void cvtsd2ss(const FloatRegister &src, const FloatRegister &dest) {
         JS_ASSERT(HasSSE2());
         masm.cvtsd2ss_rr(src.code(), dest.code());
     }
-    void movzbl(const Operand &src, const Register &dest) {
+    void movzbl(const Operand &src, Register dest) {
         switch (src.kind()) {
           case Operand::MEM_REG_DISP:
             masm.movzbl_mr(src.disp(), src.base(), dest.code());
             break;
           case Operand::MEM_SCALE:
             masm.movzbl_mr(src.disp(), src.base(), src.index(), src.scale(), dest.code());
             break;
           default:
             MOZ_ASSUME_UNREACHABLE("unexpected operand kind");
         }
     }
-    void movsbl(const Operand &src, const Register &dest) {
+    void movsbl(const Operand &src, Register dest) {
         switch (src.kind()) {
           case Operand::MEM_REG_DISP:
             masm.movsbl_mr(src.disp(), src.base(), dest.code());
             break;
           case Operand::MEM_SCALE:
             masm.movsbl_mr(src.disp(), src.base(), src.index(), src.scale(), dest.code());
             break;
           default:
             MOZ_ASSUME_UNREACHABLE("unexpected operand kind");
         }
     }
-    void movb(const Register &src, const Operand &dest) {
+    void movb(Register src, const Operand &dest) {
         switch (dest.kind()) {
           case Operand::MEM_REG_DISP:
             masm.movb_rm(src.code(), dest.disp(), dest.base());
             break;
           case Operand::MEM_SCALE:
             masm.movb_rm(src.code(), dest.disp(), dest.base(), dest.index(), dest.scale());
             break;
           default:
@@ -510,35 +510,35 @@ class AssemblerX86Shared : public Assemb
             break;
           case Operand::MEM_SCALE:
             masm.movb_i8m(src.value, dest.disp(), dest.base(), dest.index(), dest.scale());
             break;
           default:
             MOZ_ASSUME_UNREACHABLE("unexpected operand kind");
         }
     }
-    void movzwl(const Operand &src, const Register &dest) {
+    void movzwl(const Operand &src, Register dest) {
         switch (src.kind()) {
           case Operand::REG:
             masm.movzwl_rr(src.reg(), dest.code());
             break;
           case Operand::MEM_REG_DISP:
             masm.movzwl_mr(src.disp(), src.base(), dest.code());
             break;
           case Operand::MEM_SCALE:
             masm.movzwl_mr(src.disp(), src.base(), src.index(), src.scale(), dest.code());
             break;
           default:
             MOZ_ASSUME_UNREACHABLE("unexpected operand kind");
         }
     }
-    void movzwl(const Register &src, const Register &dest) {
+    void movzwl(Register src, Register dest) {
         masm.movzwl_rr(src.code(), dest.code());
     }
-    void movw(const Register &src, const Operand &dest) {
+    void movw(Register src, const Operand &dest) {
         switch (dest.kind()) {
           case Operand::MEM_REG_DISP:
             masm.movw_rm(src.code(), dest.disp(), dest.base());
             break;
           case Operand::MEM_SCALE:
             masm.movw_rm(src.code(), dest.disp(), dest.base(), dest.index(), dest.scale());
             break;
           default:
@@ -552,29 +552,29 @@ class AssemblerX86Shared : public Assemb
             break;
           case Operand::MEM_SCALE:
             masm.movw_i16m(src.value, dest.disp(), dest.base(), dest.index(), dest.scale());
             break;
           default:
             MOZ_ASSUME_UNREACHABLE("unexpected operand kind");
         }
     }
-    void movswl(const Operand &src, const Register &dest) {
+    void movswl(const Operand &src, Register dest) {
         switch (src.kind()) {
           case Operand::MEM_REG_DISP:
             masm.movswl_mr(src.disp(), src.base(), dest.code());
             break;
           case Operand::MEM_SCALE:
             masm.movswl_mr(src.disp(), src.base(), src.index(), src.scale(), dest.code());
             break;
           default:
             MOZ_ASSUME_UNREACHABLE("unexpected operand kind");
         }
     }
-    void leal(const Operand &src, const Register &dest) {
+    void leal(const Operand &src, Register dest) {
         switch (src.kind()) {
           case Operand::MEM_REG_DISP:
             masm.leal_mr(src.disp(), src.base(), dest.code());
             break;
           case Operand::MEM_SCALE:
             masm.leal_mr(src.disp(), src.base(), src.index(), src.scale(), dest.code());
             break;
           default:
@@ -748,17 +748,17 @@ class AssemblerX86Shared : public Assemb
         if (label->bound()) {
             masm.linkJump(masm.call(), JmpDst(label->offset()));
         } else {
             JmpSrc j = masm.call();
             JmpSrc prev = JmpSrc(label->use(j.offset()));
             masm.setNextJump(j, prev);
         }
     }
-    void call(const Register &reg) {
+    void call(Register reg) {
         masm.call(reg.code());
     }
     void call(const Operand &op) {
         switch (op.kind()) {
           case Operand::REG:
             masm.call(op.reg());
             break;
           case Operand::MEM_REG_DISP:
@@ -783,32 +783,32 @@ class AssemblerX86Shared : public Assemb
     }
     static bool HasSSE41() {
         return JSC::MacroAssembler::isSSE41Present();
     }
 
     // The below cmpl methods switch the lhs and rhs when it invokes the
     // macroassembler to conform with intel standard.  When calling this
     // function put the left operand on the left as you would expect.
-    void cmpl(const Register &lhs, const Register &rhs) {
+    void cmpl(Register lhs, Register rhs) {
         masm.cmpl_rr(rhs.code(), lhs.code());
     }
-    void cmpl(const Register &lhs, const Operand &rhs) {
+    void cmpl(Register lhs, const Operand &rhs) {
         switch (rhs.kind()) {
           case Operand::REG:
             masm.cmpl_rr(rhs.reg(), lhs.code());
             break;
           case Operand::MEM_REG_DISP:
             masm.cmpl_mr(rhs.disp(), rhs.base(), lhs.code());
             break;
           default:
             MOZ_ASSUME_UNREACHABLE("unexpected operand kind");
         }
     }
-    void cmpl(const Register &src, Imm32 imm) {
+    void cmpl(Register src, Imm32 imm) {
         masm.cmpl_ir(imm.value, src.code());
     }
     void cmpl(const Operand &op, Imm32 imm) {
         switch (op.kind()) {
           case Operand::REG:
             masm.cmpl_ir(imm.value, op.reg());
             break;
           case Operand::MEM_REG_DISP:
@@ -819,17 +819,17 @@ class AssemblerX86Shared : public Assemb
             break;
           case Operand::MEM_ADDRESS32:
             masm.cmpl_im(imm.value, op.address());
             break;
           default:
             MOZ_ASSUME_UNREACHABLE("unexpected operand kind");
         }
     }
-    void cmpl(const Operand &lhs, const Register &rhs) {
+    void cmpl(const Operand &lhs, Register rhs) {
         switch (lhs.kind()) {
           case Operand::REG:
             masm.cmpl_rr(rhs.code(), lhs.reg());
             break;
           case Operand::MEM_REG_DISP:
             masm.cmpl_rm(rhs.code(), lhs.disp(), lhs.base());
             break;
           case Operand::MEM_ADDRESS32:
@@ -852,51 +852,51 @@ class AssemblerX86Shared : public Assemb
             break;
           default:
             MOZ_ASSUME_UNREACHABLE("unexpected operand kind");
         }
     }
     void cmpl(const Operand &op, ImmPtr imm) {
         cmpl(op, ImmWord(uintptr_t(imm.value)));
     }
-    void cmpw(const Register &lhs, const Register &rhs) {
+    void cmpw(Register lhs, Register rhs) {
         masm.cmpw_rr(lhs.code(), rhs.code());
     }
-    void setCC(Condition cond, const Register &r) {
+    void setCC(Condition cond, Register r) {
         masm.setCC_r(static_cast<JSC::X86Assembler::Condition>(cond), r.code());
     }
-    void testb(const Register &lhs, const Register &rhs) {
+    void testb(Register lhs, Register rhs) {
         JS_ASSERT(GeneralRegisterSet(Registers::SingleByteRegs).has(lhs));
         JS_ASSERT(GeneralRegisterSet(Registers::SingleByteRegs).has(rhs));
         masm.testb_rr(rhs.code(), lhs.code());
     }
-    void testw(const Register &lhs, const Register &rhs) {
+    void testw(Register lhs, Register rhs) {
         masm.testw_rr(rhs.code(), lhs.code());
     }
-    void testl(const Register &lhs, const Register &rhs) {
+    void testl(Register lhs, Register rhs) {
         masm.testl_rr(rhs.code(), lhs.code());
     }
-    void testl(const Register &lhs, Imm32 rhs) {
+    void testl(Register lhs, Imm32 rhs) {
         masm.testl_i32r(rhs.value, lhs.code());
     }
     void testl(const Operand &lhs, Imm32 rhs) {
         switch (lhs.kind()) {
           case Operand::REG:
             masm.testl_i32r(rhs.value, lhs.reg());
             break;
           case Operand::MEM_REG_DISP:
             masm.testl_i32m(rhs.value, lhs.disp(), lhs.base());
             break;
           default:
             MOZ_ASSUME_UNREACHABLE("unexpected operand kind");
             break;
         }
     }
 
-    void addl(Imm32 imm, const Register &dest) {
+    void addl(Imm32 imm, Register dest) {
         masm.addl_ir(imm.value, dest.code());
     }
     void addl(Imm32 imm, const Operand &op) {
         switch (op.kind()) {
           case Operand::REG:
             masm.addl_ir(imm.value, op.reg());
             break;
           case Operand::MEM_REG_DISP:
@@ -904,176 +904,176 @@ class AssemblerX86Shared : public Assemb
             break;
           case Operand::MEM_ADDRESS32:
             masm.addl_im(imm.value, op.address());
             break;
           default:
             MOZ_ASSUME_UNREACHABLE("unexpected operand kind");
         }
     }
-    void subl(Imm32 imm, const Register &dest) {
+    void subl(Imm32 imm, Register dest) {
         masm.subl_ir(imm.value, dest.code());
     }
     void subl(Imm32 imm, const Operand &op) {
         switch (op.kind()) {
           case Operand::REG:
             masm.subl_ir(imm.value, op.reg());
             break;
           case Operand::MEM_REG_DISP:
             masm.subl_im(imm.value, op.disp(), op.base());
             break;
           default:
             MOZ_ASSUME_UNREACHABLE("unexpected operand kind");
         }
     }
-    void addl(const Register &src, const Register &dest) {
+    void addl(Register src, Register dest) {
         masm.addl_rr(src.code(), dest.code());
     }
-    void subl(const Register &src, const Register &dest) {
+    void subl(Register src, Register dest) {
         masm.subl_rr(src.code(), dest.code());
     }
-    void subl(const Operand &src, const Register &dest) {
+    void subl(const Operand &src, Register dest) {
         switch (src.kind()) {
           case Operand::REG:
             masm.subl_rr(src.reg(), dest.code());
             break;
           case Operand::MEM_REG_DISP:
             masm.subl_mr(src.disp(), src.base(), dest.code());
             break;
           default:
             MOZ_ASSUME_UNREACHABLE("unexpected operand kind");
         }
     }
-    void subl(const Register &src, const Operand &dest) {
+    void subl(Register src, const Operand &dest) {
         switch (dest.kind()) {
           case Operand::REG:
             masm.subl_rr(src.code(), dest.reg());
             break;
           case Operand::MEM_REG_DISP:
             masm.subl_rm(src.code(), dest.disp(), dest.base());
             break;
           default:
             MOZ_ASSUME_UNREACHABLE("unexpected operand kind");
         }
     }
-    void orl(const Register &reg, const Register &dest) {
+    void orl(Register reg, Register dest) {
         masm.orl_rr(reg.code(), dest.code());
     }
-    void orl(Imm32 imm, const Register &reg) {
+    void orl(Imm32 imm, Register reg) {
         masm.orl_ir(imm.value, reg.code());
     }
     void orl(Imm32 imm, const Operand &op) {
         switch (op.kind()) {
           case Operand::REG:
             masm.orl_ir(imm.value, op.reg());
             break;
           case Operand::MEM_REG_DISP:
             masm.orl_im(imm.value, op.disp(), op.base());
             break;
           default:
             MOZ_ASSUME_UNREACHABLE("unexpected operand kind");
         }
     }
-    void xorl(const Register &src, const Register &dest) {
+    void xorl(Register src, Register dest) {
         masm.xorl_rr(src.code(), dest.code());
     }
-    void xorl(Imm32 imm, const Register &reg) {
+    void xorl(Imm32 imm, Register reg) {
         masm.xorl_ir(imm.value, reg.code());
     }
     void xorl(Imm32 imm, const Operand &op) {
         switch (op.kind()) {
           case Operand::REG:
             masm.xorl_ir(imm.value, op.reg());
             break;
           case Operand::MEM_REG_DISP:
             masm.xorl_im(imm.value, op.disp(), op.base());
             break;
           default:
             MOZ_ASSUME_UNREACHABLE("unexpected operand kind");
         }
     }
-    void andl(const Register &src, const Register &dest) {
+    void andl(Register src, Register dest) {
         masm.andl_rr(src.code(), dest.code());
     }
-    void andl(Imm32 imm, const Register &dest) {
+    void andl(Imm32 imm, Register dest) {
         masm.andl_ir(imm.value, dest.code());
     }
     void andl(Imm32 imm, const Operand &op) {
         switch (op.kind()) {
           case Operand::REG:
             masm.andl_ir(imm.value, op.reg());
             break;
           case Operand::MEM_REG_DISP:
             masm.andl_im(imm.value, op.disp(), op.base());
             break;
           default:
             MOZ_ASSUME_UNREACHABLE("unexpected operand kind");
         }
     }
-    void addl(const Operand &src, const Register &dest) {
+    void addl(const Operand &src, Register dest) {
         switch (src.kind()) {
           case Operand::REG:
             masm.addl_rr(src.reg(), dest.code());
             break;
           case Operand::MEM_REG_DISP:
             masm.addl_mr(src.disp(), src.base(), dest.code());
             break;
           default:
             MOZ_ASSUME_UNREACHABLE("unexpected operand kind");
         }
     }
-    void orl(const Operand &src, const Register &dest) {
+    void orl(const Operand &src, Register dest) {
         switch (src.kind()) {
           case Operand::REG:
             masm.orl_rr(src.reg(), dest.code());
             break;
           case Operand::MEM_REG_DISP:
             masm.orl_mr(src.disp(), src.base(), dest.code());
             break;
           default:
             MOZ_ASSUME_UNREACHABLE("unexpected operand kind");
         }
     }
-    void xorl(const Operand &src, const Register &dest) {
+    void xorl(const Operand &src, Register dest) {
         switch (src.kind()) {
           case Operand::REG:
             masm.xorl_rr(src.reg(), dest.code());
             break;
           case Operand::MEM_REG_DISP:
             masm.xorl_mr(src.disp(), src.base(), dest.code());
             break;
           default:
             MOZ_ASSUME_UNREACHABLE("unexpected operand kind");
         }
     }
-    void andl(const Operand &src, const Register &dest) {
+    void andl(const Operand &src, Register dest) {
         switch (src.kind()) {
           case Operand::REG:
             masm.andl_rr(src.reg(), dest.code());
             break;
           case Operand::MEM_REG_DISP:
             masm.andl_mr(src.disp(), src.base(), dest.code());
             break;
           default:
             MOZ_ASSUME_UNREACHABLE("unexpected operand kind");
         }
     }
-    void imull(const Register &multiplier) {
+    void imull(Register multiplier) {
         masm.imull_r(multiplier.code());
     }
-    void imull(Imm32 imm, const Register &dest) {
+    void imull(Imm32 imm, Register dest) {
         masm.imull_i32r(dest.code(), imm.value, dest.code());
     }
-    void imull(const Register &src, const Register &dest) {
+    void imull(Register src, Register dest) {
         masm.imull_rr(src.code(), dest.code());
     }
-    void imull(Imm32 imm, const Register &src, const Register &dest) {
+    void imull(Imm32 imm, Register src, Register dest) {
         masm.imull_i32r(src.code(), imm.value, dest.code());
     }
-    void imull(const Operand &src, const Register &dest) {
+    void imull(const Operand &src, Register dest) {
         switch (src.kind()) {
           case Operand::REG:
             masm.imull_rr(src.reg(), dest.code());
             break;
           case Operand::MEM_REG_DISP:
             masm.imull_mr(src.disp(), src.base(), dest.code());
             break;
           default:
@@ -1087,50 +1087,50 @@ class AssemblerX86Shared : public Assemb
             break;
           case Operand::MEM_REG_DISP:
             masm.negl_m(src.disp(), src.base());
             break;
           default:
             MOZ_ASSUME_UNREACHABLE("unexpected operand kind");
         }
     }
-    void negl(const Register &reg) {
+    void negl(Register reg) {
         masm.negl_r(reg.code());
     }
     void notl(const Operand &src) {
         switch (src.kind()) {
           case Operand::REG:
             masm.notl_r(src.reg());
             break;
           case Operand::MEM_REG_DISP:
             masm.notl_m(src.disp(), src.base());
             break;
           default:
             MOZ_ASSUME_UNREACHABLE("unexpected operand kind");
         }
     }
-    void notl(const Register &reg) {
+    void notl(Register reg) {
         masm.notl_r(reg.code());
     }
-    void shrl(const Imm32 imm, const Register &dest) {
+    void shrl(const Imm32 imm, Register dest) {
         masm.shrl_i8r(imm.value, dest.code());
     }
-    void shll(const Imm32 imm, const Register &dest) {
+    void shll(const Imm32 imm, Register dest) {
         masm.shll_i8r(imm.value, dest.code());
     }
-    void sarl(const Imm32 imm, const Register &dest) {
+    void sarl(const Imm32 imm, Register dest) {
         masm.sarl_i8r(imm.value, dest.code());
     }
-    void shrl_cl(const Register &dest) {
+    void shrl_cl(Register dest) {
         masm.shrl_CLr(dest.code());
     }
-    void shll_cl(const Register &dest) {
+    void shll_cl(Register dest) {
         masm.shll_CLr(dest.code());
     }
-    void sarl_cl(const Register &dest) {
+    void sarl_cl(Register dest) {
         masm.sarl_CLr(dest.code());
     }
 
     void incl(const Operand &op) {
         switch (op.kind()) {
           case Operand::MEM_REG_DISP:
             masm.incl_m32(op.disp(), op.base());
             break;
@@ -1152,28 +1152,28 @@ class AssemblerX86Shared : public Assemb
             MOZ_ASSUME_UNREACHABLE("unexpected operand kind");
         }
     }
     void lock_decl(const Operand &op) {
         masm.prefix_lock();
         decl(op);
     }
 
-    void lock_cmpxchg32(const Register &src, const Operand &op) {
+    void lock_cmpxchg32(Register src, const Operand &op) {
         masm.prefix_lock();
         switch (op.kind()) {
           case Operand::MEM_REG_DISP:
             masm.cmpxchg32(src.code(), op.disp(), op.base());
             break;
           default:
             MOZ_ASSUME_UNREACHABLE("unexpected operand kind");
         }
     }
 
-    void xaddl(const Register &srcdest, const Operand &mem) {
+    void xaddl(Register srcdest, const Operand &mem) {
         switch (mem.kind()) {
           case Operand::MEM_REG_DISP:
             masm.xaddl_rm(srcdest.code(), mem.disp(), mem.base());
             break;
           case Operand::MEM_SCALE:
             masm.xaddl_rm(srcdest.code(), mem.disp(), mem.base(), mem.index(), mem.scale());
             break;
           default:
@@ -1192,17 +1192,17 @@ class AssemblerX86Shared : public Assemb
             break;
           case Operand::MEM_REG_DISP:
             masm.push_m(src.disp(), src.base());
             break;
           default:
             MOZ_ASSUME_UNREACHABLE("unexpected operand kind");
         }
     }
-    void push(const Register &src) {
+    void push(Register src) {
         masm.push_r(src.code());
     }
     void push(const Address &src) {
         masm.push_m(src.offset, src.base.code());
     }
 
     void pop(const Operand &src) {
         switch (src.kind()) {
@@ -1211,17 +1211,17 @@ class AssemblerX86Shared : public Assemb
             break;
           case Operand::MEM_REG_DISP:
             masm.pop_m(src.disp(), src.base());
             break;
           default:
             MOZ_ASSUME_UNREACHABLE("unexpected operand kind");
         }
     }
-    void pop(const Register &src) {
+    void pop(Register src) {
         masm.pop_r(src.code());
     }
 
     void pushFlags() {
         masm.push_flags();
     }
     void popFlags() {
         masm.pop_flags();
@@ -1232,17 +1232,17 @@ class AssemblerX86Shared : public Assemb
         masm.pusha();
     }
     void popAllRegs() {
         masm.popa();
     }
 #endif
 
     // Zero-extend byte to 32-bit integer.
-    void movzbl(const Register &src, const Register &dest) {
+    void movzbl(Register src, Register dest) {
         masm.movzbl_rr(src.code(), dest.code());
     }
 
     void cdq() {
         masm.cdq();
     }
     void idiv(Register divisor) {
         masm.idivl_r(divisor.code());
@@ -1250,17 +1250,17 @@ class AssemblerX86Shared : public Assemb
     void udiv(Register divisor) {
         masm.divl_r(divisor.code());
     }
 
     void unpcklps(const FloatRegister &src, const FloatRegister &dest) {
         JS_ASSERT(HasSSE2());
         masm.unpcklps_rr(src.code(), dest.code());
     }
-    void pinsrd(const Register &src, const FloatRegister &dest) {
+    void pinsrd(Register src, const FloatRegister &dest) {
         JS_ASSERT(HasSSE2());
         masm.pinsrd_rr(src.code(), dest.code());
     }
     void pinsrd(const Operand &src, const FloatRegister &dest) {
         JS_ASSERT(HasSSE2());
         switch (src.kind()) {
           case Operand::REG:
             masm.pinsrd_rr(src.reg(), dest.code());
@@ -1296,21 +1296,21 @@ class AssemblerX86Shared : public Assemb
             break;
           case Operand::MEM_SCALE:
             masm.cvtsi2sd_mr(src.disp(), src.base(), src.index(), src.scale(), dest.code());
             break;
           default:
             MOZ_ASSUME_UNREACHABLE("unexpected operand kind");
         }
     }
-    void cvttsd2si(const FloatRegister &src, const Register &dest) {
+    void cvttsd2si(const FloatRegister &src, Register dest) {
         JS_ASSERT(HasSSE2());
         masm.cvttsd2si_rr(src.code(), dest.code());
     }
-    void cvttss2si(const FloatRegister &src, const Register &dest) {
+    void cvttss2si(const FloatRegister &src, Register dest) {
         JS_ASSERT(HasSSE2());
         masm.cvttss2si_rr(src.code(), dest.code());
     }
     void cvtsi2ss(const Operand &src, const FloatRegister &dest) {
         JS_ASSERT(HasSSE2());
         switch (src.kind()) {
           case Operand::REG:
             masm.cvtsi2ss_rr(src.reg(), dest.code());
@@ -1320,29 +1320,29 @@ class AssemblerX86Shared : public Assemb
             break;
           case Operand::MEM_SCALE:
             masm.cvtsi2ss_mr(src.disp(), src.base(), src.index(), src.scale(), dest.code());
             break;
           default:
             MOZ_ASSUME_UNREACHABLE("unexpected operand kind");
         }
     }
-    void cvtsi2ss(const Register &src, const FloatRegister &dest) {
+    void cvtsi2ss(Register src, const FloatRegister &dest) {
         JS_ASSERT(HasSSE2());
         masm.cvtsi2ss_rr(src.code(), dest.code());
     }
-    void cvtsi2sd(const Register &src, const FloatRegister &dest) {
+    void cvtsi2sd(Register src, const FloatRegister &dest) {
         JS_ASSERT(HasSSE2());
         masm.cvtsi2sd_rr(src.code(), dest.code());
     }
-    void movmskpd(const FloatRegister &src, const Register &dest) {
+    void movmskpd(const FloatRegister &src, Register dest) {
         JS_ASSERT(HasSSE2());
         masm.movmskpd_rr(src.code(), dest.code());
     }
-    void movmskps(const FloatRegister &src, const Register &dest) {
+    void movmskps(const FloatRegister &src, Register dest) {
         JS_ASSERT(HasSSE2());
         masm.movmskps_rr(src.code(), dest.code());
     }
     void ptest(const FloatRegister &lhs, const FloatRegister &rhs) {
         JS_ASSERT(HasSSE41());
         masm.ptest_rr(rhs.code(), lhs.code());
     }
     void ucomisd(const FloatRegister &lhs, const FloatRegister &rhs) {
@@ -1352,21 +1352,21 @@ class AssemblerX86Shared : public Assemb
     void ucomiss(const FloatRegister &lhs, const FloatRegister &rhs) {
         JS_ASSERT(HasSSE2());
         masm.ucomiss_rr(rhs.code(), lhs.code());
     }
     void pcmpeqw(const FloatRegister &lhs, const FloatRegister &rhs) {
         JS_ASSERT(HasSSE2());
         masm.pcmpeqw_rr(rhs.code(), lhs.code());
     }
-    void movd(const Register &src, const FloatRegister &dest) {
+    void movd(Register src, const FloatRegister &dest) {
         JS_ASSERT(HasSSE2());
         masm.movd_rr(src.code(), dest.code());
     }
-    void movd(const FloatRegister &src, const Register &dest) {
+    void movd(const FloatRegister &src, Register dest) {
         JS_ASSERT(HasSSE2());
         masm.movd_rr(src.code(), dest.code());
     }
     void addsd(const FloatRegister &src, const FloatRegister &dest) {
         JS_ASSERT(HasSSE2());
         masm.addsd_rr(src.code(), dest.code());
     }
     void addss(const FloatRegister &src, const FloatRegister &dest) {
--- a/js/src/jit/shared/CodeGenerator-shared-inl.h
+++ b/js/src/jit/shared/CodeGenerator-shared-inl.h
@@ -123,17 +123,17 @@ GetValueOutput(LInstruction *ins)
 #elif defined(JS_PUNBOX64)
     return ValueOperand(ToRegister(ins->getDef(0)));
 #else
 #error "Unknown"
 #endif
 }
 
 static inline ValueOperand
-GetTempValue(const Register &type, const Register &payload)
+GetTempValue(Register type, Register payload)
 {
 #if defined(JS_NUNBOX32)
     return ValueOperand(type, payload);
 #elif defined(JS_PUNBOX64)
     (void)type;
     return ValueOperand(payload);
 #else
 #error "Unknown"
--- a/js/src/jit/shared/CodeGenerator-shared.cpp
+++ b/js/src/jit/shared/CodeGenerator-shared.cpp
@@ -716,38 +716,38 @@ class OutOfLineTruncateSlow : public Out
     }
     bool needFloat32Conversion() const {
         return needFloat32Conversion_;
     }
 
 };
 
 OutOfLineCode *
-CodeGeneratorShared::oolTruncateDouble(const FloatRegister &src, const Register &dest)
+CodeGeneratorShared::oolTruncateDouble(const FloatRegister &src, Register dest)
 {
     OutOfLineTruncateSlow *ool = new(alloc()) OutOfLineTruncateSlow(src, dest);
     if (!addOutOfLineCode(ool))
         return nullptr;
     return ool;
 }
 
 bool
-CodeGeneratorShared::emitTruncateDouble(const FloatRegister &src, const Register &dest)
+CodeGeneratorShared::emitTruncateDouble(const FloatRegister &src, Register dest)
 {
     OutOfLineCode *ool = oolTruncateDouble(src, dest);
     if (!ool)
         return false;
 
     masm.branchTruncateDouble(src, dest, ool->entry());
     masm.bind(ool->rejoin());
     return true;
 }
 
 bool
-CodeGeneratorShared::emitTruncateFloat32(const FloatRegister &src, const Register &dest)
+CodeGeneratorShared::emitTruncateFloat32(const FloatRegister &src, Register dest)
 {
     OutOfLineTruncateSlow *ool = new(alloc()) OutOfLineTruncateSlow(src, dest, true);
     if (!addOutOfLineCode(ool))
         return false;
 
     masm.branchTruncateFloat32(src, dest, ool->entry());
     masm.bind(ool->rejoin());
     return true;
--- a/js/src/jit/shared/CodeGenerator-shared.h
+++ b/js/src/jit/shared/CodeGenerator-shared.h
@@ -296,19 +296,19 @@ class CodeGeneratorShared : public LInst
 
     // Ensure that there is enough room between the last OSI point and the
     // current instruction, such that:
     //  (1) Invalidation will not overwrite the current instruction, and
     //  (2) Overwriting the current instruction will not overwrite
     //      an invalidation marker.
     void ensureOsiSpace();
 
-    OutOfLineCode *oolTruncateDouble(const FloatRegister &src, const Register &dest);
-    bool emitTruncateDouble(const FloatRegister &src, const Register &dest);
-    bool emitTruncateFloat32(const FloatRegister &src, const Register &dest);
+    OutOfLineCode *oolTruncateDouble(const FloatRegister &src, Register dest);
+    bool emitTruncateDouble(const FloatRegister &src, Register dest);
+    bool emitTruncateFloat32(const FloatRegister &src, Register dest);
 
     void emitPreBarrier(Register base, const LAllocation *index, MIRType type);
     void emitPreBarrier(Address address, MIRType type);
 
     inline bool isNextBlock(LBlock *block) {
         return current->mir()->id() + 1 == block->mir()->id();
     }
 
@@ -370,17 +370,17 @@ class CodeGeneratorShared : public LInst
     template <typename T>
     void pushArg(const T &t) {
         masm.Push(t);
 #ifdef DEBUG
         pushedArgs_++;
 #endif
     }
 
-    void storeResultTo(const Register &reg) {
+    void storeResultTo(Register reg) {
         masm.storeCallResult(reg);
     }
 
     void storeFloatResultTo(const FloatRegister &reg) {
         masm.storeCallFloatResult(reg);
     }
 
     template <typename T>
@@ -622,17 +622,17 @@ struct StoreNothing
 };
 
 class StoreRegisterTo
 {
   private:
     Register out_;
 
   public:
-    StoreRegisterTo(const Register &out)
+    StoreRegisterTo(Register out)
       : out_(out)
     { }
 
     inline void generate(CodeGeneratorShared *codegen) const {
         codegen->storeResultTo(out_);
     }
     inline RegisterSet clobbered() const {
         RegisterSet set = RegisterSet();
--- a/js/src/jit/shared/CodeGenerator-x86-shared.cpp
+++ b/js/src/jit/shared/CodeGenerator-x86-shared.cpp
@@ -1482,18 +1482,17 @@ CodeGeneratorX86Shared::visitOutOfLineTa
         if (!masm.addCodeLabel(cl))
             return false;
     }
 
     return true;
 }
 
 bool
-CodeGeneratorX86Shared::emitTableSwitchDispatch(MTableSwitch *mir, const Register &index,
-                                                const Register &base)
+CodeGeneratorX86Shared::emitTableSwitchDispatch(MTableSwitch *mir, Register index, Register base)
 {
     Label *defaultcase = mir->getDefault()->lir()->label();
 
     // Lower value with low value
     if (mir->low() != 0)
         masm.subl(Imm32(mir->low()), index);
 
     // Jump to default case if input is out of range
--- a/js/src/jit/shared/CodeGenerator-x86-shared.h
+++ b/js/src/jit/shared/CodeGenerator-x86-shared.h
@@ -100,17 +100,17 @@ class CodeGeneratorX86Shared : public Co
     }
     void testUndefinedEmitBranch(Assembler::Condition cond, const ValueOperand &value,
                                  MBasicBlock *ifTrue, MBasicBlock *ifFalse)
     {
         cond = masm.testUndefined(cond, value);
         emitBranch(cond, ifTrue, ifFalse);
     }
 
-    bool emitTableSwitchDispatch(MTableSwitch *mir, const Register &index, const Register &base);
+    bool emitTableSwitchDispatch(MTableSwitch *mir, Register index, Register base);
 
   public:
     CodeGeneratorX86Shared(MIRGenerator *gen, LIRGraph *graph, MacroAssembler *masm);
 
   public:
     // Instruction visitors.
     virtual bool visitDouble(LDouble *ins);
     virtual bool visitFloat32(LFloat32 *ins);
--- a/js/src/jit/shared/MacroAssembler-x86-shared.cpp
+++ b/js/src/jit/shared/MacroAssembler-x86-shared.cpp
@@ -115,17 +115,17 @@ MacroAssembler::clampDoubleToUint8(Float
     }
 
     bind(&done);
 }
 
 // Builds an exit frame on the stack, with a return address to an internal
 // non-function. Returns offset to be passed to markSafepointAt().
 bool
-MacroAssemblerX86Shared::buildFakeExitFrame(const Register &scratch, uint32_t *offset)
+MacroAssemblerX86Shared::buildFakeExitFrame(Register scratch, uint32_t *offset)
 {
     mozilla::DebugOnly<uint32_t> initialDepth = framePushed();
 
     CodeLabel cl;
     mov(cl.dest(), scratch);
 
     uint32_t descriptor = MakeFrameDescriptor(framePushed(), JitFrame_IonJS);
     Push(Imm32(descriptor));
@@ -152,17 +152,17 @@ MacroAssemblerX86Shared::buildOOLFakeExi
     uint32_t descriptor = MakeFrameDescriptor(framePushed(), JitFrame_IonJS);
     Push(Imm32(descriptor));
     Push(ImmPtr(fakeReturnAddr));
     return true;
 }
 
 void
 MacroAssemblerX86Shared::branchNegativeZero(const FloatRegister &reg,
-                                            const Register &scratch,
+                                            Register scratch,
                                             Label *label)
 {
     // Determines whether the low double contained in the XMM register reg
     // is equal to -0.0.
 
 #if defined(JS_CODEGEN_X86)
     Label nonZero;
 
@@ -184,15 +184,15 @@ MacroAssemblerX86Shared::branchNegativeZ
     movq(reg, scratch);
     cmpq(scratch, Imm32(1));
     j(Overflow, label);
 #endif
 }
 
 void
 MacroAssemblerX86Shared::branchNegativeZeroFloat32(const FloatRegister &reg,
-                                                   const Register &scratch,
+                                                   Register scratch,
                                                    Label *label)
 {
     movd(reg, scratch);
     cmpl(scratch, Imm32(1));
     j(Overflow, label);
 }
--- a/js/src/jit/shared/MacroAssembler-x86-shared.h
+++ b/js/src/jit/shared/MacroAssembler-x86-shared.h
@@ -87,71 +87,71 @@ class MacroAssemblerX86Shared : public A
             j(Parity, label);
             return;
         }
 
         JS_ASSERT(!(cond & DoubleConditionBitSpecial));
         j(ConditionFromDoubleCondition(cond), label);
     }
 
-    void branchNegativeZero(const FloatRegister &reg, const Register &scratch, Label *label);
-    void branchNegativeZeroFloat32(const FloatRegister &reg, const Register &scratch, Label *label);
+    void branchNegativeZero(const FloatRegister &reg, Register scratch, Label *label);
+    void branchNegativeZeroFloat32(const FloatRegister &reg, Register scratch, Label *label);
 
-    void move32(const Imm32 &imm, const Register &dest) {
+    void move32(const Imm32 &imm, Register dest) {
         // Use the ImmWord version of mov to register, which has special
         // optimizations. Casting to uint32_t here ensures that the value
         // is zero-extended.
         mov(ImmWord(uint32_t(imm.value)), dest);
     }
     void move32(const Imm32 &imm, const Operand &dest) {
         movl(imm, dest);
     }
-    void move32(const Register &src, const Register &dest) {
+    void move32(Register src, Register dest) {
         movl(src, dest);
     }
-    void move32(const Register &src, const Operand &dest) {
+    void move32(Register src, const Operand &dest) {
         movl(src, dest);
     }
-    void and32(const Imm32 &imm, const Register &dest) {
+    void and32(const Imm32 &imm, Register dest) {
         andl(imm, dest);
     }
     void and32(const Imm32 &imm, const Address &dest) {
         andl(imm, Operand(dest));
     }
-    void or32(const Register &src, const Register &dest) {
+    void or32(Register src, Register dest) {
         orl(src, dest);
     }
-    void or32(const Imm32 &imm, const Register &dest) {
+    void or32(const Imm32 &imm, Register dest) {
         orl(imm, dest);
     }
     void or32(const Imm32 &imm, const Address &dest) {
         orl(imm, Operand(dest));
     }
-    void neg32(const Register &reg) {
+    void neg32(Register reg) {
         negl(reg);
     }
-    void test32(const Register &lhs, const Register &rhs) {
+    void test32(Register lhs, Register rhs) {
         testl(lhs, rhs);
     }
     void test32(const Address &addr, Imm32 imm) {
         testl(Operand(addr), imm);
     }
-    void test32(const Register &lhs, const Imm32 &rhs) {
+    void test32(Register lhs, const Imm32 &rhs) {
         testl(lhs, rhs);
     }
-    void cmp32(const Register &lhs, const Imm32 &rhs) {
+    void cmp32(Register lhs, const Imm32 &rhs) {
         cmpl(lhs, rhs);
     }
     void cmp32(Register a, Register b) {
         cmpl(a, b);
     }
     void cmp32(const Operand &lhs, const Imm32 &rhs) {
         cmpl(lhs, rhs);
     }
-    void cmp32(const Operand &lhs, const Register &rhs) {
+    void cmp32(const Operand &lhs, Register rhs) {
         cmpl(lhs, rhs);
     }
     void add32(Register src, Register dest) {
         addl(src, dest);
     }
     void add32(Imm32 imm, Register dest) {
         addl(imm, dest);
     }
@@ -190,59 +190,59 @@ class MacroAssemblerX86Shared : public A
         lock_incl(addr);
     }
     void dec32(const Operand &addr) {
         decl(addr);
     }
     void atomic_dec32(const Operand &addr) {
         lock_decl(addr);
     }
-    void atomic_cmpxchg32(const Register &src, const Operand &addr, const Register &dest) {
+    void atomic_cmpxchg32(Register src, const Operand &addr, Register dest) {
         // %eax must be explicitly provided for calling clarity.
         MOZ_ASSERT(dest.code() == JSC::X86Registers::eax);
         lock_cmpxchg32(src, addr);
     }
 
-    void branch16(Condition cond, const Register &lhs, const Register &rhs, Label *label) {
+    void branch16(Condition cond, Register lhs, Register rhs, Label *label) {
         cmpw(lhs, rhs);
         j(cond, label);
     }
-    void branch32(Condition cond, const Operand &lhs, const Register &rhs, Label *label) {
+    void branch32(Condition cond, const Operand &lhs, Register rhs, Label *label) {
         cmpl(lhs, rhs);
         j(cond, label);
     }
     void branch32(Condition cond, const Operand &lhs, Imm32 rhs, Label *label) {
         cmpl(lhs, rhs);
         j(cond, label);
     }
-    void branch32(Condition cond, const Address &lhs, const Register &rhs, Label *label) {
+    void branch32(Condition cond, const Address &lhs, Register rhs, Label *label) {
         cmpl(Operand(lhs), rhs);
         j(cond, label);
     }
     void branch32(Condition cond, const Address &lhs, Imm32 imm, Label *label) {
         cmpl(Operand(lhs), imm);
         j(cond, label);
     }
-    void branch32(Condition cond, const Register &lhs, Imm32 imm, Label *label) {
+    void branch32(Condition cond, Register lhs, Imm32 imm, Label *label) {
         cmpl(lhs, imm);
         j(cond, label);
     }
-    void branch32(Condition cond, const Register &lhs, const Register &rhs, Label *label) {
+    void branch32(Condition cond, Register lhs, Register rhs, Label *label) {
         cmpl(lhs, rhs);
         j(cond, label);
     }
-    void branchTest16(Condition cond, const Register &lhs, const Register &rhs, Label *label) {
+    void branchTest16(Condition cond, Register lhs, Register rhs, Label *label) {
         testw(lhs, rhs);
         j(cond, label);
     }
-    void branchTest32(Condition cond, const Register &lhs, const Register &rhs, Label *label) {
+    void branchTest32(Condition cond, Register lhs, Register rhs, Label *label) {
         testl(lhs, rhs);
         j(cond, label);
     }
-    void branchTest32(Condition cond, const Register &lhs, Imm32 imm, Label *label) {
+    void branchTest32(Condition cond, Register lhs, Imm32 imm, Label *label) {
         testl(lhs, imm);
         j(cond, label);
     }
     void branchTest32(Condition cond, const Address &address, Imm32 imm, Label *label) {
         testl(Operand(address), imm);
         j(cond, label);
     }
 
@@ -292,17 +292,17 @@ class MacroAssemblerX86Shared : public A
     }
     void jump(Register reg) {
         jmp(Operand(reg));
     }
     void jump(const Address &addr) {
         jmp(Operand(addr));
     }
 
-    void convertInt32ToDouble(const Register &src, const FloatRegister &dest) {
+    void convertInt32ToDouble(Register src, const FloatRegister &dest) {
         // cvtsi2sd and friends write only part of their output register, which
         // causes slowdowns on out-of-order processors. Explicitly break
         // dependencies with xorpd (and xorps elsewhere), which are handled
         // specially in modern CPUs, for this purpose. See sections 8.14, 9.8,
         // 10.8, 12.9, 13.16, 14.14, and 15.8 of Agner's Microarchitecture
         // document.
         zeroDouble(dest);
         cvtsi2sd(src, dest);
@@ -310,17 +310,17 @@ class MacroAssemblerX86Shared : public A
     void convertInt32ToDouble(const Address &src, FloatRegister dest) {
         convertInt32ToDouble(Operand(src), dest);
     }
     void convertInt32ToDouble(const Operand &src, FloatRegister dest) {
         // Clear the output register first to break dependencies; see above;
         zeroDouble(dest);
         cvtsi2sd(Operand(src), dest);
     }
-    void convertInt32ToFloat32(const Register &src, const FloatRegister &dest) {
+    void convertInt32ToFloat32(Register src, const FloatRegister &dest) {
         // Clear the output register first to break dependencies; see above;
         zeroFloat32(dest);
         cvtsi2ss(src, dest);
     }
     void convertInt32ToFloat32(const Address &src, FloatRegister dest) {
         convertInt32ToFloat32(Operand(src), dest);
     }
     void convertInt32ToFloat32(const Operand &src, FloatRegister dest) {
@@ -332,46 +332,46 @@ class MacroAssemblerX86Shared : public A
         zeroDouble(ScratchFloatReg);
         ucomisd(ScratchFloatReg, reg);
         return truthy ? NonZero : Zero;
     }
     void branchTestDoubleTruthy(bool truthy, const FloatRegister &reg, Label *label) {
         Condition cond = testDoubleTruthy(truthy, reg);
         j(cond, label);
     }
-    void load8ZeroExtend(const Address &src, const Register &dest) {
+    void load8ZeroExtend(const Address &src, Register dest) {
         movzbl(Operand(src), dest);
     }
-    void load8ZeroExtend(const BaseIndex &src, const Register &dest) {
+    void load8ZeroExtend(const BaseIndex &src, Register dest) {
         movzbl(Operand(src), dest);
     }
-    void load8SignExtend(const Address &src, const Register &dest) {
+    void load8SignExtend(const Address &src, Register dest) {
         movsbl(Operand(src), dest);
     }
-    void load8SignExtend(const BaseIndex &src, const Register &dest) {
+    void load8SignExtend(const BaseIndex &src, Register dest) {
         movsbl(Operand(src), dest);
     }
     template <typename S, typename T>
     void store8(const S &src, const T &dest) {
         movb(src, Operand(dest));
     }
-    void load16ZeroExtend(const Address &src, const Register &dest) {
+    void load16ZeroExtend(const Address &src, Register dest) {
         movzwl(Operand(src), dest);
     }
-    void load16ZeroExtend(const BaseIndex &src, const Register &dest) {
+    void load16ZeroExtend(const BaseIndex &src, Register dest) {
         movzwl(Operand(src), dest);
     }
     template <typename S, typename T>
     void store16(const S &src, const T &dest) {
         movw(src, Operand(dest));
     }
-    void load16SignExtend(const Address &src, const Register &dest) {
+    void load16SignExtend(const Address &src, Register dest) {
         movswl(Operand(src), dest);
     }
-    void load16SignExtend(const BaseIndex &src, const Register &dest) {
+    void load16SignExtend(const BaseIndex &src, Register dest) {
         movswl(Operand(src), dest);
     }
     void load32(const Address &address, Register dest) {
         movl(Operand(address), dest);
     }
     void load32(const BaseIndex &src, Register dest) {
         movl(Operand(src), dest);
     }
@@ -456,17 +456,17 @@ class MacroAssemblerX86Shared : public A
         divsd(src, dest);
     }
     void convertFloat32ToDouble(const FloatRegister &src, const FloatRegister &dest) {
         cvtss2sd(src, dest);
     }
     void convertDoubleToFloat32(const FloatRegister &src, const FloatRegister &dest) {
         cvtsd2ss(src, dest);
     }
-    void moveFloatAsDouble(const Register &src, FloatRegister dest) {
+    void moveFloatAsDouble(Register src, FloatRegister dest) {
         movd(src, dest);
         cvtss2sd(dest, dest);
     }
     void loadFloatAsDouble(const Address &src, FloatRegister dest) {
         movss(src, dest);
         cvtss2sd(dest, dest);
     }
     void loadFloatAsDouble(const BaseIndex &src, FloatRegister dest) {
@@ -596,17 +596,17 @@ class MacroAssemblerX86Shared : public A
     }
 
     void convertBoolToInt32(Register source, Register dest) {
         // Note that C++ bool is only 1 byte, so zero extend it to clear the
         // higher-order bits.
         movzbl(source, dest);
     }
 
-    void emitSet(Assembler::Condition cond, const Register &dest,
+    void emitSet(Assembler::Condition cond, Register dest,
                  Assembler::NaNCond ifNaN = Assembler::NaN_HandledByCond) {
         if (GeneralRegisterSet(Registers::SingleByteRegs).has(dest)) {
             // If the register we're defining is a single byte register,
             // take advantage of the setCC instruction
             setCC(cond, dest);
             movzbl(dest, dest);
 
             if (ifNaN != Assembler::NaN_HandledByCond) {
@@ -632,17 +632,17 @@ class MacroAssemblerX86Shared : public A
             bind(&ifFalse);
             mov(ImmWord(0), dest);
 
             bind(&end);
         }
     }
 
     template <typename T1, typename T2>
-    void cmp32Set(Assembler::Condition cond, T1 lhs, T2 rhs, const Register &dest)
+    void cmp32Set(Assembler::Condition cond, T1 lhs, T2 rhs, Register dest)
     {
         cmp32(lhs, rhs);
         emitSet(cond, dest);
     }
 
     // Emit a JMP that can be toggled to a CMP. See ToggleToJmp(), ToggleToCmp().
     CodeOffsetLabel toggledJump(Label *label) {
         CodeOffsetLabel offset(size());
@@ -652,38 +652,38 @@ class MacroAssemblerX86Shared : public A
 
     template <typename T>
     void computeEffectiveAddress(const T &address, Register dest) {
         lea(Operand(address), dest);
     }
 
     // Builds an exit frame on the stack, with a return address to an internal
     // non-function. Returns offset to be passed to markSafepointAt().
-    bool buildFakeExitFrame(const Register &scratch, uint32_t *offset);
+    bool buildFakeExitFrame(Register scratch, uint32_t *offset);
     void callWithExitFrame(JitCode *target);
 
-    void callIon(const Register &callee) {
+    void callIon(Register callee) {
         call(callee);
     }
 
     void appendCallSite(const CallSiteDesc &desc) {
         // Add an extra sizeof(void*) to include the return address that was
         // pushed by the call instruction (see CallSite::stackDepth).
         enoughMemory_ &= append(CallSite(desc, currentOffset(), framePushed_ + sizeof(void*)));
     }
 
     void call(const CallSiteDesc &desc, Label *label) {
         call(label);
         appendCallSite(desc);
     }
-    void call(const CallSiteDesc &desc, const Register &reg) {
+    void call(const CallSiteDesc &desc, Register reg) {
         call(reg);
         appendCallSite(desc);
     }
-    void callIonFromAsmJS(const Register &reg) {
+    void callIonFromAsmJS(Register reg) {
         call(CallSiteDesc::Exit(), reg);
     }
 
     void checkStackAlignment() {
         // Exists for ARM compatibility.
     }
 
     CodeOffsetLabel labelForPatch() {
--- a/js/src/jit/x64/Assembler-x64.h
+++ b/js/src/jit/x64/Assembler-x64.h
@@ -292,50 +292,50 @@ class Assembler : public AssemblerX86Sha
         return label;
     }
 
     void pop(const FloatRegister &src) {
         movsd(Address(StackPointer, 0), src);
         addq(Imm32(sizeof(double)), StackPointer);
     }
 
-    CodeOffsetLabel movWithPatch(const ImmWord &word, const Register &dest) {
+    CodeOffsetLabel movWithPatch(const ImmWord &word, Register dest) {
         masm.movq_i64r(word.value, dest.code());
         return masm.currentOffset();
     }
-    CodeOffsetLabel movWithPatch(const ImmPtr &imm, const Register &dest) {
+    CodeOffsetLabel movWithPatch(const ImmPtr &imm, Register dest) {
         return movWithPatch(ImmWord(uintptr_t(imm.value)), dest);
     }
 
     // Load an ImmWord value into a register. Note that this instruction will
     // attempt to optimize its immediate field size. When a full 64-bit
     // immediate is needed for a relocation, use movWithPatch.
-    void movq(ImmWord word, const Register &dest) {
+    void movq(ImmWord word, Register dest) {
         // Load a 64-bit immediate into a register. If the value falls into
         // certain ranges, we can use specialized instructions which have
         // smaller encodings.
         if (word.value <= UINT32_MAX) {
             // movl has a 32-bit unsigned (effectively) immediate field.
             masm.movl_i32r((uint32_t)word.value, dest.code());
         } else if ((intptr_t)word.value >= INT32_MIN && (intptr_t)word.value <= INT32_MAX) {
             // movq has a 32-bit signed immediate field.
             masm.movq_i32r((int32_t)(intptr_t)word.value, dest.code());
         } else {
             // Otherwise use movabs.
             masm.movq_i64r(word.value, dest.code());
         }
     }
-    void movq(ImmPtr imm, const Register &dest) {
+    void movq(ImmPtr imm, Register dest) {
         movq(ImmWord(uintptr_t(imm.value)), dest);
     }
-    void movq(ImmGCPtr ptr, const Register &dest) {
+    void movq(ImmGCPtr ptr, Register dest) {
         masm.movq_i64r(ptr.value, dest.code());
         writeDataRelocation(ptr);
     }
-    void movq(const Operand &src, const Register &dest) {
+    void movq(const Operand &src, Register dest) {
         switch (src.kind()) {
           case Operand::REG:
             masm.movq_rr(src.reg(), dest.code());
             break;
           case Operand::MEM_REG_DISP:
             masm.movq_mr(src.disp(), src.base(), dest.code());
             break;
           case Operand::MEM_SCALE:
@@ -343,17 +343,17 @@ class Assembler : public AssemblerX86Sha
             break;
           case Operand::MEM_ADDRESS32:
             masm.movq_mr(src.address(), dest.code());
             break;
           default:
             MOZ_ASSUME_UNREACHABLE("unexpected operand kind");
         }
     }
-    void movq(const Register &src, const Operand &dest) {
+    void movq(Register src, const Operand &dest) {
         switch (dest.kind()) {
           case Operand::REG:
             masm.movq_rr(src.code(), dest.reg());
             break;
           case Operand::MEM_REG_DISP:
             masm.movq_rm(src.code(), dest.disp(), dest.base());
             break;
           case Operand::MEM_SCALE:
@@ -379,38 +379,38 @@ class Assembler : public AssemblerX86Sha
             break;
           case Operand::MEM_ADDRESS32:
             masm.movq_i32m(imm32.value, dest.address());
             break;
           default:
             MOZ_ASSUME_UNREACHABLE("unexpected operand kind");
         }
     }
-    void movq(const Register &src, const FloatRegister &dest) {
+    void movq(Register src, const FloatRegister &dest) {
         masm.movq_rr(src.code(), dest.code());
     }
-    void movq(const FloatRegister &src, const Register &dest) {
+    void movq(const FloatRegister &src, Register dest) {
         masm.movq_rr(src.code(), dest.code());
     }
-    void movq(const Register &src, const Register &dest) {
+    void movq(Register src, Register dest) {
         masm.movq_rr(src.code(), dest.code());
     }
 
-    void xchgq(const Register &src, const Register &dest) {
+    void xchgq(Register src, Register dest) {
         masm.xchgq_rr(src.code(), dest.code());
     }
 
-    void andq(const Register &src, const Register &dest) {
+    void andq(Register src, Register dest) {
         masm.andq_rr(src.code(), dest.code());
     }
-    void andq(Imm32 imm, const Register &dest) {
+    void andq(Imm32 imm, Register dest) {
         masm.andq_ir(imm.value, dest.code());
     }
 
-    void addq(Imm32 imm, const Register &dest) {
+    void addq(Imm32 imm, Register dest) {
         masm.addq_ir(imm.value, dest.code());
     }
     void addq(Imm32 imm, const Operand &dest) {
         switch (dest.kind()) {
           case Operand::REG:
             masm.addq_ir(imm.value, dest.reg());
             break;
           case Operand::MEM_REG_DISP:
@@ -418,181 +418,181 @@ class Assembler : public AssemblerX86Sha
             break;
           case Operand::MEM_ADDRESS32:
             masm.addq_im(imm.value, dest.address());
             break;
           default:
             MOZ_ASSUME_UNREACHABLE("unexpected operand kind");
         }
     }
-    void addq(const Register &src, const Register &dest) {
+    void addq(Register src, Register dest) {
         masm.addq_rr(src.code(), dest.code());
     }
-    void addq(const Operand &src, const Register &dest) {
+    void addq(const Operand &src, Register dest) {
         switch (src.kind()) {
           case Operand::REG:
             masm.addq_rr(src.reg(), dest.code());
             break;
           case Operand::MEM_REG_DISP:
             masm.addq_mr(src.disp(), src.base(), dest.code());
             break;
           case Operand::MEM_ADDRESS32:
             masm.addq_mr(src.address(), dest.code());
             break;
           default:
             MOZ_ASSUME_UNREACHABLE("unexpected operand kind");
         }
     }
 
-    void subq(Imm32 imm, const Register &dest) {
+    void subq(Imm32 imm, Register dest) {
         masm.subq_ir(imm.value, dest.code());
     }
-    void subq(const Register &src, const Register &dest) {
+    void subq(Register src, Register dest) {
         masm.subq_rr(src.code(), dest.code());
     }
-    void subq(const Operand &src, const Register &dest) {
+    void subq(const Operand &src, Register dest) {
         switch (src.kind()) {
           case Operand::REG:
             masm.subq_rr(src.reg(), dest.code());
             break;
           case Operand::MEM_REG_DISP:
             masm.subq_mr(src.disp(), src.base(), dest.code());
             break;
           case Operand::MEM_ADDRESS32:
             masm.subq_mr(src.address(), dest.code());
             break;
           default:
             MOZ_ASSUME_UNREACHABLE("unexpected operand kind");
         }
     }
-    void subq(const Register &src, const Operand &dest) {
+    void subq(Register src, const Operand &dest) {
         switch (dest.kind()) {
           case Operand::REG:
             masm.subq_rr(src.code(), dest.reg());
             break;
           case Operand::MEM_REG_DISP:
             masm.subq_rm(src.code(), dest.disp(), dest.base());
             break;
           default:
             MOZ_ASSUME_UNREACHABLE("unexpected operand kind");
         }
     }
-    void shlq(Imm32 imm, const Register &dest) {
+    void shlq(Imm32 imm, Register dest) {
         masm.shlq_i8r(imm.value, dest.code());
     }
-    void shrq(Imm32 imm, const Register &dest) {
+    void shrq(Imm32 imm, Register dest) {
         masm.shrq_i8r(imm.value, dest.code());
     }
-    void sarq(Imm32 imm, const Register &dest) {
+    void sarq(Imm32 imm, Register dest) {
         masm.sarq_i8r(imm.value, dest.code());
     }
-    void orq(Imm32 imm, const Register &dest) {
+    void orq(Imm32 imm, Register dest) {
         masm.orq_ir(imm.value, dest.code());
     }
-    void orq(const Register &src, const Register &dest) {
+    void orq(Register src, Register dest) {
         masm.orq_rr(src.code(), dest.code());
     }
-    void orq(const Operand &src, const Register &dest) {
+    void orq(const Operand &src, Register dest) {
         switch (src.kind()) {
           case Operand::REG:
             masm.orq_rr(src.reg(), dest.code());
             break;
           case Operand::MEM_REG_DISP:
             masm.orq_mr(src.disp(), src.base(), dest.code());
             break;
           case Operand::MEM_ADDRESS32:
             masm.orq_mr(src.address(), dest.code());
             break;
           default:
             MOZ_ASSUME_UNREACHABLE("unexpected operand kind");
         }
     }
-    void xorq(const Register &src, const Register &dest) {
+    void xorq(Register src, Register dest) {
         masm.xorq_rr(src.code(), dest.code());
     }
-    void xorq(Imm32 imm, const Register &dest) {
+    void xorq(Imm32 imm, Register dest) {
         masm.xorq_ir(imm.value, dest.code());
     }
 
-    void mov(ImmWord word, const Register &dest) {
+    void mov(ImmWord word, Register dest) {
         // Use xor for setting registers to zero, as it is specially optimized
         // for this purpose on modern hardware. Note that it does clobber FLAGS
         // though. Use xorl instead of xorq since they are functionally
         // equivalent (32-bit instructions zero-extend their results to 64 bits)
         // and xorl has a smaller encoding.
         if (word.value == 0)
             xorl(dest, dest);
         else
             movq(word, dest);
     }
-    void mov(ImmPtr imm, const Register &dest) {
+    void mov(ImmPtr imm, Register dest) {
         movq(imm, dest);
     }
-    void mov(AsmJSImmPtr imm, const Register &dest) {
+    void mov(AsmJSImmPtr imm, Register dest) {
         masm.movq_i64r(-1, dest.code());
         enoughMemory_ &= append(AsmJSAbsoluteLink(masm.currentOffset(), imm.kind()));
     }
-    void mov(const Operand &src, const Register &dest) {
+    void mov(const Operand &src, Register dest) {
         movq(src, dest);
     }
-    void mov(const Register &src, const Operand &dest) {
+    void mov(Register src, const Operand &dest) {
         movq(src, dest);
     }
     void mov(const Imm32 &imm32, const Operand &dest) {
         movq(imm32, dest);
     }
-    void mov(const Register &src, const Register &dest) {
+    void mov(Register src, Register dest) {
         movq(src, dest);
     }
-    void mov(AbsoluteLabel *label, const Register &dest) {
+    void mov(AbsoluteLabel *label, Register dest) {
         JS_ASSERT(!label->bound());
         // Thread the patch list through the unpatched address word in the
         // instruction stream.
         masm.movq_i64r(label->prev(), dest.code());
         label->setPrev(masm.size());
     }
-    void xchg(const Register &src, const Register &dest) {
+    void xchg(Register src, Register dest) {
         xchgq(src, dest);
     }
-    void lea(const Operand &src, const Register &dest) {
+    void lea(const Operand &src, Register dest) {
         switch (src.kind()) {
           case Operand::MEM_REG_DISP:
             masm.leaq_mr(src.disp(), src.base(), dest.code());
             break;
           case Operand::MEM_SCALE:
             masm.leaq_mr(src.disp(), src.base(), src.index(), src.scale(), dest.code());
             break;
           default:
             MOZ_ASSUME_UNREACHABLE("unexepcted operand kind");
         }
     }
 
-    CodeOffsetLabel loadRipRelativeInt32(const Register &dest) {
+    CodeOffsetLabel loadRipRelativeInt32(Register dest) {
         return CodeOffsetLabel(masm.movl_ripr(dest.code()).offset());
     }
-    CodeOffsetLabel loadRipRelativeInt64(const Register &dest) {
+    CodeOffsetLabel loadRipRelativeInt64(Register dest) {
         return CodeOffsetLabel(masm.movq_ripr(dest.code()).offset());
     }
     CodeOffsetLabel loadRipRelativeDouble(const FloatRegister &dest) {
         return CodeOffsetLabel(masm.movsd_ripr(dest.code()).offset());
     }
-    CodeOffsetLabel storeRipRelativeInt32(const Register &dest) {
+    CodeOffsetLabel storeRipRelativeInt32(Register dest) {
         return CodeOffsetLabel(masm.movl_rrip(dest.code()).offset());
     }
     CodeOffsetLabel storeRipRelativeDouble(const FloatRegister &dest) {
         return CodeOffsetLabel(masm.movsd_rrip(dest.code()).offset());
     }
-    CodeOffsetLabel leaRipRelative(const Register &dest) {
+    CodeOffsetLabel leaRipRelative(Register dest) {
         return CodeOffsetLabel(masm.leaq_rip(dest.code()).offset());
     }
 
     // The below cmpq methods switch the lhs and rhs when it invokes the
     // macroassembler to conform with intel standard.  When calling this
     // function put the left operand on the left as you would expect.
-    void cmpq(const Operand &lhs, const Register &rhs) {
+    void cmpq(const Operand &lhs, Register rhs) {
         switch (lhs.kind()) {
           case Operand::REG:
             masm.cmpq_rr(rhs.code(), lhs.reg());
             break;
           case Operand::MEM_REG_DISP:
             masm.cmpq_rm(rhs.code(), lhs.disp(), lhs.base());
             break;
           case Operand::MEM_ADDRESS32:
@@ -612,39 +612,39 @@ class Assembler : public AssemblerX86Sha
             break;
           case Operand::MEM_ADDRESS32:
             masm.cmpq_im(rhs.value, lhs.address());
             break;
           default:
             MOZ_ASSUME_UNREACHABLE("unexpected operand kind");
         }
     }
-    void cmpq(const Register &lhs, const Operand &rhs) {
+    void cmpq(Register lhs, const Operand &rhs) {
         switch (rhs.kind()) {
           case Operand::REG:
             masm.cmpq_rr(rhs.reg(), lhs.code());
             break;
           case Operand::MEM_REG_DISP:
             masm.cmpq_mr(rhs.disp(), rhs.base(), lhs.code());
             break;
           default:
             MOZ_ASSUME_UNREACHABLE("unexpected operand kind");
         }
     }
-    void cmpq(const Register &lhs, const Register &rhs) {
+    void cmpq(Register lhs, Register rhs) {
         masm.cmpq_rr(rhs.code(), lhs.code());
     }
-    void cmpq(const Register &lhs, Imm32 rhs) {
+    void cmpq(Register lhs, Imm32 rhs) {
         masm.cmpq_ir(rhs.value, lhs.code());
     }
 
-    void testq(const Register &lhs, Imm32 rhs) {
+    void testq(Register lhs, Imm32 rhs) {
         masm.testq_i32r(rhs.value, lhs.code());
     }
-    void testq(const Register &lhs, const Register &rhs) {
+    void testq(Register lhs, Register rhs) {
         masm.testq_rr(rhs.code(), lhs.code());
     }
     void testq(const Operand &lhs, Imm32 rhs) {
         switch (lhs.kind()) {
           case Operand::REG:
             masm.testq_i32r(rhs.value, lhs.reg());
             break;
           case Operand::MEM_REG_DISP:
@@ -690,26 +690,26 @@ class Assembler : public AssemblerX86Sha
     static size_t ToggledCallSize() {
         // Size of a call instruction.
         return 5;
     }
 
     // Do not mask shared implementations.
     using AssemblerX86Shared::call;
 
-    void cvttsd2sq(const FloatRegister &src, const Register &dest) {
+    void cvttsd2sq(const FloatRegister &src, Register dest) {
         masm.cvttsd2sq_rr(src.code(), dest.code());
     }
-    void cvttss2sq(const FloatRegister &src, const Register &dest) {
+    void cvttss2sq(const FloatRegister &src, Register dest) {
         masm.cvttss2sq_rr(src.code(), dest.code());
     }
-    void cvtsq2sd(const Register &src, const FloatRegister &dest) {
+    void cvtsq2sd(Register src, const FloatRegister &dest) {
         masm.cvtsq2sd_rr(src.code(), dest.code());
     }
-    void cvtsq2ss(const Register &src, const FloatRegister &dest) {
+    void cvtsq2ss(Register src, const FloatRegister &dest) {
         masm.cvtsq2ss_rr(src.code(), dest.code());
     }
 };
 
 static inline void
 PatchJump(CodeLocationJump jump, CodeLocationLabel label)
 {
     if (JSC::X86Assembler::canRelinkJump(jump.raw(), label.raw())) {
--- a/js/src/jit/x64/CodeGenerator-x64.cpp
+++ b/js/src/jit/x64/CodeGenerator-x64.cpp
@@ -244,17 +244,17 @@ CodeGeneratorX64::visitLoadElementT(LLoa
 
     JS_ASSERT(!load->mir()->needsHoleCheck());
     return true;
 }
 
 
 void
 CodeGeneratorX64::storeElementTyped(const LAllocation *value, MIRType valueType, MIRType elementType,
-                                    const Register &elements, const LAllocation *index)
+                                    Register elements, const LAllocation *index)
 {
     Operand dest = createArrayElementOperand(elements, index);
     storeUnboxedValue(value, valueType, dest, elementType);
 }
 
 bool
 CodeGeneratorX64::visitImplicitThis(LImplicitThis *lir)
 {
--- a/js/src/jit/x64/CodeGenerator-x64.h
+++ b/js/src/jit/x64/CodeGenerator-x64.h
@@ -24,17 +24,17 @@ class CodeGeneratorX64 : public CodeGene
     ValueOperand ToTempValue(LInstruction *ins, size_t pos);
 
 
     void loadUnboxedValue(Operand source, MIRType type, const LDefinition *dest);
     void storeUnboxedValue(const LAllocation *value, MIRType valueType,
                            Operand dest, MIRType slotType);
 
     void storeElementTyped(const LAllocation *value, MIRType valueType, MIRType elementType,
-                           const Register &elements, const LAllocation *index);
+                           Register elements, const LAllocation *index);
 
   public:
     CodeGeneratorX64(MIRGenerator *gen, LIRGraph *graph, MacroAssembler *masm);
 
   public:
     bool visitValue(LValue *value);
     bool visitBox(LBox *box);
     bool visitUnbox(LUnbox *unbox);
--- a/js/src/jit/x64/MacroAssembler-x64.cpp
+++ b/js/src/jit/x64/MacroAssembler-x64.cpp
@@ -116,17 +116,17 @@ MacroAssemblerX64::setupABICall(uint32_t
 void
 MacroAssemblerX64::setupAlignedABICall(uint32_t args)
 {
     setupABICall(args);
     dynamicAlignment_ = false;
 }
 
 void
-MacroAssemblerX64::setupUnalignedABICall(uint32_t args, const Register &scratch)
+MacroAssemblerX64::setupUnalignedABICall(uint32_t args, Register scratch)
 {
     setupABICall(args);
     dynamicAlignment_ = true;
 
     movq(rsp, scratch);
     andq(Imm32(~(StackAlignment - 1)), rsp);
     push(scratch);
 }
@@ -172,17 +172,17 @@ MacroAssemblerX64::passABIArg(const Move
       default:
         MOZ_ASSUME_UNREACHABLE("Unexpected argument type");
     }
 
     enoughMemory_ = moveResolver_.addMove(from, to, type);
 }
 
 void
-MacroAssemblerX64::passABIArg(const Register &reg)
+MacroAssemblerX64::passABIArg(Register reg)
 {
     passABIArg(MoveOperand(reg), MoveOp::GENERAL);
 }
 
 void
 MacroAssemblerX64::passABIArg(const FloatRegister &reg, MoveOp::Type type)
 {
     passABIArg(MoveOperand(reg), type);
--- a/js/src/jit/x64/MacroAssembler-x64.h
+++ b/js/src/jit/x64/MacroAssembler-x64.h
@@ -227,17 +227,17 @@ class MacroAssemblerX64 : public MacroAs
     void pushValue(const Address &addr) {
         push(Operand(addr));
     }
     void Pop(const ValueOperand &val) {
         popValue(val);
         framePushed_ -= sizeof(Value);
     }
 
-    void moveValue(const Value &val, const Register &dest) {
+    void moveValue(const Value &val, Register dest) {
         jsval_layout jv = JSVAL_TO_IMPL(val);
         movWithPatch(ImmWord(jv.asBits), dest);
         writeDataRelocation(val);
     }
     void moveValue(const Value &src, const ValueOperand &dest) {
         moveValue(src, dest.valueReg());
     }
     void moveValue(const ValueOperand &src, const ValueOperand &dest) {
@@ -302,25 +302,25 @@ class MacroAssemblerX64 : public MacroAs
         return cond == Equal ? BelowOrEqual : Above;
     }
     Condition testGCThing(Condition cond, Register tag) {
         JS_ASSERT(cond == Equal || cond == NotEqual);
         cmpl(tag, Imm32(JSVAL_LOWER_INCL_TAG_OF_GCTHING_SET));
         return cond == Equal ? AboveOrEqual : Below;
     }
 
-    Condition testMagic(Condition cond, const Register &tag) {
+    Condition testMagic(Condition cond, Register tag) {
         JS_ASSERT(cond == Equal || cond == NotEqual);
         cmpl(tag, ImmTag(JSVAL_TAG_MAGIC));
         return cond;
     }
-    Condition testError(Condition cond, const Register &tag) {
+    Condition testError(Condition cond, Register tag) {
         return testMagic(cond, tag);
     }
-    Condition testPrimitive(Condition cond, const Register &tag) {
+    Condition testPrimitive(Condition cond, Register tag) {
         JS_ASSERT(cond == Equal || cond == NotEqual);
         cmpl(tag, ImmTag(JSVAL_UPPER_EXCL_TAG_OF_PRIMITIVE_SET));
         return cond == Equal ? Below : AboveOrEqual;
     }
 
     Condition testUndefined(Condition cond, const ValueOperand &src) {
         splitTag(src, ScratchReg);
         return testUndefined(cond, ScratchReg);
@@ -447,30 +447,30 @@ class MacroAssemblerX64 : public MacroAs
     }
 
     Condition isMagic(Condition cond, const ValueOperand &src, JSWhyMagic why) {
         uint64_t magic = MagicValue(why).asRawBits();
         cmpPtr(src.valueReg(), ImmWord(magic));
         return cond;
     }
 
-    void cmpPtr(const Register &lhs, const ImmWord rhs) {
+    void cmpPtr(Register lhs, const ImmWord rhs) {
         JS_ASSERT(lhs != ScratchReg);
         mov(rhs, ScratchReg);
         cmpq(lhs, ScratchReg);
     }
-    void cmpPtr(const Register &lhs, const ImmPtr rhs) {
+    void cmpPtr(Register lhs, const ImmPtr rhs) {
         cmpPtr(lhs, ImmWord(uintptr_t(rhs.value)));
     }
-    void cmpPtr(const Register &lhs, const ImmGCPtr rhs) {
+    void cmpPtr(Register lhs, const ImmGCPtr rhs) {
         JS_ASSERT(lhs != ScratchReg);
         movq(rhs, ScratchReg);
         cmpq(lhs, ScratchReg);
     }
-    void cmpPtr(const Register &lhs, const Imm32 rhs) {
+    void cmpPtr(Register lhs, const Imm32 rhs) {
         cmpq(lhs, rhs);
     }
     void cmpPtr(const Operand &lhs, const ImmGCPtr rhs) {
         movq(rhs, ScratchReg);
         cmpq(lhs, ScratchReg);
     }
     void cmpPtr(const Operand &lhs, const ImmWord rhs) {
         if ((intptr_t)rhs.value <= INT32_MAX && (intptr_t)rhs.value >= INT32_MIN) {
@@ -487,34 +487,34 @@ class MacroAssemblerX64 : public MacroAs
         cmpPtr(Operand(lhs), rhs);
     }
     void cmpPtr(const Address &lhs, const ImmWord rhs) {
         cmpPtr(Operand(lhs), rhs);
     }
     void cmpPtr(const Address &lhs, const ImmPtr rhs) {
         cmpPtr(lhs, ImmWord(uintptr_t(rhs.value)));
     }
-    void cmpPtr(const Operand &lhs, const Register &rhs) {
+    void cmpPtr(const Operand &lhs, Register rhs) {
         cmpq(lhs, rhs);
     }
     void cmpPtr(const Operand &lhs, const Imm32 rhs) {
         cmpq(lhs, rhs);
     }
-    void cmpPtr(const Address &lhs, const Register &rhs) {
+    void cmpPtr(const Address &lhs, Register rhs) {
         cmpPtr(Operand(lhs), rhs);
     }
-    void cmpPtr(const Register &lhs, const Register &rhs) {
+    void cmpPtr(Register lhs, Register rhs) {
         return cmpq(lhs, rhs);
     }
-    void testPtr(const Register &lhs, const Register &rhs) {
+    void testPtr(Register lhs, Register rhs) {
         testq(lhs, rhs);
     }
 
     template <typename T1, typename T2>
-    void cmpPtrSet(Assembler::Condition cond, T1 lhs, T2 rhs, const Register &dest)
+    void cmpPtrSet(Assembler::Condition cond, T1 lhs, T2 rhs, Register dest)
     {
         cmpPtr(lhs, rhs);
         emitSet(cond, dest);
     }
 
     /////////////////////////////////////////////////////////////////
     // Common interface.
     /////////////////////////////////////////////////////////////////
@@ -528,53 +528,53 @@ class MacroAssemblerX64 : public MacroAs
         if (amount)
             addq(Imm32(amount), StackPointer);
         framePushed_ -= amount;
     }
     void freeStack(Register amount) {
         addq(amount, StackPointer);
     }
 
-    void addPtr(const Register &src, const Register &dest) {
+    void addPtr(Register src, Register dest) {
         addq(src, dest);
     }
-    void addPtr(Imm32 imm, const Register &dest) {
+    void addPtr(Imm32 imm, Register dest) {
         addq(imm, dest);
     }
     void addPtr(Imm32 imm, const Address &dest) {
         addq(imm, Operand(dest));
     }
     void addPtr(Imm32 imm, const Operand &dest) {
         addq(imm, dest);
     }
-    void addPtr(ImmWord imm, const Register &dest) {
+    void addPtr(ImmWord imm, Register dest) {
         JS_ASSERT(dest != ScratchReg);
         if ((intptr_t)imm.value <= INT32_MAX && (intptr_t)imm.value >= INT32_MIN) {
             addq(Imm32((int32_t)imm.value), dest);
         } else {
             mov(imm, ScratchReg);
             addq(ScratchReg, dest);
         }
     }
-    void addPtr(ImmPtr imm, const Register &dest) {
+    void addPtr(ImmPtr imm, Register dest) {
         addPtr(ImmWord(uintptr_t(imm.value)), dest);
     }
-    void addPtr(const Address &src, const Register &dest) {
+    void addPtr(const Address &src, Register dest) {
         addq(Operand(src), dest);
     }
-    void subPtr(Imm32 imm, const Register &dest) {
+    void subPtr(Imm32 imm, Register dest) {
         subq(imm, dest);
     }
-    void subPtr(const Register &src, const Register &dest) {
+    void subPtr(Register src, Register dest) {
         subq(src, dest);
     }
-    void subPtr(const Address &addr, const Register &dest) {
+    void subPtr(const Address &addr, Register dest) {
         subq(Operand(addr), dest);
     }
-    void subPtr(const Register &src, const Address &dest) {
+    void subPtr(Register src, const Address &dest) {
         subq(src, Operand(dest));
     }
 
     void branch32(Condition cond, const AbsoluteAddress &lhs, Imm32 rhs, Label *label) {
         if (JSC::X86Assembler::isAddressImmediate(lhs.addr)) {
             branch32(cond, Operand(lhs), rhs, label);
         } else {
             mov(ImmPtr(lhs.addr), ScratchReg);
@@ -586,26 +586,26 @@ class MacroAssemblerX64 : public MacroAs
             branch32(cond, Operand(lhs), rhs, label);
         } else {
             mov(ImmPtr(lhs.addr), ScratchReg);
             branch32(cond, Address(ScratchReg, 0), rhs, label);
         }
     }
 
     // Specialization for AbsoluteAddress.
-    void branchPtr(Condition cond, const AbsoluteAddress &addr, const Register &ptr, Label *label) {
+    void branchPtr(Condition cond, const AbsoluteAddress &addr, Register ptr, Label *label) {
         JS_ASSERT(ptr != ScratchReg);
         if (JSC::X86Assembler::isAddressImmediate(addr.addr)) {
             branchPtr(cond, Operand(addr), ptr, label);
         } else {
             mov(ImmPtr(addr.addr), ScratchReg);
             branchPtr(cond, Operand(ScratchReg, 0x0), ptr, label);
         }
     }
-    void branchPtr(Condition cond, const AsmJSAbsoluteAddress &addr, const Register &ptr, Label *label) {
+    void branchPtr(Condition cond, const AsmJSAbsoluteAddress &addr, Register ptr, Label *label) {
         JS_ASSERT(ptr != ScratchReg);
         mov(AsmJSImmPtr(addr.kind()), ScratchReg);
         branchPtr(cond, Operand(ScratchReg, 0x0), ptr, label);
     }
 
     void branchPrivatePtr(Condition cond, Address lhs, ImmPtr ptr, Label *label) {
         branchPtr(cond, lhs, ImmWord(uintptr_t(ptr.value) >> 1), label);
     }
@@ -649,34 +649,34 @@ class MacroAssemblerX64 : public MacroAs
     void branchTestPtr(Condition cond, Register lhs, Imm32 imm, Label *label) {
         testq(lhs, imm);
         j(cond, label);
     }
     void branchTestPtr(Condition cond, const Address &lhs, Imm32 imm, Label *label) {
         testq(Operand(lhs), imm);
         j(cond, label);
     }
-    void decBranchPtr(Condition cond, const Register &lhs, Imm32 imm, Label *label) {
+    void decBranchPtr(Condition cond, Register lhs, Imm32 imm, Label *label) {
         subPtr(imm, lhs);
         j(cond, label);
     }
 
-    void movePtr(const Register &src, const Register &dest) {
+    void movePtr(Register src, Register dest) {
         movq(src, dest);
     }
-    void movePtr(const Register &src, const Operand &dest) {
+    void movePtr(Register src, const Operand &dest) {
         movq(src, dest);
     }
     void movePtr(ImmWord imm, Register dest) {
         mov(imm, dest);
     }
     void movePtr(ImmPtr imm, Register dest) {
         mov(imm, dest);
     }
-    void movePtr(AsmJSImmPtr imm, const Register &dest) {
+    void movePtr(AsmJSImmPtr imm, Register dest) {
         mov(imm, dest);
     }
     void movePtr(ImmGCPtr imm, Register dest) {
         movq(imm, dest);
     }
     void loadPtr(const AbsoluteAddress &address, Register dest) {
         if (JSC::X86Assembler::isAddressImmediate(address.addr)) {
             movq(Operand(address), dest);
@@ -722,25 +722,25 @@ class MacroAssemblerX64 : public MacroAs
         movq(ScratchReg, Operand(address));
     }
     void storePtr(Register src, const Address &address) {
         movq(src, Operand(address));
     }
     void storePtr(Register src, const Operand &dest) {
         movq(src, dest);
     }
-    void storePtr(const Register &src, const AbsoluteAddress &address) {
+    void storePtr(Register src, const AbsoluteAddress &address) {
         if (JSC::X86Assembler::isAddressImmediate(address.addr)) {
             movq(src, Operand(address));
         } else {
             mov(ImmPtr(address.addr), ScratchReg);
             storePtr(src, Address(ScratchReg, 0x0));
         }
     }
-    void store32(const Register &src, const AbsoluteAddress &address) {
+    void store32(Register src, const AbsoluteAddress &address) {
         if (JSC::X86Assembler::isAddressImmediate(address.addr)) {
             movl(src, Operand(address));
         } else {
             mov(ImmPtr(address.addr), ScratchReg);
             store32(src, Address(ScratchReg, 0x0));
         }
     }
     void rshiftPtr(Imm32 imm, Register dest) {
@@ -768,27 +768,27 @@ class MacroAssemblerX64 : public MacroAs
         andq(src, dest);
     }
 
     void splitTag(Register src, Register dest) {
         if (src != dest)
             movq(src, dest);
         shrq(Imm32(JSVAL_TAG_SHIFT), dest);
     }
-    void splitTag(const ValueOperand &operand, const Register &dest) {
+    void splitTag(const ValueOperand &operand, Register dest) {
         splitTag(operand.valueReg(), dest);
     }
-    void splitTag(const Operand &operand, const Register &dest) {
+    void splitTag(const Operand &operand, Register dest) {
         movq(operand, dest);
         shrq(Imm32(JSVAL_TAG_SHIFT), dest);
     }
-    void splitTag(const Address &operand, const Register &dest) {
+    void splitTag(const Address &operand, Register dest) {
         splitTag(Operand(operand), dest);
     }
-    void splitTag(const BaseIndex &operand, const Register &dest) {
+    void splitTag(const BaseIndex &operand, Register dest) {
         splitTag(Operand(operand), dest);
     }
 
     // Extracts the tag of a value and places it in ScratchReg.
     Register splitTagForTest(const ValueOperand &value) {
         splitTag(value, ScratchReg);
         return ScratchReg;
     }
@@ -992,57 +992,57 @@ class MacroAssemblerX64 : public MacroAs
     void testUndefinedSet(Condition cond, const ValueOperand &value, Register dest) {
         cond = testUndefined(cond, value);
         emitSet(cond, dest);
     }
 
     void boxDouble(const FloatRegister &src, const ValueOperand &dest) {
         movq(src, dest.valueReg());
     }
-    void boxNonDouble(JSValueType type, const Register &src, const ValueOperand &dest) {
+    void boxNonDouble(JSValueType type, Register src, const ValueOperand &dest) {
         JS_ASSERT(src != dest.valueReg());
         boxValue(type, src, dest.valueReg());
     }
 
     // Note that the |dest| register here may be ScratchReg, so we shouldn't
     // use it.
-    void unboxInt32(const ValueOperand &src, const Register &dest) {
+    void unboxInt32(const ValueOperand &src, Register dest) {
         movl(src.valueReg(), dest);
     }
-    void unboxInt32(const Operand &src, const Register &dest) {
+    void unboxInt32(const Operand &src, Register dest) {
         movl(src, dest);
     }
-    void unboxInt32(const Address &src, const Register &dest) {
+    void unboxInt32(const Address &src, Register dest) {
         unboxInt32(Operand(src), dest);
     }
     void unboxDouble(const Address &src, const FloatRegister &dest) {
         loadDouble(Operand(src), dest);
     }
 
-    void unboxArgObjMagic(const ValueOperand &src, const Register &dest) {
+    void unboxArgObjMagic(const ValueOperand &src, Register dest) {
         unboxArgObjMagic(Operand(src.valueReg()), dest);
     }
-    void unboxArgObjMagic(const Operand &src, const Register &dest) {
+    void unboxArgObjMagic(const Operand &src, Register dest) {
         mov(ImmWord(0), dest);
     }
-    void unboxArgObjMagic(const Address &src, const Register &dest) {
+    void unboxArgObjMagic(const Address &src, Register dest) {
         unboxArgObjMagic(Operand(src), dest);
     }
 
-    void unboxBoolean(const ValueOperand &src, const Register &dest) {
+    void unboxBoolean(const ValueOperand &src, Register dest) {
         movl(src.valueReg(), dest);
     }
-    void unboxBoolean(const Operand &src, const Register &dest) {
+    void unboxBoolean(const Operand &src, Register dest) {
         movl(src, dest);
     }
-    void unboxBoolean(const Address &src, const Register &dest) {
+    void unboxBoolean(const Address &src, Register dest) {
         unboxBoolean(Operand(src), dest);
     }
 
-    void unboxMagic(const ValueOperand &src, const Register &dest) {
+    void unboxMagic(const ValueOperand &src, Register dest) {
         movl(src.valueReg(), dest);
     }
 
     void unboxDouble(const ValueOperand &src, const FloatRegister &dest) {
         movq(src.valueReg(), dest);
     }
     void unboxPrivate(const ValueOperand &src, const Register dest) {
         movq(src.valueReg(), dest);
@@ -1050,41 +1050,41 @@ class MacroAssemblerX64 : public MacroAs
     }
 
     void notBoolean(const ValueOperand &val) {
         xorq(Imm32(1), val.valueReg());
     }
 
     // Unbox any non-double value into dest. Prefer unboxInt32 or unboxBoolean
     // instead if the source type is known.
-    void unboxNonDouble(const ValueOperand &src, const Register &dest) {
+    void unboxNonDouble(const ValueOperand &src, Register dest) {
         // In a non-trivial coupling, we're not permitted to use ScratchReg when
         // src and dest are different registers, because of how extractObject is
         // implemented.
         if (src.valueReg() == dest) {
             mov(ImmWord(JSVAL_PAYLOAD_MASK), ScratchReg);
             andq(ScratchReg, dest);
         } else {
             mov(ImmWord(JSVAL_PAYLOAD_MASK), dest);
             andq(src.valueReg(), dest);
         }
     }
-    void unboxNonDouble(const Operand &src, const Register &dest) {
+    void unboxNonDouble(const Operand &src, Register dest) {
         // Explicitly permits |dest| to be used in |src|.
         JS_ASSERT(dest != ScratchReg);
         mov(ImmWord(JSVAL_PAYLOAD_MASK), ScratchReg);
         movq(src, dest);
         andq(ScratchReg, dest);
     }
 
-    void unboxString(const ValueOperand &src, const Register &dest) { unboxNonDouble(src, dest); }
-    void unboxString(const Operand &src, const Register &dest) { unboxNonDouble(src, dest); }
+    void unboxString(const ValueOperand &src, Register dest) { unboxNonDouble(src, dest); }
+    void unboxString(const Operand &src, Register dest) { unboxNonDouble(src, dest); }
 
-    void unboxObject(const ValueOperand &src, const Register &dest) { unboxNonDouble(src, dest); }
-    void unboxObject(const Operand &src, const Register &dest) { unboxNonDouble(src, dest); }
+    void unboxObject(const ValueOperand &src, Register dest) { unboxNonDouble(src, dest); }
+    void unboxObject(const Operand &src, Register dest) { unboxNonDouble(src, dest); }
 
     // Extended unboxing API. If the payload is already in a register, returns
     // that register. Otherwise, provides a move to the given scratch register,
     // and returns that.
     Register extractObject(const Address &address, Register scratch) {
         JS_ASSERT(scratch != ScratchReg);
         loadPtr(address, ScratchReg);
         // We have a special coupling with unboxObject. As long as the registers
@@ -1146,28 +1146,28 @@ class MacroAssemblerX64 : public MacroAs
     }
     void int32ValueToFloat32(const ValueOperand &operand, const FloatRegister &dest) {
         convertInt32ToFloat32(operand.valueReg(), dest);
     }
 
     void loadConstantDouble(double d, const FloatRegister &dest);
     void loadConstantFloat32(float f, const FloatRegister &dest);
 
-    void branchTruncateDouble(const FloatRegister &src, const Register &dest, Label *fail) {
+    void branchTruncateDouble(const FloatRegister &src, Register dest, Label *fail) {
         cvttsd2sq(src, dest);
 
         // cvttsd2sq returns 0x8000000000000000 on failure. Test for it by
         // subtracting 1 and testing overflow (this avoids the need to
         // materialize that value in a register).
         cmpq(dest, Imm32(1));
         j(Assembler::Overflow, fail);
 
         movl(dest, dest); // Zero upper 32-bits.
     }
-    void branchTruncateFloat32(const FloatRegister &src, const Register &dest, Label *fail) {
+    void branchTruncateFloat32(const FloatRegister &src, Register dest, Label *fail) {
         cvttss2sq(src, dest);
 
         // Same trick as for Doubles
         cmpq(dest, Imm32(1));
         j(Assembler::Overflow, fail);
 
         movl(dest, dest); // Zero upper 32-bits.
     }
@@ -1211,25 +1211,25 @@ class MacroAssemblerX64 : public MacroAs
         if (dest.isFloat())
             loadInt32OrDouble(Operand(src), dest.fpu());
         else if (type == MIRType_Int32 || type == MIRType_Boolean)
             movl(Operand(src), dest.gpr());
         else
             unboxNonDouble(Operand(src), dest.gpr());
     }
 
-    void loadInstructionPointerAfterCall(const Register &dest) {
+    void loadInstructionPointerAfterCall(Register dest) {
         loadPtr(Address(StackPointer, 0x0), dest);
     }
 
-    void convertUInt32ToDouble(const Register &src, const FloatRegister &dest) {
+    void convertUInt32ToDouble(Register src, const FloatRegister &dest) {
         cvtsq2sd(src, dest);
     }
 
-    void convertUInt32ToFloat32(const Register &src, const FloatRegister &dest) {
+    void convertUInt32ToFloat32(Register src, const FloatRegister &dest) {
         cvtsq2ss(src, dest);
     }
 
     void inc64(AbsoluteAddress dest) {
         if (JSC::X86Assembler::isAddressImmediate(dest.addr)) {
             addPtr(Imm32(1), Operand(dest));
         } else {
             mov(ImmPtr(dest.addr), ScratchReg);
@@ -1265,26 +1265,26 @@ class MacroAssemblerX64 : public MacroAs
     // In order for alignment to work correctly, the MacroAssembler must have a
     // consistent view of the stack displacement. It is okay to call "push"
     // manually, however, if the stack alignment were to change, the macro
     // assembler should be notified before starting a call.
     void setupAlignedABICall(uint32_t args);
 
     // Sets up an ABI call for when the alignment is not known. This may need a
     // scratch register.
-    void setupUnalignedABICall(uint32_t args, const Register &scratch);
+    void setupUnalignedABICall(uint32_t args, Register scratch);
 
     // Arguments must be assigned to a C/C++ call in order. They are moved
     // in parallel immediately before performing the call. This process may
     // temporarily use more stack, in which case esp-relative addresses will be
     // automatically adjusted. It is extremely important that esp-relative
     // addresses are computed *after* setupABICall(). Furthermore, no
     // operations should be emitted while setting arguments.
     void passABIArg(const MoveOperand &from, MoveOp::Type type);
-    void passABIArg(const Register &reg);
+    void passABIArg(Register reg);
     void passABIArg(const FloatRegister &reg, MoveOp::Type type);
 
   private:
     void callWithABIPre(uint32_t *stackAdjust);
     void callWithABIPost(uint32_t stackAdjust, MoveOp::Type result);
 
   public:
     // Emits a call to a C/C++ function, resolving all argument moves.
@@ -1310,17 +1310,17 @@ class MacroAssemblerX64 : public MacroAs
         addPtr(Imm32(framePushed()), dynStack);
         makeFrameDescriptor(dynStack, JitFrame_IonJS);
         Push(dynStack);
         call(target);
     }
 
     // Save an exit frame to the thread data of the current thread, given a
     // register that holds a PerThreadData *.
-    void linkParallelExitFrame(const Register &pt) {
+    void linkParallelExitFrame(Register pt) {
         storePtr(StackPointer, Address(pt, offsetof(PerThreadData, jitTop)));
     }
 
     // See CodeGeneratorX64 calls to noteAsmJSGlobalAccess.
     void patchAsmJSGlobalAccess(CodeOffsetLabel patchAt, uint8_t *code, uint8_t *globalData,
                                 unsigned globalDataOffset)
     {
         uint8_t *nextInsn = code + patchAt.offset();
--- a/js/src/jit/x86/Assembler-x86.h
+++ b/js/src/jit/x86/Assembler-x86.h
@@ -205,25 +205,25 @@ class Assembler : public AssemblerX86Sha
         return masm.currentOffset();
     }
 
     void pop(const FloatRegister &src) {
         movsd(Address(StackPointer, 0), src);
         addl(Imm32(sizeof(double)), StackPointer);
     }
 
-    CodeOffsetLabel movWithPatch(const ImmWord &word, const Register &dest) {
+    CodeOffsetLabel movWithPatch(const ImmWord &word, Register dest) {
         movl(Imm32(word.value), dest);
         return masm.currentOffset();
     }
-    CodeOffsetLabel movWithPatch(const ImmPtr &imm, const Register &dest) {
+    CodeOffsetLabel movWithPatch(const ImmPtr &imm, Register dest) {
         return movWithPatch(ImmWord(uintptr_t(imm.value)), dest);
     }
 
-    void movl(const ImmGCPtr &ptr, const Register &dest) {
+    void movl(const ImmGCPtr &ptr, Register dest) {
         masm.movl_i32r(ptr.value, dest.code());
         writeDataRelocation(ptr);
     }
     void movl(const ImmGCPtr &ptr, const Operand &dest) {
         switch (dest.kind()) {
           case Operand::REG:
             masm.movl_i32r(ptr.value, dest.reg());
             writeDataRelocation(ptr);
@@ -257,39 +257,39 @@ class Assembler : public AssemblerX86Sha
     }
     void mov(ImmPtr imm, Register dest) {
         mov(ImmWord(uintptr_t(imm.value)), dest);
     }
     void mov(AsmJSImmPtr imm, Register dest) {
         masm.movl_i32r(-1, dest.code());
         enoughMemory_ &= append(AsmJSAbsoluteLink(masm.currentOffset(), imm.kind()));
     }
-    void mov(const Operand &src, const Register &dest) {
+    void mov(const Operand &src, Register dest) {
         movl(src, dest);
     }
-    void mov(const Register &src, const Operand &dest) {
+    void mov(Register src, const Operand &dest) {
         movl(src, dest);
     }
     void mov(Imm32 imm, const Operand &dest) {
         movl(imm, dest);
     }
-    void mov(AbsoluteLabel *label, const Register &dest) {
+    void mov(AbsoluteLabel *label, Register dest) {
         JS_ASSERT(!label->bound());
         // Thread the patch list through the unpatched address word in the
         // instruction stream.
         masm.movl_i32r(label->prev(), dest.code());
         label->setPrev(masm.size());
     }
-    void mov(const Register &src, const Register &dest) {
+    void mov(Register src, Register dest) {
         movl(src, dest);
     }
-    void xchg(const Register &src, const Register &dest) {
+    void xchg(Register src, Register dest) {
         xchgl(src, dest);
     }
-    void lea(const Operand &src, const Register &dest) {
+    void lea(const Operand &src, Register dest) {
         return leal(src, dest);
     }
 
     void fld32(const Operand &dest) {
         switch (dest.kind()) {
           case Operand::MEM_REG_DISP:
             masm.fld32_m(dest.disp(), dest.base());
             break;
@@ -313,17 +313,17 @@ class Assembler : public AssemblerX86Sha
     }
     void cmpl(const Register src, ImmPtr imm) {
         cmpl(src, ImmWord(uintptr_t(imm.value)));
     }
     void cmpl(const Register src, ImmGCPtr ptr) {
         masm.cmpl_ir(ptr.value, src.code());
         writeDataRelocation(ptr);
     }
-    void cmpl(const Register &lhs, const Register &rhs) {
+    void cmpl(Register lhs, Register rhs) {
         masm.cmpl_rr(rhs.code(), lhs.code());
     }
     void cmpl(const Operand &op, ImmGCPtr imm) {
         switch (op.kind()) {
           case Operand::REG:
             masm.cmpl_ir_force32(imm.value, op.reg());
             writeDataRelocation(imm);
             break;
@@ -334,21 +334,21 @@ class Assembler : public AssemblerX86Sha
           case Operand::MEM_ADDRESS32:
             masm.cmpl_im(imm.value, op.address());
             writeDataRelocation(imm);
             break;
           default:
             MOZ_ASSUME_UNREACHABLE("unexpected operand kind");
         }
     }
-    void cmpl(const AsmJSAbsoluteAddress &lhs, const Register &rhs) {
+    void cmpl(const AsmJSAbsoluteAddress &lhs, Register rhs) {
         masm.cmpl_rm_force32(rhs.code(), (void*)-1);
         enoughMemory_ &= append(AsmJSAbsoluteLink(masm.currentOffset(), lhs.kind()));
     }
-    CodeOffsetLabel cmplWithPatch(const Register &lhs, Imm32 rhs) {
+    CodeOffsetLabel cmplWithPatch(Register lhs, Imm32 rhs) {
         masm.cmpl_ir_force32(rhs.value, lhs.code());
         return masm.currentOffset();
     }
 
     void jmp(ImmPtr target, Relocation::Kind reloc = Relocation::HARDCODED) {
         JmpSrc src = masm.jmp();
         addPendingJump(src, target, reloc);
     }
--- a/js/src/jit/x86/CodeGenerator-x86.cpp
+++ b/js/src/jit/x86/CodeGenerator-x86.cpp
@@ -216,17 +216,17 @@ CodeGeneratorX86::visitLoadElementT(LLoa
         masm.movl(masm.ToPayload(source), ToRegister(load->output()));
     }
 
     return true;
 }
 
 void
 CodeGeneratorX86::storeElementTyped(const LAllocation *value, MIRType valueType, MIRType elementType,
-                                    const Register &elements, const LAllocation *index)
+                                    Register elements, const LAllocation *index)
 {
     Operand dest = createArrayElementOperand(elements, index);
 
     if (valueType == MIRType_Double) {
         masm.storeDouble(ToFloatRegister(value), dest);
         return;
     }
 
--- a/js/src/jit/x86/CodeGenerator-x86.h
+++ b/js/src/jit/x86/CodeGenerator-x86.h
@@ -37,17 +37,17 @@ class CodeGeneratorX86 : public CodeGene
                                        const LDefinition *out);
     template<typename T>
     bool storeAndNoteViewTypeElement(ArrayBufferView::ViewType vt, const LAllocation *value,
                               const T &dstAddr);
     template<typename T>
     void storeViewTypeElement(ArrayBufferView::ViewType vt, const LAllocation *value,
                                         const T &dstAddr);
     void storeElementTyped(const LAllocation *value, MIRType valueType, MIRType elementType,
-                           const Register &elements, const LAllocation *index);
+                           Register elements, const LAllocation *index);
 
   public:
     CodeGeneratorX86(MIRGenerator *gen, LIRGraph *graph, MacroAssembler *masm);
 
   public:
     bool visitBox(LBox *box);
     bool visitBoxFloatingPoint(LBoxFloatingPoint *box);
     bool visitUnbox(LUnbox *unbox);
--- a/js/src/jit/x86/MacroAssembler-x86.cpp
+++ b/js/src/jit/x86/MacroAssembler-x86.cpp
@@ -148,17 +148,17 @@ MacroAssemblerX86::setupABICall(uint32_t
 void
 MacroAssemblerX86::setupAlignedABICall(uint32_t args)
 {
     setupABICall(args);
     dynamicAlignment_ = false;
 }
 
 void
-MacroAssemblerX86::setupUnalignedABICall(uint32_t args, const Register &scratch)
+MacroAssemblerX86::setupUnalignedABICall(uint32_t args, Register scratch)
 {
     setupABICall(args);
     dynamicAlignment_ = true;
 
     movl(esp, scratch);
     andl(Imm32(~(StackAlignment - 1)), esp);
     push(scratch);
 }
@@ -174,17 +174,17 @@ MacroAssemblerX86::passABIArg(const Move
       case MoveOp::INT32:   stackForCall_ += sizeof(int32_t); break;
       case MoveOp::GENERAL: stackForCall_ += sizeof(intptr_t); break;
       default: MOZ_ASSUME_UNREACHABLE("Unexpected argument type");
     }
     enoughMemory_ &= moveResolver_.addMove(from, to, type);
 }
 
 void
-MacroAssemblerX86::passABIArg(const Register &reg)
+MacroAssemblerX86::passABIArg(Register reg)
 {
     passABIArg(MoveOperand(reg), MoveOp::GENERAL);
 }
 
 void
 MacroAssemblerX86::passABIArg(const FloatRegister &reg, MoveOp::Type type)
 {
     passABIArg(MoveOperand(reg), type);
--- a/js/src/jit/x86/MacroAssembler-x86.h
+++ b/js/src/jit/x86/MacroAssembler-x86.h
@@ -247,100 +247,100 @@ class MacroAssemblerX86 : public MacroAs
     }
     void storePayload(Register src, Operand dest) {
         movl(src, ToPayload(dest));
     }
     void storeTypeTag(ImmTag tag, Operand dest) {
         movl(tag, ToType(dest));
     }
 
-    void movePtr(const Register &src, const Register &dest) {
+    void movePtr(Register src, Register dest) {
         movl(src, dest);
     }
-    void movePtr(const Register &src, const Operand &dest) {
+    void movePtr(Register src, const Operand &dest) {
         movl(src, dest);
     }
 
     // Returns the register containing the type tag.
     Register splitTagForTest(const ValueOperand &value) {
         return value.typeReg();
     }
 
-    Condition testUndefined(Condition cond, const Register &tag) {
+    Condition testUndefined(Condition cond, Register tag) {
         JS_ASSERT(cond == Equal || cond == NotEqual);
         cmpl(tag, ImmTag(JSVAL_TAG_UNDEFINED));
         return cond;
     }
-    Condition testBoolean(Condition cond, const Register &tag) {
+    Condition testBoolean(Condition cond, Register tag) {
         JS_ASSERT(cond == Equal || cond == NotEqual);
         cmpl(tag, ImmTag(JSVAL_TAG_BOOLEAN));
         return cond;
     }
-    Condition testInt32(Condition cond, const Register &tag) {
+    Condition testInt32(Condition cond, Register tag) {
         JS_ASSERT(cond == Equal || cond == NotEqual);
         cmpl(tag, ImmTag(JSVAL_TAG_INT32));
         return cond;
     }
-    Condition testDouble(Condition cond, const Register &tag) {
+    Condition testDouble(Condition cond, Register tag) {
         JS_ASSERT(cond == Assembler::Equal || cond == Assembler::NotEqual);
         Condition actual = (cond == Equal) ? Below : AboveOrEqual;
         cmpl(tag, ImmTag(JSVAL_TAG_CLEAR));
         return actual;
     }
-    Condition testNull(Condition cond, const Register &tag) {
+    Condition testNull(Condition cond, Register tag) {
         JS_ASSERT(cond == Equal || cond == NotEqual);
         cmpl(tag, ImmTag(JSVAL_TAG_NULL));
         return cond;
     }
-    Condition testString(Condition cond, const Register &tag) {
+    Condition testString(Condition cond, Register tag) {
         JS_ASSERT(cond == Equal || cond == NotEqual);
         cmpl(tag, ImmTag(JSVAL_TAG_STRING));
         return cond;
     }
-    Condition testObject(Condition cond, const Register &tag) {
+    Condition testObject(Condition cond, Register tag) {
         JS_ASSERT(cond == Equal || cond == NotEqual);
         cmpl(tag, ImmTag(JSVAL_TAG_OBJECT));
         return cond;
     }
-    Condition testNumber(Condition cond, const Register &tag) {
+    Condition testNumber(Condition cond, Register tag) {
         JS_ASSERT(cond == Equal || cond == NotEqual);
         cmpl(tag, ImmTag(JSVAL_UPPER_INCL_TAG_OF_NUMBER_SET));
         return cond == Equal ? BelowOrEqual : Above;
     }
-    Condition testGCThing(Condition cond, const Register &tag) {
+    Condition testGCThing(Condition cond, Register tag) {
         JS_ASSERT(cond == Equal || cond == NotEqual);
         cmpl(tag, ImmTag(JSVAL_LOWER_INCL_TAG_OF_GCTHING_SET));
         return cond == Equal ? AboveOrEqual : Below;
     }
     Condition testGCThing(Condition cond, const Address &address) {
         JS_ASSERT(cond == Equal || cond == NotEqual);
         cmpl(tagOf(address), ImmTag(JSVAL_LOWER_INCL_TAG_OF_GCTHING_SET));
         return cond == Equal ? AboveOrEqual : Below;
     }
     Condition testMagic(Condition cond, const Address &address) {
         JS_ASSERT(cond == Equal || cond == NotEqual);
         cmpl(tagOf(address), ImmTag(JSVAL_TAG_MAGIC));
         return cond;
     }
-    Condition testMagic(Condition cond, const Register &tag) {
+    Condition testMagic(Condition cond, Register tag) {
         JS_ASSERT(cond == Equal || cond == NotEqual);
         cmpl(tag, ImmTag(JSVAL_TAG_MAGIC));
         return cond;
     }
     Condition testMagic(Condition cond, const Operand &operand) {
         JS_ASSERT(cond == Equal || cond == NotEqual);
         cmpl(ToType(operand), ImmTag(JSVAL_TAG_MAGIC));
         return cond;
     }
-    Condition testPrimitive(Condition cond, const Register &tag) {
+    Condition testPrimitive(Condition cond, Register tag) {
         JS_ASSERT(cond == Equal || cond == NotEqual);
         cmpl(tag, ImmTag(JSVAL_UPPER_EXCL_TAG_OF_PRIMITIVE_SET));
         return cond == Equal ? Below : AboveOrEqual;
     }
-    Condition testError(Condition cond, const Register &tag) {
+    Condition testError(Condition cond, Register tag) {
         return testMagic(cond, tag);
     }
     Condition testInt32(Condition cond, const Operand &operand) {
         JS_ASSERT(cond == Equal || cond == NotEqual);
         cmpl(ToType(operand), ImmTag(JSVAL_TAG_INT32));
         return cond;
     }
     Condition testInt32(Condition cond, const Address &address) {
@@ -519,17 +519,17 @@ class MacroAssemblerX86 : public MacroAs
     void cmpPtr(Register lhs, Register rhs) {
         cmpl(lhs, rhs);
     }
     void testPtr(Register lhs, Register rhs) {
         testl(lhs, rhs);
     }
 
     template <typename T1, typename T2>
-    void cmpPtrSet(Assembler::Condition cond, T1 lhs, T2 rhs, const Register &dest)
+    void cmpPtrSet(Assembler::Condition cond, T1 lhs, T2 rhs, Register dest)
     {
         cmpPtr(lhs, rhs);
         emitSet(cond, dest);
     }
 
     /////////////////////////////////////////////////////////////////
     // Common interface.
     /////////////////////////////////////////////////////////////////
@@ -543,47 +543,47 @@ class MacroAssemblerX86 : public MacroAs
         if (amount)
             addl(Imm32(amount), StackPointer);
         framePushed_ -= amount;
     }
     void freeStack(Register amount) {
         addl(amount, StackPointer);
     }
 
-    void addPtr(const Register &src, const Register &dest) {
+    void addPtr(Register src, Register dest) {
         addl(src, dest);
     }
-    void addPtr(Imm32 imm, const Register &dest) {
+    void addPtr(Imm32 imm, Register dest) {
         addl(imm, dest);
     }
-    void addPtr(ImmWord imm, const Register &dest) {
+    void addPtr(ImmWord imm, Register dest) {
         addl(Imm32(imm.value), dest);
     }
-    void addPtr(ImmPtr imm, const Register &dest) {
+    void addPtr(ImmPtr imm, Register dest) {
         addPtr(ImmWord(uintptr_t(imm.value)), dest);
     }
     void addPtr(Imm32 imm, const Address &dest) {
         addl(imm, Operand(dest));
     }
     void addPtr(Imm32 imm, const Operand &dest) {
         addl(imm, dest);
     }
-    void addPtr(const Address &src, const Register &dest) {
+    void addPtr(const Address &src, Register dest) {
         addl(Operand(src), dest);
     }
-    void subPtr(Imm32 imm, const Register &dest) {
+    void subPtr(Imm32 imm, Register dest) {
         subl(imm, dest);
     }
-    void subPtr(const Register &src, const Register &dest) {
+    void subPtr(Register src, Register dest) {
         subl(src, dest);
     }
-    void subPtr(const Address &addr, const Register &dest) {
+    void subPtr(const Address &addr, Register dest) {
         subl(Operand(addr), dest);
     }
-    void subPtr(const Register &src, const Address &dest) {
+    void subPtr(Register src, const Address &dest) {
         subl(src, Operand(dest));
     }
 
     void branch32(Condition cond, const AbsoluteAddress &lhs, Imm32 rhs, Label *label) {
         cmpl(Operand(lhs), rhs);
         j(cond, label);
     }
     void branch32(Condition cond, const AbsoluteAddress &lhs, Register rhs, Label *label) {
@@ -647,17 +647,17 @@ class MacroAssemblerX86 : public MacroAs
     void branchTestPtr(Condition cond, Register lhs, Imm32 imm, Label *label) {
         testl(lhs, imm);
         j(cond, label);
     }
     void branchTestPtr(Condition cond, const Address &lhs, Imm32 imm, Label *label) {
         testl(Operand(lhs), imm);
         j(cond, label);
     }
-    void decBranchPtr(Condition cond, const Register &lhs, Imm32 imm, Label *label) {
+    void decBranchPtr(Condition cond, Register lhs, Imm32 imm, Label *label) {
         subPtr(imm, lhs);
         j(cond, label);
     }
 
     void movePtr(ImmWord imm, Register dest) {
         movl(Imm32(imm.value), dest);
     }
     void movePtr(ImmPtr imm, Register dest) {
@@ -704,17 +704,17 @@ class MacroAssemblerX86 : public MacroAs
     }
     void storePtr(Register src, const AbsoluteAddress &address) {
         movl(src, Operand(address));
     }
     void store32(Register src, const AbsoluteAddress &address) {
         movl(src, Operand(address));
     }
 
-    void setStackArg(const Register &reg, uint32_t arg) {
+    void setStackArg(Register reg, uint32_t arg) {
         movl(reg, Operand(esp, arg * sizeof(intptr_t)));
     }
 
     // Type testing instructions can take a tag in a register or a
     // ValueOperand.
     template <typename T>
     void branchTestUndefined(Condition cond, const T &t, Label *label) {
         cond = testUndefined(cond, t);
@@ -790,71 +790,71 @@ class MacroAssemblerX86 : public MacroAs
     }
 
     // Note: this function clobbers the source register.
     void boxDouble(const FloatRegister &src, const ValueOperand &dest) {
         movd(src, dest.payloadReg());
         psrldq(Imm32(4), src);
         movd(src, dest.typeReg());
     }
-    void boxNonDouble(JSValueType type, const Register &src, const ValueOperand &dest) {
+    void boxNonDouble(JSValueType type, Register src, const ValueOperand &dest) {
         if (src != dest.payloadReg())
             movl(src, dest.payloadReg());
         movl(ImmType(type), dest.typeReg());
     }
-    void unboxInt32(const ValueOperand &src, const Register &dest) {
+    void unboxInt32(const ValueOperand &src, Register dest) {
         movl(src.payloadReg(), dest);
     }
-    void unboxInt32(const Address &src, const Register &dest) {
+    void unboxInt32(const Address &src, Register dest) {
         movl(payloadOf(src), dest);
     }
     void unboxDouble(const Address &src, const FloatRegister &dest) {
         loadDouble(Operand(src), dest);
     }
-    void unboxBoolean(const ValueOperand &src, const Register &dest) {
+    void unboxBoolean(const ValueOperand &src, Register dest) {
         movl(src.payloadReg(), dest);
     }
-    void unboxBoolean(const Address &src, const Register &dest) {
+    void unboxBoolean(const Address &src, Register dest) {
         movl(payloadOf(src), dest);
     }
-    void unboxObject(const ValueOperand &src, const Register &dest) {
+    void unboxObject(const ValueOperand &src, Register dest) {
         if (src.payloadReg() != dest)
             movl(src.payloadReg(), dest);
     }
     void unboxDouble(const ValueOperand &src, const FloatRegister &dest) {
         JS_ASSERT(dest != ScratchFloatReg);
         if (Assembler::HasSSE41()) {
             movd(src.payloadReg(), dest);
             pinsrd(src.typeReg(), dest);
         } else {
             movd(src.payloadReg(), dest);
             movd(src.typeReg(), ScratchFloatReg);
             unpcklps(ScratchFloatReg, dest);
         }
     }
     void unboxDouble(const Operand &payload, const Operand &type,
-                     const Register &scratch, const FloatRegister &dest) {
+                     Register scratch, const FloatRegister &dest) {
         JS_ASSERT(dest != ScratchFloatReg);
         if (Assembler::HasSSE41()) {
             movl(payload, scratch);
             movd(scratch, dest);
             movl(type, scratch);
             pinsrd(scratch, dest);
         } else {
             movl(payload, scratch);
             movd(scratch, dest);
             movl(type, scratch);
             movd(scratch, ScratchFloatReg);
             unpcklps(ScratchFloatReg, dest);
         }
     }
-    void unboxString(const ValueOperand &src, const Register &dest) {
+    void unboxString(const ValueOperand &src, Register dest) {
         movl(src.payloadReg(), dest);
     }
-    void unboxString(const Address &src, const Register &dest) {
+    void unboxString(const Address &src, Register dest) {
         movl(payloadOf(src), dest);
     }
     void unboxValue(const ValueOperand &src, AnyRegister dest) {
         if (dest.isFloat()) {
             Label notInt32, end;
             branchTestInt32(Assembler::NotEqual, src, &notInt32);
             convertInt32ToDouble(src.payloadReg(), dest.fpu());
             jump(&end);
@@ -912,26 +912,26 @@ class MacroAssemblerX86 : public MacroAs
         convertInt32ToFloat32(operand.payloadReg(), dest);
     }
 
     void loadConstantDouble(double d, const FloatRegister &dest);
     void addConstantDouble(double d, const FloatRegister &dest);
     void loadConstantFloat32(float f, const FloatRegister &dest);
     void addConstantFloat32(float f, const FloatRegister &dest);
 
-    void branchTruncateDouble(const FloatRegister &src, const Register &dest, Label *fail) {
+    void branchTruncateDouble(const FloatRegister &src, Register dest, Label *fail) {
         cvttsd2si(src, dest);
 
         // cvttsd2si returns 0x80000000 on failure. Test for it by
         // subtracting 1 and testing overflow (this permits the use of a
         // smaller immediate field).
         cmpl(dest, Imm32(1));
         j(Assembler::Overflow, fail);
     }
-    void branchTruncateFloat32(const FloatRegister &src, const Register &dest, Label *fail) {
+    void branchTruncateFloat32(const FloatRegister &src, Register dest, Label *fail) {
         cvttss2si(src, dest);
 
         // cvttss2si returns 0x80000000 on failure. Test for it by
         // subtracting 1 and testing overflow (this permits the use of a
         // smaller immediate field).
         cmpl(dest, Imm32(1));
         j(Assembler::Overflow, fail);
     }
@@ -999,35 +999,35 @@ class MacroAssemblerX86 : public MacroAs
     }
     void andPtr(Imm32 imm, Register dest) {
         andl(imm, dest);
     }
     void andPtr(Register src, Register dest) {
         andl(src, dest);
     }
 
-    void loadInstructionPointerAfterCall(const Register &dest) {
+    void loadInstructionPointerAfterCall(Register dest) {
         movl(Operand(StackPointer, 0x0), dest);
     }
 
     // Note: this function clobbers the source register.
-    void convertUInt32ToDouble(const Register &src, const FloatRegister &dest) {
+    void convertUInt32ToDouble(Register src, const FloatRegister &dest) {
         // src is [0, 2^32-1]
         subl(Imm32(0x80000000), src);
 
         // Now src is [-2^31, 2^31-1] - int range, but not the same value.
         convertInt32ToDouble(src, dest);
 
         // dest is now a double with the int range.
         // correct the double value by adding 0x80000000.
         addConstantDouble(2147483648.0, dest);
     }
 
     // Note: this function clobbers the source register.
-    void convertUInt32ToFloat32(const Register &src, const FloatRegister &dest) {
+    void convertUInt32ToFloat32(Register src, const FloatRegister &dest) {
         convertUInt32ToDouble(src, dest);
         convertDoubleToFloat32(dest, dest);
     }
 
     void inc64(AbsoluteAddress dest) {
         addl(Imm32(1), Operand(dest));
         Label noOverflow;
         j(NonZero, &noOverflow);
@@ -1061,26 +1061,26 @@ class MacroAssemblerX86 : public MacroAs
     // In order for alignment to work correctly, the MacroAssembler must have a
     // consistent view of the stack displacement. It is okay to call "push"
     // manually, however, if the stack alignment were to change, the macro
     // assembler should be notified before starting a call.
     void setupAlignedABICall(uint32_t args);
 
     // Sets up an ABI call for when the alignment is not known. This may need a
     // scratch register.
-    void setupUnalignedABICall(uint32_t args, const Register &scratch);
+    void setupUnalignedABICall(uint32_t args, Register scratch);
 
     // Arguments must be assigned to a C/C++ call in order. They are moved
     // in parallel immediately before performing the call. This process may
     // temporarily use more stack, in which case esp-relative addresses will be
     // automatically adjusted. It is extremely important that esp-relative
     // addresses are computed *after* setupABICall(). Furthermore, no
     // operations should be emitted while setting arguments.
     void passABIArg(const MoveOperand &from, MoveOp::Type type);
-    void passABIArg(const Register &reg);
+    void passABIArg(Register reg);
     void passABIArg(const FloatRegister &reg, MoveOp::Type type);
 
   private:
     void callWithABIPre(uint32_t *stackAdjust);
     void callWithABIPost(uint32_t stackAdjust, MoveOp::Type result);
 
   public:
     // Emits a call to a C/C++ function, resolving all argument moves.
@@ -1114,17 +1114,17 @@ class MacroAssemblerX86 : public MacroAs
         appendCallSite(desc);
     }
     void callExit(AsmJSImmPtr target, uint32_t stackArgBytes) {
         call(CallSiteDesc::Exit(), target);
     }
 
     // Save an exit frame to the thread data of the current thread, given a
     // register that holds a PerThreadData *.
-    void linkParallelExitFrame(const Register &pt) {
+    void linkParallelExitFrame(Register pt) {
         movl(StackPointer, Operand(pt, offsetof(PerThreadData, jitTop)));
     }
 
 #ifdef JSGC_GENERATIONAL
     void branchPtrInNurseryRange(Condition cond, Register ptr, Register temp, Label *label);
     void branchValueIsNurseryObject(Condition cond, ValueOperand value, Register temp, Label *label);
 #endif
 };