Bug 1210322 - IonMonkey: MIPS: Rename BaseFloatRegister/s to FloatRegister/sMIPSShared. r=nbp
authorHeiher <r@hev.cc>
Mon, 12 Oct 2015 04:46:03 +0800
changeset 300600 6bd81a0dcc37e76228d36915b23a972b1ea27a92
parent 300599 80d22f41f35e7838a7116f086782e898a9752af7
child 300601 54b2262a04e52168c29b2361014ab506c6867747
push id5392
push userraliiev@mozilla.com
push dateMon, 14 Dec 2015 20:08:23 +0000
treeherdermozilla-beta@16ce8562a975 [default view] [failures only]
perfherder[talos] [build metrics] [platform microbench] (compared to previous push)
reviewersnbp
bugs1210322
milestone44.0a1
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Bug 1210322 - IonMonkey: MIPS: Rename BaseFloatRegister/s to FloatRegister/sMIPSShared. r=nbp --- js/src/jit/mips-shared/Architecture-mips-shared.h | 6 +++--- js/src/jit/mips32/Architecture-mips32.h | 4 ++-- js/src/jit/mips64/Architecture-mips64.h | 6 +++--- 3 files changed, 8 insertions(+), 8 deletions(-)
js/src/jit/mips-shared/Architecture-mips-shared.h
js/src/jit/mips32/Architecture-mips32.h
js/src/jit/mips64/Architecture-mips64.h
--- a/js/src/jit/mips-shared/Architecture-mips-shared.h
+++ b/js/src/jit/mips-shared/Architecture-mips-shared.h
@@ -218,17 +218,17 @@ class Registers
     static uint32_t LastBit(SetType x) {
         return 31 - mozilla::CountLeadingZeroes32(x);
     }
 };
 
 // Smallest integer type that can hold a register bitmask.
 typedef uint32_t PackedRegisterMask;
 
-class BaseFloatRegisters
+class FloatRegistersMIPSShared
 {
   public:
     enum FPRegisterID {
         f0 = 0,
         f1,
         f2,
         f3,
         f4,
@@ -281,23 +281,23 @@ class BaseFloatRegisters
     static const Code Invalid = invalid_freg;
 
     typedef uint64_t SetType;
 };
 
 template <typename T>
 class TypedRegisterSet;
 
-class BaseFloatRegister
+class FloatRegisterMIPSShared
 {
   public:
     bool isInt32x4() const { return false; }
     bool isFloat32x4() const { return false; }
 
-    typedef BaseFloatRegisters::SetType SetType;
+    typedef FloatRegistersMIPSShared::SetType SetType;
 
     static uint32_t SetSize(SetType x) {
         static_assert(sizeof(SetType) == 8, "SetType must be 64 bits");
         return mozilla::CountPopulation32(x);
     }
     static uint32_t FirstBit(SetType x) {
         return mozilla::CountTrailingZeroes64(x);
     }
--- a/js/src/jit/mips32/Architecture-mips32.h
+++ b/js/src/jit/mips32/Architecture-mips32.h
@@ -54,17 +54,17 @@ static const uint32_t BAILOUT_TABLE_ENTR
 // precision registers and pairs of even and odd float registers are used as
 // double precision registers. Example: f0 (double) is composed of
 // f0 and f1 (single).
 // - 64 bit floating-point coprocessor - In this case, there are 32 double
 // precision register which can also be used as single precision registers.
 
 // When using O32 ABI, floating-point coprocessor is 32 bit.
 // When using N32 ABI, floating-point coprocessor is 64 bit.
-class FloatRegisters : public BaseFloatRegisters
+class FloatRegisters : public FloatRegistersMIPSShared
 {
   public:
     static const char* GetName(uint32_t i) {
         MOZ_ASSERT(i < Total);
         return GetName(Code(i % 32));
     }
 
     static Code FromName(const char* name);
@@ -123,17 +123,17 @@ class FloatRegisters : public BaseFloatR
         (1ULL << FloatRegisters::f19);
 
     // Registers that can be allocated without being saved, generally.
     static const SetType TempMask = VolatileMask & ~NonAllocatableMask;
 
     static const SetType AllocatableMask = AllMask & ~NonAllocatableMask;
 };
 
-class FloatRegister : public BaseFloatRegister
+class FloatRegister : public FloatRegisterMIPSShared
 {
   public:
     enum RegType {
         Single = 0x0,
         Double = 0x1,
     };
 
     typedef FloatRegisters Codes;
--- a/js/src/jit/mips64/Architecture-mips64.h
+++ b/js/src/jit/mips64/Architecture-mips64.h
@@ -36,28 +36,28 @@
 namespace js {
 namespace jit {
 
 // Shadow stack space is not required on MIPS64.
 static const uint32_t ShadowStackSpace = 0;
 
 // MIPS64 have 64 bit floating-point coprocessor. There are 32 double
 // precision register which can also be used as single precision registers.
-class FloatRegisters : public BaseFloatRegisters
+class FloatRegisters : public FloatRegistersMIPSShared
 {
   public:
     enum ContentType {
         Single,
         Double,
         NumTypes
     };
 
     static const char* GetName(uint32_t i) {
         MOZ_ASSERT(i < TotalPhys);
-        return BaseFloatRegisters::GetName(Encoding(i));
+        return FloatRegistersMIPSShared::GetName(Encoding(i));
     }
 
     static Encoding FromName(const char* name);
 
     static const uint32_t Total = 32 * NumTypes;
     static const uint32_t Allocatable = 60;
     // When saving all registers we only need to do is save double registers.
     static const uint32_t TotalPhys = 32;
@@ -104,17 +104,17 @@ class FloatRegisters : public BaseFloatR
     static const SetType TempMask = VolatileMask & ~NonAllocatableMask;
 
     static const SetType AllocatableMask = AllMask & ~NonAllocatableMask;
 };
 
 template <typename T>
 class TypedRegisterSet;
 
-class FloatRegister : public BaseFloatRegister
+class FloatRegister : public FloatRegisterMIPSShared
 {
   public:
     typedef FloatRegisters Codes;
     typedef size_t Code;
     typedef Codes::Encoding Encoding;
     typedef Codes::ContentType ContentType;
 
     Encoding reg_: 6;