Bug 774364 - Part 2: Move architecture specific function from BaseAssembler-x86-shared.h to BaseAssembler-x86.h and BaseAssembler-x64.h. r=sstangl
authorTooru Fujisawa <arai_a@mac.com>
Fri, 07 Aug 2015 07:39:12 +0900
changeset 296093 41cce993981073d8319cab239570192c3aacd3d1
parent 296092 8eda15c59d265f755582342dd027e97959b2429b
child 296094 ef13876b06a6558b7999a382f23c70f1c4b9526a
push id5245
push userraliiev@mozilla.com
push dateThu, 29 Oct 2015 11:30:51 +0000
treeherdermozilla-beta@dac831dc1bd0 [default view] [failures only]
perfherder[talos] [build metrics] [platform microbench] (compared to previous push)
reviewerssstangl
bugs774364
milestone43.0a1
first release with
nightly linux32
nightly linux64
nightly mac
nightly win32
nightly win64
last release without
nightly linux32
nightly linux64
nightly mac
nightly win32
nightly win64
Bug 774364 - Part 2: Move architecture specific function from BaseAssembler-x86-shared.h to BaseAssembler-x86.h and BaseAssembler-x64.h. r=sstangl
js/src/jit/x64/BaseAssembler-x64.h
js/src/jit/x86-shared/Assembler-x86-shared.h
js/src/jit/x86-shared/BaseAssembler-x86-shared.h
js/src/jit/x86/BaseAssembler-x86.h
new file mode 100644
--- /dev/null
+++ b/js/src/jit/x64/BaseAssembler-x64.h
@@ -0,0 +1,782 @@
+/* -*- Mode: C++; tab-width: 8; indent-tabs-mode: nil; c-basic-offset: 4 -*-
+ * vim: set ts=8 sts=4 et sw=4 tw=99:
+ * This Source Code Form is subject to the terms of the Mozilla Public
+ * License, v. 2.0. If a copy of the MPL was not distributed with this
+ * file, You can obtain one at http://mozilla.org/MPL/2.0/. */
+
+#ifndef jit_x64_BaseAssembler_x64_h
+#define jit_x64_BaseAssembler_x64_h
+
+#include "jit/x86-shared/BaseAssembler-x86-shared.h"
+
+namespace js {
+namespace jit {
+
+namespace X86Encoding {
+
+class BaseAssemblerX64 : public BaseAssembler
+{
+  public:
+
+    // Arithmetic operations:
+
+    void addq_rr(RegisterID src, RegisterID dst)
+    {
+        spew("addq       %s, %s", GPReg64Name(src), GPReg64Name(dst));
+        m_formatter.oneByteOp64(OP_ADD_GvEv, src, dst);
+    }
+
+    void addq_mr(int32_t offset, RegisterID base, RegisterID dst)
+    {
+        spew("addq       " MEM_ob ", %s", ADDR_ob(offset, base), GPReg64Name(dst));
+        m_formatter.oneByteOp64(OP_ADD_GvEv, offset, base, dst);
+    }
+
+    void addq_mr(const void* addr, RegisterID dst)
+    {
+        spew("addq       %p, %s", addr, GPReg64Name(dst));
+        m_formatter.oneByteOp64(OP_ADD_GvEv, addr, dst);
+    }
+
+    void addq_ir(int32_t imm, RegisterID dst)
+    {
+        spew("addq       $%d, %s", imm, GPReg64Name(dst));
+        if (CAN_SIGN_EXTEND_8_32(imm)) {
+            m_formatter.oneByteOp64(OP_GROUP1_EvIb, dst, GROUP1_OP_ADD);
+            m_formatter.immediate8s(imm);
+        } else {
+            if (dst == rax)
+                m_formatter.oneByteOp64(OP_ADD_EAXIv);
+            else
+                m_formatter.oneByteOp64(OP_GROUP1_EvIz, dst, GROUP1_OP_ADD);
+            m_formatter.immediate32(imm);
+        }
+    }
+
+    void addq_im(int32_t imm, int32_t offset, RegisterID base)
+    {
+        spew("addq       $%d, " MEM_ob, imm, ADDR_ob(offset, base));
+        if (CAN_SIGN_EXTEND_8_32(imm)) {
+            m_formatter.oneByteOp64(OP_GROUP1_EvIb, offset, base, GROUP1_OP_ADD);
+            m_formatter.immediate8s(imm);
+        } else {
+            m_formatter.oneByteOp64(OP_GROUP1_EvIz, offset, base, GROUP1_OP_ADD);
+            m_formatter.immediate32(imm);
+        }
+    }
+
+    void addq_im(int32_t imm, const void* addr)
+    {
+        spew("addq       $%d, %p", imm, addr);
+        if (CAN_SIGN_EXTEND_8_32(imm)) {
+            m_formatter.oneByteOp64(OP_GROUP1_EvIb, addr, GROUP1_OP_ADD);
+            m_formatter.immediate8s(imm);
+        } else {
+            m_formatter.oneByteOp64(OP_GROUP1_EvIz, addr, GROUP1_OP_ADD);
+            m_formatter.immediate32(imm);
+        }
+    }
+
+    void andq_rr(RegisterID src, RegisterID dst)
+    {
+        spew("andq       %s, %s", GPReg64Name(src), GPReg64Name(dst));
+        m_formatter.oneByteOp64(OP_AND_GvEv, src, dst);
+    }
+
+    void andq_mr(int32_t offset, RegisterID base, RegisterID dst)
+    {
+        spew("andq       " MEM_ob ", %s", ADDR_ob(offset, base), GPReg64Name(dst));
+        m_formatter.oneByteOp64(OP_AND_GvEv, offset, base, dst);
+    }
+
+    void andq_mr(int32_t offset, RegisterID base, RegisterID index, int scale, RegisterID dst)
+    {
+        spew("andq       " MEM_obs ", %s", ADDR_obs(offset, base, index, scale), GPReg64Name(dst));
+        m_formatter.oneByteOp64(OP_AND_GvEv, offset, base, index, scale, dst);
+    }
+
+    void andq_mr(const void* addr, RegisterID dst)
+    {
+        spew("andq       %p, %s", addr, GPReg64Name(dst));
+        m_formatter.oneByteOp64(OP_AND_GvEv, addr, dst);
+    }
+
+    void orq_mr(int32_t offset, RegisterID base, RegisterID dst)
+    {
+        spew("orq        " MEM_ob ", %s", ADDR_ob(offset, base), GPReg64Name(dst));
+        m_formatter.oneByteOp64(OP_OR_GvEv, offset, base, dst);
+    }
+
+    void orq_mr(const void* addr, RegisterID dst)
+    {
+        spew("orq        %p, %s", addr, GPReg64Name(dst));
+        m_formatter.oneByteOp64(OP_OR_GvEv, addr, dst);
+    }
+
+    void andq_ir(int32_t imm, RegisterID dst)
+    {
+        spew("andq       $0x%" PRIx64 ", %s", int64_t(imm), GPReg64Name(dst));
+        if (CAN_SIGN_EXTEND_8_32(imm)) {
+            m_formatter.oneByteOp64(OP_GROUP1_EvIb, dst, GROUP1_OP_AND);
+            m_formatter.immediate8s(imm);
+        } else {
+            if (dst == rax)
+                m_formatter.oneByteOp64(OP_AND_EAXIv);
+            else
+                m_formatter.oneByteOp64(OP_GROUP1_EvIz, dst, GROUP1_OP_AND);
+            m_formatter.immediate32(imm);
+        }
+    }
+
+    void negq_r(RegisterID dst)
+    {
+        spew("negq       %s", GPReg64Name(dst));
+        m_formatter.oneByteOp64(OP_GROUP3_Ev, dst, GROUP3_OP_NEG);
+    }
+
+    void orq_rr(RegisterID src, RegisterID dst)
+    {
+        spew("orq        %s, %s", GPReg64Name(src), GPReg64Name(dst));
+        m_formatter.oneByteOp64(OP_OR_GvEv, src, dst);
+    }
+
+    void orq_ir(int32_t imm, RegisterID dst)
+    {
+        spew("orq        $0x%" PRIx64 ", %s", int64_t(imm), GPReg64Name(dst));
+        if (CAN_SIGN_EXTEND_8_32(imm)) {
+            m_formatter.oneByteOp64(OP_GROUP1_EvIb, dst, GROUP1_OP_OR);
+            m_formatter.immediate8s(imm);
+        } else {
+            if (dst == rax)
+                m_formatter.oneByteOp64(OP_OR_EAXIv);
+            else
+                m_formatter.oneByteOp64(OP_GROUP1_EvIz, dst, GROUP1_OP_OR);
+            m_formatter.immediate32(imm);
+        }
+    }
+
+    void notq_r(RegisterID dst)
+    {
+        spew("notq       %s", GPReg64Name(dst));
+        m_formatter.oneByteOp64(OP_GROUP3_Ev, dst, GROUP3_OP_NOT);
+    }
+
+    void subq_rr(RegisterID src, RegisterID dst)
+    {
+        spew("subq       %s, %s", GPReg64Name(src), GPReg64Name(dst));
+        m_formatter.oneByteOp64(OP_SUB_GvEv, src, dst);
+    }
+
+    void subq_rm(RegisterID src, int32_t offset, RegisterID base)
+    {
+        spew("subq       %s, " MEM_ob, GPReg64Name(src), ADDR_ob(offset, base));
+        m_formatter.oneByteOp64(OP_SUB_EvGv, offset, base, src);
+    }
+
+    void subq_mr(int32_t offset, RegisterID base, RegisterID dst)
+    {
+        spew("subq       " MEM_ob ", %s", ADDR_ob(offset, base), GPReg64Name(dst));
+        m_formatter.oneByteOp64(OP_SUB_GvEv, offset, base, dst);
+    }
+
+    void subq_mr(const void* addr, RegisterID dst)
+    {
+        spew("subq       %p, %s", addr, GPReg64Name(dst));
+        m_formatter.oneByteOp64(OP_SUB_GvEv, addr, dst);
+    }
+
+    void subq_ir(int32_t imm, RegisterID dst)
+    {
+        spew("subq       $%d, %s", imm, GPReg64Name(dst));
+        if (CAN_SIGN_EXTEND_8_32(imm)) {
+            m_formatter.oneByteOp64(OP_GROUP1_EvIb, dst, GROUP1_OP_SUB);
+            m_formatter.immediate8s(imm);
+        } else {
+            if (dst == rax)
+                m_formatter.oneByteOp64(OP_SUB_EAXIv);
+            else
+                m_formatter.oneByteOp64(OP_GROUP1_EvIz, dst, GROUP1_OP_SUB);
+            m_formatter.immediate32(imm);
+        }
+    }
+
+    void xorq_rr(RegisterID src, RegisterID dst)
+    {
+        spew("xorq       %s, %s", GPReg64Name(src), GPReg64Name(dst));
+        m_formatter.oneByteOp64(OP_XOR_GvEv, src, dst);
+    }
+
+    void xorq_ir(int32_t imm, RegisterID dst)
+    {
+        spew("xorq       $0x%" PRIx64 ", %s", int64_t(imm), GPReg64Name(dst));
+        if (CAN_SIGN_EXTEND_8_32(imm)) {
+            m_formatter.oneByteOp64(OP_GROUP1_EvIb, dst, GROUP1_OP_XOR);
+            m_formatter.immediate8s(imm);
+        } else {
+            if (dst == rax)
+                m_formatter.oneByteOp64(OP_XOR_EAXIv);
+            else
+                m_formatter.oneByteOp64(OP_GROUP1_EvIz, dst, GROUP1_OP_XOR);
+            m_formatter.immediate32(imm);
+        }
+    }
+
+    void sarq_CLr(RegisterID dst)
+    {
+        spew("sarq       %%cl, %s", GPReg64Name(dst));
+        m_formatter.oneByteOp64(OP_GROUP2_EvCL, dst, GROUP2_OP_SAR);
+    }
+
+    void sarq_ir(int32_t imm, RegisterID dst)
+    {
+        MOZ_ASSERT(imm < 64);
+        spew("sarq       $%d, %s", imm, GPReg64Name(dst));
+        if (imm == 1)
+            m_formatter.oneByteOp64(OP_GROUP2_Ev1, dst, GROUP2_OP_SAR);
+        else {
+            m_formatter.oneByteOp64(OP_GROUP2_EvIb, dst, GROUP2_OP_SAR);
+            m_formatter.immediate8u(imm);
+        }
+    }
+
+    void shlq_ir(int32_t imm, RegisterID dst)
+    {
+        MOZ_ASSERT(imm < 64);
+        spew("shlq       $%d, %s", imm, GPReg64Name(dst));
+        if (imm == 1)
+            m_formatter.oneByteOp64(OP_GROUP2_Ev1, dst, GROUP2_OP_SHL);
+        else {
+            m_formatter.oneByteOp64(OP_GROUP2_EvIb, dst, GROUP2_OP_SHL);
+            m_formatter.immediate8u(imm);
+        }
+    }
+
+    void shrq_ir(int32_t imm, RegisterID dst)
+    {
+        MOZ_ASSERT(imm < 64);
+        spew("shrq       $%d, %s", imm, GPReg64Name(dst));
+        if (imm == 1)
+            m_formatter.oneByteOp64(OP_GROUP2_Ev1, dst, GROUP2_OP_SHR);
+        else {
+            m_formatter.oneByteOp64(OP_GROUP2_EvIb, dst, GROUP2_OP_SHR);
+            m_formatter.immediate8u(imm);
+        }
+    }
+
+    void imulq_rr(RegisterID src, RegisterID dst)
+    {
+        spew("imulq      %s, %s", GPReg64Name(src), GPReg64Name(dst));
+        m_formatter.twoByteOp64(OP2_IMUL_GvEv, src, dst);
+    }
+
+    // Comparisons:
+
+    void cmpq_rr(RegisterID rhs, RegisterID lhs)
+    {
+        spew("cmpq       %s, %s", GPReg64Name(rhs), GPReg64Name(lhs));
+        m_formatter.oneByteOp64(OP_CMP_GvEv, rhs, lhs);
+    }
+
+    void cmpq_rm(RegisterID rhs, int32_t offset, RegisterID base)
+    {
+        spew("cmpq       %s, " MEM_ob, GPReg64Name(rhs), ADDR_ob(offset, base));
+        m_formatter.oneByteOp64(OP_CMP_EvGv, offset, base, rhs);
+    }
+
+    void cmpq_mr(int32_t offset, RegisterID base, RegisterID lhs)
+    {
+        spew("cmpq       " MEM_ob ", %s", ADDR_ob(offset, base), GPReg64Name(lhs));
+        m_formatter.oneByteOp64(OP_CMP_GvEv, offset, base, lhs);
+    }
+
+    void cmpq_ir(int32_t rhs, RegisterID lhs)
+    {
+        if (rhs == 0) {
+            testq_rr(lhs, lhs);
+            return;
+        }
+
+        spew("cmpq       $0x%" PRIx64 ", %s", int64_t(rhs), GPReg64Name(lhs));
+        if (CAN_SIGN_EXTEND_8_32(rhs)) {
+            m_formatter.oneByteOp64(OP_GROUP1_EvIb, lhs, GROUP1_OP_CMP);
+            m_formatter.immediate8s(rhs);
+        } else {
+            if (lhs == rax)
+                m_formatter.oneByteOp64(OP_CMP_EAXIv);
+            else
+                m_formatter.oneByteOp64(OP_GROUP1_EvIz, lhs, GROUP1_OP_CMP);
+            m_formatter.immediate32(rhs);
+        }
+    }
+
+    void cmpq_im(int32_t rhs, int32_t offset, RegisterID base)
+    {
+        spew("cmpq       $0x%" PRIx64 ", " MEM_ob, int64_t(rhs), ADDR_ob(offset, base));
+        if (CAN_SIGN_EXTEND_8_32(rhs)) {
+            m_formatter.oneByteOp64(OP_GROUP1_EvIb, offset, base, GROUP1_OP_CMP);
+            m_formatter.immediate8s(rhs);
+        } else {
+            m_formatter.oneByteOp64(OP_GROUP1_EvIz, offset, base, GROUP1_OP_CMP);
+            m_formatter.immediate32(rhs);
+        }
+    }
+
+    void cmpq_im(int32_t rhs, int32_t offset, RegisterID base, RegisterID index, int scale)
+    {
+        spew("cmpq       $0x%x, " MEM_obs, rhs, ADDR_obs(offset, base, index, scale));
+        if (CAN_SIGN_EXTEND_8_32(rhs)) {
+            m_formatter.oneByteOp64(OP_GROUP1_EvIb, offset, base, index, scale, GROUP1_OP_CMP);
+            m_formatter.immediate8s(rhs);
+        } else {
+            m_formatter.oneByteOp64(OP_GROUP1_EvIz, offset, base, index, scale, GROUP1_OP_CMP);
+            m_formatter.immediate32(rhs);
+        }
+    }
+    void cmpq_im(int32_t rhs, const void* addr)
+    {
+        spew("cmpq       $0x%" PRIx64 ", %p", int64_t(rhs), addr);
+        if (CAN_SIGN_EXTEND_8_32(rhs)) {
+            m_formatter.oneByteOp64(OP_GROUP1_EvIb, addr, GROUP1_OP_CMP);
+            m_formatter.immediate8s(rhs);
+        } else {
+            m_formatter.oneByteOp64(OP_GROUP1_EvIz, addr, GROUP1_OP_CMP);
+            m_formatter.immediate32(rhs);
+        }
+    }
+    void cmpq_rm(RegisterID rhs, const void* addr)
+    {
+        spew("cmpq       %s, %p", GPReg64Name(rhs), addr);
+        m_formatter.oneByteOp64(OP_CMP_EvGv, addr, rhs);
+    }
+
+    void testq_rr(RegisterID rhs, RegisterID lhs)
+    {
+        spew("testq      %s, %s", GPReg64Name(rhs), GPReg64Name(lhs));
+        m_formatter.oneByteOp64(OP_TEST_EvGv, lhs, rhs);
+    }
+
+    void testq_ir(int32_t rhs, RegisterID lhs)
+    {
+        // If the mask fits in a 32-bit immediate, we can use testl with a
+        // 32-bit subreg.
+        if (CAN_ZERO_EXTEND_32_64(rhs)) {
+            testl_ir(rhs, lhs);
+            return;
+        }
+        spew("testq      $0x%" PRIx64 ", %s", int64_t(rhs), GPReg64Name(lhs));
+        if (lhs == rax)
+            m_formatter.oneByteOp64(OP_TEST_EAXIv);
+        else
+            m_formatter.oneByteOp64(OP_GROUP3_EvIz, lhs, GROUP3_OP_TEST);
+        m_formatter.immediate32(rhs);
+    }
+
+    void testq_i32m(int32_t rhs, int32_t offset, RegisterID base)
+    {
+        spew("testq      $0x%" PRIx64 ", " MEM_ob, int64_t(rhs), ADDR_ob(offset, base));
+        m_formatter.oneByteOp64(OP_GROUP3_EvIz, offset, base, GROUP3_OP_TEST);
+        m_formatter.immediate32(rhs);
+    }
+
+    void testq_i32m(int32_t rhs, int32_t offset, RegisterID base, RegisterID index, int scale)
+    {
+        spew("testq      $0x%4x, " MEM_obs, rhs, ADDR_obs(offset, base, index, scale));
+        m_formatter.oneByteOp64(OP_GROUP3_EvIz, offset, base, index, scale, GROUP3_OP_TEST);
+        m_formatter.immediate32(rhs);
+    }
+
+    // Various move ops:
+
+    void xchgq_rr(RegisterID src, RegisterID dst)
+    {
+        spew("xchgq      %s, %s", GPReg64Name(src), GPReg64Name(dst));
+        m_formatter.oneByteOp64(OP_XCHG_GvEv, src, dst);
+    }
+    void xchgq_rm(RegisterID src, int32_t offset, RegisterID base)
+    {
+        spew("xchgq      %s, " MEM_ob, GPReg64Name(src), ADDR_ob(offset, base));
+        m_formatter.oneByteOp64(OP_XCHG_GvEv, offset, base, src);
+    }
+    void xchgq_rm(RegisterID src, int32_t offset, RegisterID base, RegisterID index, int scale)
+    {
+        spew("xchgq      %s, " MEM_obs, GPReg64Name(src), ADDR_obs(offset, base, index, scale));
+        m_formatter.oneByteOp64(OP_XCHG_GvEv, offset, base, index, scale, src);
+    }
+
+    void movq_rr(RegisterID src, RegisterID dst)
+    {
+        spew("movq       %s, %s", GPReg64Name(src), GPReg64Name(dst));
+        m_formatter.oneByteOp64(OP_MOV_GvEv, src, dst);
+    }
+
+    void movq_rm(RegisterID src, int32_t offset, RegisterID base)
+    {
+        spew("movq       %s, " MEM_ob, GPReg64Name(src), ADDR_ob(offset, base));
+        m_formatter.oneByteOp64(OP_MOV_EvGv, offset, base, src);
+    }
+
+    void movq_rm_disp32(RegisterID src, int32_t offset, RegisterID base)
+    {
+        spew("movq       %s, " MEM_o32b, GPReg64Name(src), ADDR_o32b(offset, base));
+        m_formatter.oneByteOp64_disp32(OP_MOV_EvGv, offset, base, src);
+    }
+
+    void movq_rm(RegisterID src, int32_t offset, RegisterID base, RegisterID index, int scale)
+    {
+        spew("movq       %s, " MEM_obs, GPReg64Name(src), ADDR_obs(offset, base, index, scale));
+        m_formatter.oneByteOp64(OP_MOV_EvGv, offset, base, index, scale, src);
+    }
+
+    void movq_rm(RegisterID src, const void* addr)
+    {
+        if (src == rax && !IsAddressImmediate(addr)) {
+            movq_EAXm(addr);
+            return;
+        }
+
+        spew("movq       %s, %p", GPReg64Name(src), addr);
+        m_formatter.oneByteOp64(OP_MOV_EvGv, addr, src);
+    }
+
+    void movq_mEAX(const void* addr)
+    {
+        if (IsAddressImmediate(addr)) {
+            movq_mr(addr, rax);
+            return;
+        }
+
+        spew("movq       %p, %%rax", addr);
+        m_formatter.oneByteOp64(OP_MOV_EAXOv);
+        m_formatter.immediate64(reinterpret_cast<int64_t>(addr));
+    }
+
+    void movq_EAXm(const void* addr)
+    {
+        if (IsAddressImmediate(addr)) {
+            movq_rm(rax, addr);
+            return;
+        }
+
+        spew("movq       %%rax, %p", addr);
+        m_formatter.oneByteOp64(OP_MOV_OvEAX);
+        m_formatter.immediate64(reinterpret_cast<int64_t>(addr));
+    }
+
+    void movq_mr(int32_t offset, RegisterID base, RegisterID dst)
+    {
+        spew("movq       " MEM_ob ", %s", ADDR_ob(offset, base), GPReg64Name(dst));
+        m_formatter.oneByteOp64(OP_MOV_GvEv, offset, base, dst);
+    }
+
+    void movq_mr_disp32(int32_t offset, RegisterID base, RegisterID dst)
+    {
+        spew("movq       " MEM_o32b ", %s", ADDR_o32b(offset, base), GPReg64Name(dst));
+        m_formatter.oneByteOp64_disp32(OP_MOV_GvEv, offset, base, dst);
+    }
+
+    void movq_mr(int32_t offset, RegisterID base, RegisterID index, int scale, RegisterID dst)
+    {
+        spew("movq       " MEM_obs ", %s", ADDR_obs(offset, base, index, scale), GPReg64Name(dst));
+        m_formatter.oneByteOp64(OP_MOV_GvEv, offset, base, index, scale, dst);
+    }
+
+    void movq_mr(const void* addr, RegisterID dst)
+    {
+        if (dst == rax && !IsAddressImmediate(addr)) {
+            movq_mEAX(addr);
+            return;
+        }
+
+        spew("movq       %p, %s", addr, GPReg64Name(dst));
+        m_formatter.oneByteOp64(OP_MOV_GvEv, addr, dst);
+    }
+
+    void leaq_mr(int32_t offset, RegisterID base, RegisterID index, int scale, RegisterID dst)
+    {
+        spew("leaq       " MEM_obs ", %s", ADDR_obs(offset, base, index, scale), GPReg64Name(dst)),
+        m_formatter.oneByteOp64(OP_LEA, offset, base, index, scale, dst);
+    }
+
+    void movq_i32m(int32_t imm, int32_t offset, RegisterID base)
+    {
+        spew("movq       $%d, " MEM_ob, imm, ADDR_ob(offset, base));
+        m_formatter.oneByteOp64(OP_GROUP11_EvIz, offset, base, GROUP11_MOV);
+        m_formatter.immediate32(imm);
+    }
+
+    void movq_i32m(int32_t imm, int32_t offset, RegisterID base, RegisterID index, int scale)
+    {
+        spew("movq       $%d, " MEM_obs, imm, ADDR_obs(offset, base, index, scale));
+        m_formatter.oneByteOp64(OP_GROUP11_EvIz, offset, base, index, scale, GROUP11_MOV);
+        m_formatter.immediate32(imm);
+    }
+    void movq_i32m(int32_t imm, const void* addr)
+    {
+        spew("movq       $%d, %p", imm, addr);
+        m_formatter.oneByteOp64(OP_GROUP11_EvIz, addr, GROUP11_MOV);
+        m_formatter.immediate32(imm);
+    }
+
+    // Note that this instruction sign-extends its 32-bit immediate field to 64
+    // bits and loads the 64-bit value into a 64-bit register.
+    //
+    // Note also that this is similar to the movl_i32r instruction, except that
+    // movl_i32r *zero*-extends its 32-bit immediate, and it has smaller code
+    // size, so it's preferred for values which could use either.
+    void movq_i32r(int32_t imm, RegisterID dst)
+    {
+        spew("movq       $%d, %s", imm, GPRegName(dst));
+        m_formatter.oneByteOp64(OP_GROUP11_EvIz, dst, GROUP11_MOV);
+        m_formatter.immediate32(imm);
+    }
+
+    void movq_i64r(int64_t imm, RegisterID dst)
+    {
+        spew("movabsq    $0x%" PRIx64 ", %s", imm, GPReg64Name(dst));
+        m_formatter.oneByteOp64(OP_MOV_EAXIv, dst);
+        m_formatter.immediate64(imm);
+    }
+
+    void movslq_rr(RegisterID src, RegisterID dst)
+    {
+        spew("movslq     %s, %s", GPReg32Name(src), GPReg64Name(dst));
+        m_formatter.oneByteOp64(OP_MOVSXD_GvEv, src, dst);
+    }
+    void movslq_mr(int32_t offset, RegisterID base, RegisterID dst)
+    {
+        spew("movslq     " MEM_ob ", %s", ADDR_ob(offset, base), GPReg64Name(dst));
+        m_formatter.oneByteOp64(OP_MOVSXD_GvEv, offset, base, dst);
+    }
+    void movslq_mr(int32_t offset, RegisterID base, RegisterID index, int scale, RegisterID dst)
+    {
+        spew("movslq     " MEM_obs ", %s", ADDR_obs(offset, base, index, scale), GPReg64Name(dst));
+        m_formatter.oneByteOp64(OP_MOVSXD_GvEv, offset, base, index, scale, dst);
+    }
+
+    MOZ_WARN_UNUSED_RESULT JmpSrc
+    movl_ripr(RegisterID dst)
+    {
+        m_formatter.oneByteRipOp(OP_MOV_GvEv, 0, (RegisterID)dst);
+        JmpSrc label(m_formatter.size());
+        spew("movl       " MEM_o32r ", %s", ADDR_o32r(label.offset()), GPReg32Name(dst));
+        return label;
+    }
+
+    MOZ_WARN_UNUSED_RESULT JmpSrc
+    movl_rrip(RegisterID src)
+    {
+        m_formatter.oneByteRipOp(OP_MOV_EvGv, 0, (RegisterID)src);
+        JmpSrc label(m_formatter.size());
+        spew("movl       %s, " MEM_o32r "", GPReg32Name(src), ADDR_o32r(label.offset()));
+        return label;
+    }
+
+    MOZ_WARN_UNUSED_RESULT JmpSrc
+    movq_ripr(RegisterID dst)
+    {
+        m_formatter.oneByteRipOp64(OP_MOV_GvEv, 0, dst);
+        JmpSrc label(m_formatter.size());
+        spew("movq       " MEM_o32r ", %s", ADDR_o32r(label.offset()), GPRegName(dst));
+        return label;
+    }
+
+    void leaq_mr(int32_t offset, RegisterID base, RegisterID dst)
+    {
+        spew("leaq       " MEM_ob ", %s", ADDR_ob(offset, base), GPReg64Name(dst));
+        m_formatter.oneByteOp64(OP_LEA, offset, base, dst);
+    }
+
+    MOZ_WARN_UNUSED_RESULT JmpSrc
+    leaq_rip(RegisterID dst)
+    {
+        m_formatter.oneByteRipOp64(OP_LEA, 0, dst);
+        JmpSrc label(m_formatter.size());
+        spew("leaq       " MEM_o32r ", %s", ADDR_o32r(label.offset()), GPRegName(dst));
+        return label;
+    }
+
+    // Flow control:
+
+    void jmp_rip(int ripOffset)
+    {
+        // rip-relative addressing.
+        spew("jmp        *%d(%%rip)", ripOffset);
+        m_formatter.oneByteRipOp(OP_GROUP5_Ev, ripOffset, GROUP5_OP_JMPN);
+    }
+
+    void immediate64(int64_t imm)
+    {
+        spew(".quad      %lld", (long long)imm);
+        m_formatter.immediate64(imm);
+    }
+
+    // SSE operations:
+
+    void vcvtsq2sd_rr(RegisterID src1, XMMRegisterID src0, XMMRegisterID dst)
+    {
+        twoByteOpInt64Simd("vcvtsi2sd", VEX_SD, OP2_CVTSI2SD_VsdEd, src1, src0, dst);
+    }
+    void vcvtsq2ss_rr(RegisterID src1, XMMRegisterID src0, XMMRegisterID dst)
+    {
+        twoByteOpInt64Simd("vcvtsi2ss", VEX_SS, OP2_CVTSI2SD_VsdEd, src1, src0, dst);
+    }
+
+    void vcvtsi2sdq_rr(RegisterID src, XMMRegisterID dst)
+    {
+        twoByteOpInt64Simd("vcvtsi2sdq", VEX_SD, OP2_CVTSI2SD_VsdEd, src, invalid_xmm, dst);
+    }
+
+    void vcvttsd2sq_rr(XMMRegisterID src, RegisterID dst)
+    {
+        twoByteOpSimdInt64("vcvttsd2si", VEX_SD, OP2_CVTTSD2SI_GdWsd, src, dst);
+    }
+
+    void vcvttss2sq_rr(XMMRegisterID src, RegisterID dst)
+    {
+        twoByteOpSimdInt64("vcvttss2si", VEX_SS, OP2_CVTTSD2SI_GdWsd, src, dst);
+    }
+
+    void vmovq_rr(XMMRegisterID src, RegisterID dst)
+    {
+        // While this is called "vmovq", it actually uses the vmovd encoding
+        // with a REX prefix modifying it to be 64-bit.
+        twoByteOpSimdInt64("vmovq", VEX_PD, OP2_MOVD_EdVd, (XMMRegisterID)dst, (RegisterID)src);
+    }
+
+    void vmovq_rr(RegisterID src, XMMRegisterID dst)
+    {
+        // While this is called "vmovq", it actually uses the vmovd encoding
+        // with a REX prefix modifying it to be 64-bit.
+        twoByteOpInt64Simd("vmovq", VEX_PD, OP2_MOVD_VdEd, src, invalid_xmm, dst);
+    }
+
+    MOZ_WARN_UNUSED_RESULT JmpSrc
+    vmovsd_ripr(XMMRegisterID dst)
+    {
+        return twoByteRipOpSimd("vmovsd", VEX_SD, OP2_MOVSD_VsdWsd, invalid_xmm, dst);
+    }
+    MOZ_WARN_UNUSED_RESULT JmpSrc
+    vmovss_ripr(XMMRegisterID dst)
+    {
+        return twoByteRipOpSimd("vmovss", VEX_SS, OP2_MOVSD_VsdWsd, invalid_xmm, dst);
+    }
+    MOZ_WARN_UNUSED_RESULT JmpSrc
+    vmovsd_rrip(XMMRegisterID src)
+    {
+        return twoByteRipOpSimd("vmovsd", VEX_SD, OP2_MOVSD_WsdVsd, invalid_xmm, src);
+    }
+    MOZ_WARN_UNUSED_RESULT JmpSrc
+    vmovss_rrip(XMMRegisterID src)
+    {
+        return twoByteRipOpSimd("vmovss", VEX_SS, OP2_MOVSD_WsdVsd, invalid_xmm, src);
+    }
+    MOZ_WARN_UNUSED_RESULT JmpSrc
+    vmovdqa_rrip(XMMRegisterID src)
+    {
+        return twoByteRipOpSimd("vmovdqa", VEX_PD, OP2_MOVDQ_WdqVdq, invalid_xmm, src);
+    }
+    MOZ_WARN_UNUSED_RESULT JmpSrc
+    vmovaps_rrip(XMMRegisterID src)
+    {
+        return twoByteRipOpSimd("vmovdqa", VEX_PS, OP2_MOVAPS_WsdVsd, invalid_xmm, src);
+    }
+
+    MOZ_WARN_UNUSED_RESULT JmpSrc
+    vmovaps_ripr(XMMRegisterID dst)
+    {
+        return twoByteRipOpSimd("vmovaps", VEX_PS, OP2_MOVAPS_VsdWsd, invalid_xmm, dst);
+    }
+
+    MOZ_WARN_UNUSED_RESULT JmpSrc
+    vmovdqa_ripr(XMMRegisterID dst)
+    {
+        return twoByteRipOpSimd("vmovdqa", VEX_PD, OP2_MOVDQ_VdqWdq, invalid_xmm, dst);
+    }
+
+  private:
+
+    MOZ_WARN_UNUSED_RESULT JmpSrc
+    twoByteRipOpSimd(const char* name, VexOperandType ty, TwoByteOpcodeID opcode,
+                     XMMRegisterID src0, XMMRegisterID dst)
+    {
+        if (useLegacySSEEncoding(src0, dst)) {
+            m_formatter.legacySSEPrefix(ty);
+            m_formatter.twoByteRipOp(opcode, 0, dst);
+            JmpSrc label(m_formatter.size());
+            if (IsXMMReversedOperands(opcode))
+                spew("%-11s%s, " MEM_o32r "", legacySSEOpName(name), XMMRegName(dst), ADDR_o32r(label.offset()));
+            else
+                spew("%-11s" MEM_o32r ", %s", legacySSEOpName(name), ADDR_o32r(label.offset()), XMMRegName(dst));
+            return label;
+        }
+
+        m_formatter.twoByteRipOpVex(ty, opcode, 0, src0, dst);
+        JmpSrc label(m_formatter.size());
+        if (src0 == invalid_xmm) {
+            if (IsXMMReversedOperands(opcode))
+                spew("%-11s%s, " MEM_o32r "", name, XMMRegName(dst), ADDR_o32r(label.offset()));
+            else
+                spew("%-11s" MEM_o32r ", %s", name, ADDR_o32r(label.offset()), XMMRegName(dst));
+        } else {
+            spew("%-11s" MEM_o32r ", %s, %s", name, ADDR_o32r(label.offset()), XMMRegName(src0), XMMRegName(dst));
+        }
+        return label;
+    }
+
+    void twoByteOpInt64Simd(const char* name, VexOperandType ty, TwoByteOpcodeID opcode,
+                            RegisterID rm, XMMRegisterID src0, XMMRegisterID dst)
+    {
+        if (useLegacySSEEncoding(src0, dst)) {
+            if (IsXMMReversedOperands(opcode))
+                spew("%-11s%s, %s", legacySSEOpName(name), XMMRegName(dst), GPRegName(rm));
+            else
+                spew("%-11s%s, %s", legacySSEOpName(name), GPRegName(rm), XMMRegName(dst));
+            m_formatter.legacySSEPrefix(ty);
+            m_formatter.twoByteOp64(opcode, rm, dst);
+            return;
+        }
+
+        if (src0 == invalid_xmm) {
+            if (IsXMMReversedOperands(opcode))
+                spew("%-11s%s, %s", name, XMMRegName(dst), GPRegName(rm));
+            else
+                spew("%-11s%s, %s", name, GPRegName(rm), XMMRegName(dst));
+        } else {
+            spew("%-11s%s, %s, %s", name, GPRegName(rm), XMMRegName(src0), XMMRegName(dst));
+        }
+        m_formatter.twoByteOpVex64(ty, opcode, rm, src0, dst);
+    }
+
+    void twoByteOpSimdInt64(const char* name, VexOperandType ty, TwoByteOpcodeID opcode,
+                            XMMRegisterID rm, RegisterID dst)
+    {
+        if (useLegacySSEEncodingForOtherOutput()) {
+            if (IsXMMReversedOperands(opcode))
+                spew("%-11s%s, %s", legacySSEOpName(name), GPRegName(dst), XMMRegName(rm));
+            else if (opcode == OP2_MOVD_EdVd)
+                spew("%-11s%s, %s", legacySSEOpName(name), XMMRegName((XMMRegisterID)dst), GPRegName((RegisterID)rm));
+            else
+                spew("%-11s%s, %s", legacySSEOpName(name), XMMRegName(rm), GPRegName(dst));
+            m_formatter.legacySSEPrefix(ty);
+            m_formatter.twoByteOp64(opcode, (RegisterID)rm, dst);
+            return;
+        }
+
+        if (IsXMMReversedOperands(opcode))
+            spew("%-11s%s, %s", name, GPRegName(dst), XMMRegName(rm));
+        else if (opcode == OP2_MOVD_EdVd)
+            spew("%-11s%s, %s", name, XMMRegName((XMMRegisterID)dst), GPRegName((RegisterID)rm));
+        else
+            spew("%-11s%s, %s", name, XMMRegName(rm), GPRegName(dst));
+        m_formatter.twoByteOpVex64(ty, opcode, (RegisterID)rm, invalid_xmm, (XMMRegisterID)dst);
+    }
+};
+
+typedef BaseAssemblerX64 BaseAssemblerSpecific;
+
+} // namespace X86Encoding
+
+} // namespace jit
+} // namespace js
+
+#endif /* jit_x64_BaseAssembler_x64_h */
--- a/js/src/jit/x86-shared/Assembler-x86-shared.h
+++ b/js/src/jit/x86-shared/Assembler-x86-shared.h
@@ -5,17 +5,24 @@
  * file, You can obtain one at http://mozilla.org/MPL/2.0/. */
 
 #ifndef jit_x86_shared_Assembler_x86_shared_h
 #define jit_x86_shared_Assembler_x86_shared_h
 
 #include <cstddef>
 
 #include "jit/shared/Assembler-shared.h"
-#include "jit/x86-shared/BaseAssembler-x86-shared.h"
+
+#if defined(JS_CODEGEN_X86)
+# include "jit/x86/BaseAssembler-x86.h"
+#elif defined(JS_CODEGEN_X64)
+# include "jit/x64/BaseAssembler-x64.h"
+#else
+# error "Unknown architecture!"
+#endif
 
 namespace js {
 namespace jit {
 
 struct ScratchFloat32Scope : public AutoFloatRegisterScope
 {
     explicit ScratchFloat32Scope(MacroAssembler& masm)
       : AutoFloatRegisterScope(masm, ScratchFloat32Reg)
@@ -256,17 +263,17 @@ class AssemblerX86Shared : public Assemb
             dataRelocations_.writeUnsigned(masm.currentOffset());
         }
     }
     void writePrebarrierOffset(CodeOffsetLabel label) {
         preBarriers_.writeUnsigned(label.offset());
     }
 
   protected:
-    X86Encoding::BaseAssembler masm;
+    X86Encoding::BaseAssemblerSpecific masm;
 
     typedef X86Encoding::JmpSrc JmpSrc;
     typedef X86Encoding::JmpDst JmpDst;
 
   public:
     AssemblerX86Shared()
     {
         if (!HasAVX())
--- a/js/src/jit/x86-shared/BaseAssembler-x86-shared.h
+++ b/js/src/jit/x86-shared/BaseAssembler-x86-shared.h
@@ -251,30 +251,16 @@ public:
     void pop_flags()
     {
         spew("popf");
         m_formatter.oneByteOp(OP_POPFLAGS);
     }
 
     // Arithmetic operations:
 
-#ifdef JS_CODEGEN_X86
-    void adcl_im(int32_t imm, const void* addr)
-    {
-        spew("adcl       %d, %p", imm, addr);
-        if (CAN_SIGN_EXTEND_8_32(imm)) {
-            m_formatter.oneByteOp(OP_GROUP1_EvIb, addr, GROUP1_OP_ADC);
-            m_formatter.immediate8s(imm);
-        } else {
-            m_formatter.oneByteOp(OP_GROUP1_EvIz, addr, GROUP1_OP_ADC);
-            m_formatter.immediate32(imm);
-        }
-    }
-#endif
-
     void addl_rr(RegisterID src, RegisterID dst)
     {
         spew("addl       %s, %s", GPReg32Name(src), GPReg32Name(dst));
         m_formatter.oneByteOp(OP_ADD_GvEv, src, dst);
     }
 
     void addw_rr(RegisterID src, RegisterID dst)
     {
@@ -354,74 +340,16 @@ public:
             m_formatter.oneByteOp(OP_GROUP1_EvIb, offset, base, index, scale, GROUP1_OP_ADD);
             m_formatter.immediate8s(imm);
         } else {
             m_formatter.oneByteOp(OP_GROUP1_EvIz, offset, base, index, scale, GROUP1_OP_ADD);
             m_formatter.immediate32(imm);
         }
     }
 
-#ifdef JS_CODEGEN_X64
-    void addq_rr(RegisterID src, RegisterID dst)
-    {
-        spew("addq       %s, %s", GPReg64Name(src), GPReg64Name(dst));
-        m_formatter.oneByteOp64(OP_ADD_GvEv, src, dst);
-    }
-
-    void addq_mr(int32_t offset, RegisterID base, RegisterID dst)
-    {
-        spew("addq       " MEM_ob ", %s", ADDR_ob(offset, base), GPReg64Name(dst));
-        m_formatter.oneByteOp64(OP_ADD_GvEv, offset, base, dst);
-    }
-
-    void addq_mr(const void* addr, RegisterID dst)
-    {
-        spew("addq       %p, %s", addr, GPReg64Name(dst));
-        m_formatter.oneByteOp64(OP_ADD_GvEv, addr, dst);
-    }
-
-    void addq_ir(int32_t imm, RegisterID dst)
-    {
-        spew("addq       $%d, %s", imm, GPReg64Name(dst));
-        if (CAN_SIGN_EXTEND_8_32(imm)) {
-            m_formatter.oneByteOp64(OP_GROUP1_EvIb, dst, GROUP1_OP_ADD);
-            m_formatter.immediate8s(imm);
-        } else {
-            if (dst == rax)
-                m_formatter.oneByteOp64(OP_ADD_EAXIv);
-            else
-                m_formatter.oneByteOp64(OP_GROUP1_EvIz, dst, GROUP1_OP_ADD);
-            m_formatter.immediate32(imm);
-        }
-    }
-
-    void addq_im(int32_t imm, int32_t offset, RegisterID base)
-    {
-        spew("addq       $%d, " MEM_ob, imm, ADDR_ob(offset, base));
-        if (CAN_SIGN_EXTEND_8_32(imm)) {
-            m_formatter.oneByteOp64(OP_GROUP1_EvIb, offset, base, GROUP1_OP_ADD);
-            m_formatter.immediate8s(imm);
-        } else {
-            m_formatter.oneByteOp64(OP_GROUP1_EvIz, offset, base, GROUP1_OP_ADD);
-            m_formatter.immediate32(imm);
-        }
-    }
-
-    void addq_im(int32_t imm, const void* addr)
-    {
-        spew("addq       $%d, %p", imm, addr);
-        if (CAN_SIGN_EXTEND_8_32(imm)) {
-            m_formatter.oneByteOp64(OP_GROUP1_EvIb, addr, GROUP1_OP_ADD);
-            m_formatter.immediate8s(imm);
-        } else {
-            m_formatter.oneByteOp64(OP_GROUP1_EvIz, addr, GROUP1_OP_ADD);
-            m_formatter.immediate32(imm);
-        }
-    }
-#endif
     void addl_im(int32_t imm, const void* addr)
     {
         spew("addl       $%d, %p", imm, addr);
         if (CAN_SIGN_EXTEND_8_32(imm)) {
             m_formatter.oneByteOp(OP_GROUP1_EvIb, addr, GROUP1_OP_ADD);
             m_formatter.immediate8s(imm);
         } else {
             m_formatter.oneByteOp(OP_GROUP1_EvIz, addr, GROUP1_OP_ADD);
@@ -864,81 +792,16 @@ public:
             m_formatter.oneByteOp(OP_GROUP1_EvIb, offset, base, index, scale, GROUP1_OP_AND);
             m_formatter.immediate8s(imm);
         } else {
             m_formatter.oneByteOp(OP_GROUP1_EvIz, offset, base, index, scale, GROUP1_OP_AND);
             m_formatter.immediate16(imm);
         }
     }
 
-#ifdef JS_CODEGEN_X64
-    void andq_rr(RegisterID src, RegisterID dst)
-    {
-        spew("andq       %s, %s", GPReg64Name(src), GPReg64Name(dst));
-        m_formatter.oneByteOp64(OP_AND_GvEv, src, dst);
-    }
-
-    void andq_mr(int32_t offset, RegisterID base, RegisterID dst)
-    {
-        spew("andq       " MEM_ob ", %s", ADDR_ob(offset, base), GPReg64Name(dst));
-        m_formatter.oneByteOp64(OP_AND_GvEv, offset, base, dst);
-    }
-
-    void andq_mr(int32_t offset, RegisterID base, RegisterID index, int scale, RegisterID dst)
-    {
-        spew("andq       " MEM_obs ", %s", ADDR_obs(offset, base, index, scale), GPReg64Name(dst));
-        m_formatter.oneByteOp64(OP_AND_GvEv, offset, base, index, scale, dst);
-    }
-
-    void andq_mr(const void* addr, RegisterID dst)
-    {
-        spew("andq       %p, %s", addr, GPReg64Name(dst));
-        m_formatter.oneByteOp64(OP_AND_GvEv, addr, dst);
-    }
-
-    void orq_mr(int32_t offset, RegisterID base, RegisterID dst)
-    {
-        spew("orq        " MEM_ob ", %s", ADDR_ob(offset, base), GPReg64Name(dst));
-        m_formatter.oneByteOp64(OP_OR_GvEv, offset, base, dst);
-    }
-
-    void orq_mr(const void* addr, RegisterID dst)
-    {
-        spew("orq        %p, %s", addr, GPReg64Name(dst));
-        m_formatter.oneByteOp64(OP_OR_GvEv, addr, dst);
-    }
-
-    void andq_ir(int32_t imm, RegisterID dst)
-    {
-        spew("andq       $0x%" PRIx64 ", %s", int64_t(imm), GPReg64Name(dst));
-        if (CAN_SIGN_EXTEND_8_32(imm)) {
-            m_formatter.oneByteOp64(OP_GROUP1_EvIb, dst, GROUP1_OP_AND);
-            m_formatter.immediate8s(imm);
-        } else {
-            if (dst == rax)
-                m_formatter.oneByteOp64(OP_AND_EAXIv);
-            else
-                m_formatter.oneByteOp64(OP_GROUP1_EvIz, dst, GROUP1_OP_AND);
-            m_formatter.immediate32(imm);
-        }
-    }
-#else
-    void andl_im(int32_t imm, const void* addr)
-    {
-        spew("andl       $0x%x, %p", imm, addr);
-        if (CAN_SIGN_EXTEND_8_32(imm)) {
-            m_formatter.oneByteOp(OP_GROUP1_EvIb, addr, GROUP1_OP_AND);
-            m_formatter.immediate8s(imm);
-        } else {
-            m_formatter.oneByteOp(OP_GROUP1_EvIz, addr, GROUP1_OP_AND);
-            m_formatter.immediate32(imm);
-        }
-    }
-#endif
-
     void fld_m(int32_t offset, RegisterID base)
     {
         spew("fld        " MEM_ob, ADDR_ob(offset, base));
         m_formatter.oneByteOp(OP_FPU6, offset, base, FPU6_OP_FLD);
     }
     void fld32_m(int32_t offset, RegisterID base)
     {
         spew("fld        " MEM_ob, ADDR_ob(offset, base));
@@ -1105,63 +968,16 @@ public:
             m_formatter.oneByteOp(OP_GROUP1_EvIb, offset, base, index, scale, GROUP1_OP_OR);
             m_formatter.immediate8s(imm);
         } else {
             m_formatter.oneByteOp(OP_GROUP1_EvIz, offset, base, index, scale, GROUP1_OP_OR);
             m_formatter.immediate16(imm);
         }
     }
 
-#ifdef JS_CODEGEN_X64
-    void negq_r(RegisterID dst)
-    {
-        spew("negq       %s", GPReg64Name(dst));
-        m_formatter.oneByteOp64(OP_GROUP3_Ev, dst, GROUP3_OP_NEG);
-    }
-
-    void orq_rr(RegisterID src, RegisterID dst)
-    {
-        spew("orq        %s, %s", GPReg64Name(src), GPReg64Name(dst));
-        m_formatter.oneByteOp64(OP_OR_GvEv, src, dst);
-    }
-
-    void orq_ir(int32_t imm, RegisterID dst)
-    {
-        spew("orq        $0x%" PRIx64 ", %s", int64_t(imm), GPReg64Name(dst));
-        if (CAN_SIGN_EXTEND_8_32(imm)) {
-            m_formatter.oneByteOp64(OP_GROUP1_EvIb, dst, GROUP1_OP_OR);
-            m_formatter.immediate8s(imm);
-        } else {
-            if (dst == rax)
-                m_formatter.oneByteOp64(OP_OR_EAXIv);
-            else
-                m_formatter.oneByteOp64(OP_GROUP1_EvIz, dst, GROUP1_OP_OR);
-            m_formatter.immediate32(imm);
-        }
-    }
-
-    void notq_r(RegisterID dst)
-    {
-        spew("notq       %s", GPReg64Name(dst));
-        m_formatter.oneByteOp64(OP_GROUP3_Ev, dst, GROUP3_OP_NOT);
-    }
-#else
-    void orl_im(int32_t imm, const void* addr)
-    {
-        spew("orl        $0x%x, %p", imm, addr);
-        if (CAN_SIGN_EXTEND_8_32(imm)) {
-            m_formatter.oneByteOp(OP_GROUP1_EvIb, addr, GROUP1_OP_OR);
-            m_formatter.immediate8s(imm);
-        } else {
-            m_formatter.oneByteOp(OP_GROUP1_EvIz, addr, GROUP1_OP_OR);
-            m_formatter.immediate32(imm);
-        }
-    }
-#endif
-
     void subl_rr(RegisterID src, RegisterID dst)
     {
         spew("subl       %s, %s", GPReg32Name(src), GPReg32Name(dst));
         m_formatter.oneByteOp(OP_SUB_GvEv, src, dst);
     }
 
     void subw_rr(RegisterID src, RegisterID dst)
     {
@@ -1278,69 +1094,16 @@ public:
             m_formatter.oneByteOp(OP_GROUP1_EvIb, offset, base, index, scale, GROUP1_OP_SUB);
             m_formatter.immediate8s(imm);
         } else {
             m_formatter.oneByteOp(OP_GROUP1_EvIz, offset, base, index, scale, GROUP1_OP_SUB);
             m_formatter.immediate16(imm);
         }
     }
 
-#ifdef JS_CODEGEN_X64
-    void subq_rr(RegisterID src, RegisterID dst)
-    {
-        spew("subq       %s, %s", GPReg64Name(src), GPReg64Name(dst));
-        m_formatter.oneByteOp64(OP_SUB_GvEv, src, dst);
-    }
-
-    void subq_rm(RegisterID src, int32_t offset, RegisterID base)
-    {
-        spew("subq       %s, " MEM_ob, GPReg64Name(src), ADDR_ob(offset, base));
-        m_formatter.oneByteOp64(OP_SUB_EvGv, offset, base, src);
-    }
-
-    void subq_mr(int32_t offset, RegisterID base, RegisterID dst)
-    {
-        spew("subq       " MEM_ob ", %s", ADDR_ob(offset, base), GPReg64Name(dst));
-        m_formatter.oneByteOp64(OP_SUB_GvEv, offset, base, dst);
-    }
-
-    void subq_mr(const void* addr, RegisterID dst)
-    {
-        spew("subq       %p, %s", addr, GPReg64Name(dst));
-        m_formatter.oneByteOp64(OP_SUB_GvEv, addr, dst);
-    }
-
-    void subq_ir(int32_t imm, RegisterID dst)
-    {
-        spew("subq       $%d, %s", imm, GPReg64Name(dst));
-        if (CAN_SIGN_EXTEND_8_32(imm)) {
-            m_formatter.oneByteOp64(OP_GROUP1_EvIb, dst, GROUP1_OP_SUB);
-            m_formatter.immediate8s(imm);
-        } else {
-            if (dst == rax)
-                m_formatter.oneByteOp64(OP_SUB_EAXIv);
-            else
-                m_formatter.oneByteOp64(OP_GROUP1_EvIz, dst, GROUP1_OP_SUB);
-            m_formatter.immediate32(imm);
-        }
-    }
-#else
-    void subl_im(int32_t imm, const void* addr)
-    {
-        spew("subl       $%d, %p", imm, addr);
-        if (CAN_SIGN_EXTEND_8_32(imm)) {
-            m_formatter.oneByteOp(OP_GROUP1_EvIb, addr, GROUP1_OP_SUB);
-            m_formatter.immediate8s(imm);
-        } else {
-            m_formatter.oneByteOp(OP_GROUP1_EvIz, addr, GROUP1_OP_SUB);
-            m_formatter.immediate32(imm);
-        }
-    }
-#endif
-
     void xorl_rr(RegisterID src, RegisterID dst)
     {
         spew("xorl       %s, %s", GPReg32Name(src), GPReg32Name(dst));
         m_formatter.oneByteOp(OP_XOR_GvEv, src, dst);
     }
 
     void xorw_rr(RegisterID src, RegisterID dst)
     {
@@ -1457,39 +1220,16 @@ public:
             if (dst == rax)
                 m_formatter.oneByteOp(OP_XOR_EAXIv);
             else
                 m_formatter.oneByteOp(OP_GROUP1_EvIz, dst, GROUP1_OP_XOR);
             m_formatter.immediate16(imm);
         }
     }
 
-#ifdef JS_CODEGEN_X64
-    void xorq_rr(RegisterID src, RegisterID dst)
-    {
-        spew("xorq       %s, %s", GPReg64Name(src), GPReg64Name(dst));
-        m_formatter.oneByteOp64(OP_XOR_GvEv, src, dst);
-    }
-
-    void xorq_ir(int32_t imm, RegisterID dst)
-    {
-        spew("xorq       $0x%" PRIx64 ", %s", int64_t(imm), GPReg64Name(dst));
-        if (CAN_SIGN_EXTEND_8_32(imm)) {
-            m_formatter.oneByteOp64(OP_GROUP1_EvIb, dst, GROUP1_OP_XOR);
-            m_formatter.immediate8s(imm);
-        } else {
-            if (dst == rax)
-                m_formatter.oneByteOp64(OP_XOR_EAXIv);
-            else
-                m_formatter.oneByteOp64(OP_GROUP1_EvIz, dst, GROUP1_OP_XOR);
-            m_formatter.immediate32(imm);
-        }
-    }
-#endif
-
     void sarl_ir(int32_t imm, RegisterID dst)
     {
         MOZ_ASSERT(imm < 32);
         spew("sarl       $%d, %s", imm, GPReg32Name(dst));
         if (imm == 1)
             m_formatter.oneByteOp(OP_GROUP2_Ev1, dst, GROUP2_OP_SAR);
         else {
             m_formatter.oneByteOp(OP_GROUP2_EvIb, dst, GROUP2_OP_SAR);
@@ -1534,60 +1274,16 @@ public:
     }
 
     void shll_CLr(RegisterID dst)
     {
         spew("shll       %%cl, %s", GPReg32Name(dst));
         m_formatter.oneByteOp(OP_GROUP2_EvCL, dst, GROUP2_OP_SHL);
     }
 
-#ifdef JS_CODEGEN_X64
-    void sarq_CLr(RegisterID dst)
-    {
-        spew("sarq       %%cl, %s", GPReg64Name(dst));
-        m_formatter.oneByteOp64(OP_GROUP2_EvCL, dst, GROUP2_OP_SAR);
-    }
-
-    void sarq_ir(int32_t imm, RegisterID dst)
-    {
-        MOZ_ASSERT(imm < 64);
-        spew("sarq       $%d, %s", imm, GPReg64Name(dst));
-        if (imm == 1)
-            m_formatter.oneByteOp64(OP_GROUP2_Ev1, dst, GROUP2_OP_SAR);
-        else {
-            m_formatter.oneByteOp64(OP_GROUP2_EvIb, dst, GROUP2_OP_SAR);
-            m_formatter.immediate8u(imm);
-        }
-    }
-
-    void shlq_ir(int32_t imm, RegisterID dst)
-    {
-        MOZ_ASSERT(imm < 64);
-        spew("shlq       $%d, %s", imm, GPReg64Name(dst));
-        if (imm == 1)
-            m_formatter.oneByteOp64(OP_GROUP2_Ev1, dst, GROUP2_OP_SHL);
-        else {
-            m_formatter.oneByteOp64(OP_GROUP2_EvIb, dst, GROUP2_OP_SHL);
-            m_formatter.immediate8u(imm);
-        }
-    }
-
-    void shrq_ir(int32_t imm, RegisterID dst)
-    {
-        MOZ_ASSERT(imm < 64);
-        spew("shrq       $%d, %s", imm, GPReg64Name(dst));
-        if (imm == 1)
-            m_formatter.oneByteOp64(OP_GROUP2_Ev1, dst, GROUP2_OP_SHR);
-        else {
-            m_formatter.oneByteOp64(OP_GROUP2_EvIb, dst, GROUP2_OP_SHR);
-            m_formatter.immediate8u(imm);
-        }
-    }
-#endif
-
     void bsr_rr(RegisterID src, RegisterID dst)
     {
         spew("bsr        %s, %s", GPReg32Name(src), GPReg32Name(dst));
         m_formatter.twoByteOp(OP2_BSR_GvEv, src, dst);
     }
 
     void imull_rr(RegisterID src, RegisterID dst)
     {
@@ -1614,24 +1310,16 @@ public:
             m_formatter.oneByteOp(OP_IMUL_GvEvIb, src, dst);
             m_formatter.immediate8s(value);
         } else {
             m_formatter.oneByteOp(OP_IMUL_GvEvIz, src, dst);
             m_formatter.immediate32(value);
         }
     }
 
-#ifdef JS_CODEGEN_X64
-    void imulq_rr(RegisterID src, RegisterID dst)
-    {
-        spew("imulq      %s, %s", GPReg64Name(src), GPReg64Name(dst));
-        m_formatter.twoByteOp64(OP2_IMUL_GvEv, src, dst);
-    }
-#endif
-
     void mull_r(RegisterID multiplier)
     {
         spew("mull       %s", GPReg32Name(multiplier));
         m_formatter.oneByteOp(OP_GROUP3_Ev, multiplier, GROUP3_OP_MUL);
     }
 
     void idivl_r(RegisterID divisor)
     {
@@ -1844,95 +1532,16 @@ public:
 
     void cmpl_i32m(int32_t rhs, const void* addr)
     {
         spew("cmpl       $0x%04x, %p", rhs, addr);
         m_formatter.oneByteOp(OP_GROUP1_EvIz, addr, GROUP1_OP_CMP);
         m_formatter.immediate32(rhs);
     }
 
-#ifdef JS_CODEGEN_X64
-    void cmpq_rr(RegisterID rhs, RegisterID lhs)
-    {
-        spew("cmpq       %s, %s", GPReg64Name(rhs), GPReg64Name(lhs));
-        m_formatter.oneByteOp64(OP_CMP_GvEv, rhs, lhs);
-    }
-
-    void cmpq_rm(RegisterID rhs, int32_t offset, RegisterID base)
-    {
-        spew("cmpq       %s, " MEM_ob, GPReg64Name(rhs), ADDR_ob(offset, base));
-        m_formatter.oneByteOp64(OP_CMP_EvGv, offset, base, rhs);
-    }
-
-    void cmpq_mr(int32_t offset, RegisterID base, RegisterID lhs)
-    {
-        spew("cmpq       " MEM_ob ", %s", ADDR_ob(offset, base), GPReg64Name(lhs));
-        m_formatter.oneByteOp64(OP_CMP_GvEv, offset, base, lhs);
-    }
-
-    void cmpq_ir(int32_t rhs, RegisterID lhs)
-    {
-        if (rhs == 0) {
-            testq_rr(lhs, lhs);
-            return;
-        }
-
-        spew("cmpq       $0x%" PRIx64 ", %s", int64_t(rhs), GPReg64Name(lhs));
-        if (CAN_SIGN_EXTEND_8_32(rhs)) {
-            m_formatter.oneByteOp64(OP_GROUP1_EvIb, lhs, GROUP1_OP_CMP);
-            m_formatter.immediate8s(rhs);
-        } else {
-            if (lhs == rax)
-                m_formatter.oneByteOp64(OP_CMP_EAXIv);
-            else
-                m_formatter.oneByteOp64(OP_GROUP1_EvIz, lhs, GROUP1_OP_CMP);
-            m_formatter.immediate32(rhs);
-        }
-    }
-
-    void cmpq_im(int32_t rhs, int32_t offset, RegisterID base)
-    {
-        spew("cmpq       $0x%" PRIx64 ", " MEM_ob, int64_t(rhs), ADDR_ob(offset, base));
-        if (CAN_SIGN_EXTEND_8_32(rhs)) {
-            m_formatter.oneByteOp64(OP_GROUP1_EvIb, offset, base, GROUP1_OP_CMP);
-            m_formatter.immediate8s(rhs);
-        } else {
-            m_formatter.oneByteOp64(OP_GROUP1_EvIz, offset, base, GROUP1_OP_CMP);
-            m_formatter.immediate32(rhs);
-        }
-    }
-
-    void cmpq_im(int32_t rhs, int32_t offset, RegisterID base, RegisterID index, int scale)
-    {
-        spew("cmpq       $0x%x, " MEM_obs, rhs, ADDR_obs(offset, base, index, scale));
-        if (CAN_SIGN_EXTEND_8_32(rhs)) {
-            m_formatter.oneByteOp64(OP_GROUP1_EvIb, offset, base, index, scale, GROUP1_OP_CMP);
-            m_formatter.immediate8s(rhs);
-        } else {
-            m_formatter.oneByteOp64(OP_GROUP1_EvIz, offset, base, index, scale, GROUP1_OP_CMP);
-            m_formatter.immediate32(rhs);
-        }
-    }
-    void cmpq_im(int32_t rhs, const void* addr)
-    {
-        spew("cmpq       $0x%" PRIx64 ", %p", int64_t(rhs), addr);
-        if (CAN_SIGN_EXTEND_8_32(rhs)) {
-            m_formatter.oneByteOp64(OP_GROUP1_EvIb, addr, GROUP1_OP_CMP);
-            m_formatter.immediate8s(rhs);
-        } else {
-            m_formatter.oneByteOp64(OP_GROUP1_EvIz, addr, GROUP1_OP_CMP);
-            m_formatter.immediate32(rhs);
-        }
-    }
-    void cmpq_rm(RegisterID rhs, const void* addr)
-    {
-        spew("cmpq       %s, %p", GPReg64Name(rhs), addr);
-        m_formatter.oneByteOp64(OP_CMP_EvGv, addr, rhs);
-    }
-#endif
     void cmpl_rm(RegisterID rhs, const void* addr)
     {
         spew("cmpl       %s, %p", GPReg32Name(rhs), addr);
         m_formatter.oneByteOp(OP_CMP_EvGv, addr, rhs);
     }
 
     void cmpl_rm_disp32(RegisterID rhs, const void* addr)
     {
@@ -2044,54 +1653,16 @@ public:
 
     void testl_i32m(int32_t rhs, int32_t offset, RegisterID base, RegisterID index, int scale)
     {
         spew("testl      $0x%4x, " MEM_obs, rhs, ADDR_obs(offset, base, index, scale));
         m_formatter.oneByteOp(OP_GROUP3_EvIz, offset, base, index, scale, GROUP3_OP_TEST);
         m_formatter.immediate32(rhs);
     }
 
-#ifdef JS_CODEGEN_X64
-    void testq_rr(RegisterID rhs, RegisterID lhs)
-    {
-        spew("testq      %s, %s", GPReg64Name(rhs), GPReg64Name(lhs));
-        m_formatter.oneByteOp64(OP_TEST_EvGv, lhs, rhs);
-    }
-
-    void testq_ir(int32_t rhs, RegisterID lhs)
-    {
-        // If the mask fits in a 32-bit immediate, we can use testl with a
-        // 32-bit subreg.
-        if (CAN_ZERO_EXTEND_32_64(rhs)) {
-            testl_ir(rhs, lhs);
-            return;
-        }
-        spew("testq      $0x%" PRIx64 ", %s", int64_t(rhs), GPReg64Name(lhs));
-        if (lhs == rax)
-            m_formatter.oneByteOp64(OP_TEST_EAXIv);
-        else
-            m_formatter.oneByteOp64(OP_GROUP3_EvIz, lhs, GROUP3_OP_TEST);
-        m_formatter.immediate32(rhs);
-    }
-
-    void testq_i32m(int32_t rhs, int32_t offset, RegisterID base)
-    {
-        spew("testq      $0x%" PRIx64 ", " MEM_ob, int64_t(rhs), ADDR_ob(offset, base));
-        m_formatter.oneByteOp64(OP_GROUP3_EvIz, offset, base, GROUP3_OP_TEST);
-        m_formatter.immediate32(rhs);
-    }
-
-    void testq_i32m(int32_t rhs, int32_t offset, RegisterID base, RegisterID index, int scale)
-    {
-        spew("testq      $0x%4x, " MEM_obs, rhs, ADDR_obs(offset, base, index, scale));
-        m_formatter.oneByteOp64(OP_GROUP3_EvIz, offset, base, index, scale, GROUP3_OP_TEST);
-        m_formatter.immediate32(rhs);
-    }
-#endif
-
     void testw_rr(RegisterID rhs, RegisterID lhs)
     {
         spew("testw      %s, %s", GPReg16Name(rhs), GPReg16Name(lhs));
         m_formatter.prefix(PRE_OPERAND_SIZE);
         m_formatter.oneByteOp(OP_TEST_EvGv, lhs, rhs);
     }
 
     void testb_ir(int32_t rhs, RegisterID lhs)
@@ -2182,34 +1753,16 @@ public:
         m_formatter.oneByteOp(OP_XCHG_GvEv, offset, base, src);
     }
     void xchgl_rm(RegisterID src, int32_t offset, RegisterID base, RegisterID index, int scale)
     {
         spew("xchgl      %s, " MEM_obs, GPReg32Name(src), ADDR_obs(offset, base, index, scale));
         m_formatter.oneByteOp(OP_XCHG_GvEv, offset, base, index, scale, src);
     }
 
-#ifdef JS_CODEGEN_X64
-    void xchgq_rr(RegisterID src, RegisterID dst)
-    {
-        spew("xchgq      %s, %s", GPReg64Name(src), GPReg64Name(dst));
-        m_formatter.oneByteOp64(OP_XCHG_GvEv, src, dst);
-    }
-    void xchgq_rm(RegisterID src, int32_t offset, RegisterID base)
-    {
-        spew("xchgq      %s, " MEM_ob, GPReg64Name(src), ADDR_ob(offset, base));
-        m_formatter.oneByteOp64(OP_XCHG_GvEv, offset, base, src);
-    }
-    void xchgq_rm(RegisterID src, int32_t offset, RegisterID base, RegisterID index, int scale)
-    {
-        spew("xchgq      %s, " MEM_obs, GPReg64Name(src), ADDR_obs(offset, base, index, scale));
-        m_formatter.oneByteOp64(OP_XCHG_GvEv, offset, base, index, scale, src);
-    }
-#endif
-
     void movl_rr(RegisterID src, RegisterID dst)
     {
         spew("movl       %s, %s", GPReg32Name(src), GPReg32Name(dst));
         m_formatter.oneByteOp(OP_MOV_GvEv, src, dst);
     }
 
     void movw_rm(RegisterID src, int32_t offset, RegisterID base)
     {
@@ -2407,53 +1960,16 @@ public:
         m_formatter.oneByteOp(OP_MOV_OvEAX);
 #ifdef JS_CODEGEN_X64
         m_formatter.immediate64(reinterpret_cast<int64_t>(addr));
 #else
         m_formatter.immediate32(reinterpret_cast<int32_t>(addr));
 #endif
     }
 
-#ifdef JS_CODEGEN_X64
-    void movq_rr(RegisterID src, RegisterID dst)
-    {
-        spew("movq       %s, %s", GPReg64Name(src), GPReg64Name(dst));
-        m_formatter.oneByteOp64(OP_MOV_GvEv, src, dst);
-    }
-
-    void movq_rm(RegisterID src, int32_t offset, RegisterID base)
-    {
-        spew("movq       %s, " MEM_ob, GPReg64Name(src), ADDR_ob(offset, base));
-        m_formatter.oneByteOp64(OP_MOV_EvGv, offset, base, src);
-    }
-
-    void movq_rm_disp32(RegisterID src, int32_t offset, RegisterID base)
-    {
-        spew("movq       %s, " MEM_o32b, GPReg64Name(src), ADDR_o32b(offset, base));
-        m_formatter.oneByteOp64_disp32(OP_MOV_EvGv, offset, base, src);
-    }
-
-    void movq_rm(RegisterID src, int32_t offset, RegisterID base, RegisterID index, int scale)
-    {
-        spew("movq       %s, " MEM_obs, GPReg64Name(src), ADDR_obs(offset, base, index, scale));
-        m_formatter.oneByteOp64(OP_MOV_EvGv, offset, base, index, scale, src);
-    }
-
-    void movq_rm(RegisterID src, const void* addr)
-    {
-        if (src == rax && !IsAddressImmediate(addr)) {
-            movq_EAXm(addr);
-            return;
-        }
-
-        spew("movq       %s, %p", GPReg64Name(src), addr);
-        m_formatter.oneByteOp64(OP_MOV_EvGv, addr, src);
-    }
-#endif
-
     void vmovq_rm(XMMRegisterID src, int32_t offset, RegisterID base)
     {
         // vmovq_rm can be encoded either as a true vmovq or as a vmovd with a
         // REX prefix modifying it to be 64-bit. We choose the vmovq encoding
         // because it's smaller (when it doesn't need a REX prefix for other
         // reasons) and because it works on 32-bit x86 too.
         twoByteOpSimd("vmovq", VEX_PD, OP2_MOVQ_WdVd, offset, base, invalid_xmm, src);
     }
@@ -2468,71 +1984,16 @@ public:
         twoByteOpSimd("vmovq", VEX_PD, OP2_MOVQ_WdVd, offset, base, index, scale, invalid_xmm, src);
     }
 
     void vmovq_rm(XMMRegisterID src, const void* addr)
     {
         twoByteOpSimd("vmovq", VEX_PD, OP2_MOVQ_WdVd, addr, invalid_xmm, src);
     }
 
-#ifdef JS_CODEGEN_X64
-    void movq_mEAX(const void* addr)
-    {
-        if (IsAddressImmediate(addr)) {
-            movq_mr(addr, rax);
-            return;
-        }
-
-        spew("movq       %p, %%rax", addr);
-        m_formatter.oneByteOp64(OP_MOV_EAXOv);
-        m_formatter.immediate64(reinterpret_cast<int64_t>(addr));
-    }
-
-    void movq_EAXm(const void* addr)
-    {
-        if (IsAddressImmediate(addr)) {
-            movq_rm(rax, addr);
-            return;
-        }
-
-        spew("movq       %%rax, %p", addr);
-        m_formatter.oneByteOp64(OP_MOV_OvEAX);
-        m_formatter.immediate64(reinterpret_cast<int64_t>(addr));
-    }
-
-    void movq_mr(int32_t offset, RegisterID base, RegisterID dst)
-    {
-        spew("movq       " MEM_ob ", %s", ADDR_ob(offset, base), GPReg64Name(dst));
-        m_formatter.oneByteOp64(OP_MOV_GvEv, offset, base, dst);
-    }
-
-    void movq_mr_disp32(int32_t offset, RegisterID base, RegisterID dst)
-    {
-        spew("movq       " MEM_o32b ", %s", ADDR_o32b(offset, base), GPReg64Name(dst));
-        m_formatter.oneByteOp64_disp32(OP_MOV_GvEv, offset, base, dst);
-    }
-
-    void movq_mr(int32_t offset, RegisterID base, RegisterID index, int scale, RegisterID dst)
-    {
-        spew("movq       " MEM_obs ", %s", ADDR_obs(offset, base, index, scale), GPReg64Name(dst));
-        m_formatter.oneByteOp64(OP_MOV_GvEv, offset, base, index, scale, dst);
-    }
-
-    void movq_mr(const void* addr, RegisterID dst)
-    {
-        if (dst == rax && !IsAddressImmediate(addr)) {
-            movq_mEAX(addr);
-            return;
-        }
-
-        spew("movq       %p, %s", addr, GPReg64Name(dst));
-        m_formatter.oneByteOp64(OP_MOV_GvEv, addr, dst);
-    }
-#endif
-
     void vmovq_mr(int32_t offset, RegisterID base, XMMRegisterID dst)
     {
         // vmovq_mr can be encoded either as a true vmovq or as a vmovd with a
         // REX prefix modifying it to be 64-bit. We choose the vmovq encoding
         // because it's smaller (when it doesn't need a REX prefix for other
         // reasons) and because it works on 32-bit x86 too.
         twoByteOpSimd("vmovq", VEX_SS, OP2_MOVQ_VdWd, offset, base, invalid_xmm, dst);
     }
@@ -2547,105 +2008,16 @@ public:
         twoByteOpSimd("vmovq", VEX_SS, OP2_MOVQ_VdWd, offset, base, index, scale, invalid_xmm, dst);
     }
 
     void vmovq_mr(const void* addr, XMMRegisterID dst)
     {
         twoByteOpSimd("vmovq", VEX_SS, OP2_MOVQ_VdWd, addr, invalid_xmm, dst);
     }
 
-#ifdef JS_CODEGEN_X64
-    void leaq_mr(int32_t offset, RegisterID base, RegisterID index, int scale, RegisterID dst)
-    {
-        spew("leaq       " MEM_obs ", %s", ADDR_obs(offset, base, index, scale), GPReg64Name(dst)),
-        m_formatter.oneByteOp64(OP_LEA, offset, base, index, scale, dst);
-    }
-
-    void movq_i32m(int32_t imm, int32_t offset, RegisterID base)
-    {
-        spew("movq       $%d, " MEM_ob, imm, ADDR_ob(offset, base));
-        m_formatter.oneByteOp64(OP_GROUP11_EvIz, offset, base, GROUP11_MOV);
-        m_formatter.immediate32(imm);
-    }
-
-    void movq_i32m(int32_t imm, int32_t offset, RegisterID base, RegisterID index, int scale)
-    {
-        spew("movq       $%d, " MEM_obs, imm, ADDR_obs(offset, base, index, scale));
-        m_formatter.oneByteOp64(OP_GROUP11_EvIz, offset, base, index, scale, GROUP11_MOV);
-        m_formatter.immediate32(imm);
-    }
-    void movq_i32m(int32_t imm, const void* addr)
-    {
-        spew("movq       $%d, %p", imm, addr);
-        m_formatter.oneByteOp64(OP_GROUP11_EvIz, addr, GROUP11_MOV);
-        m_formatter.immediate32(imm);
-    }
-
-    // Note that this instruction sign-extends its 32-bit immediate field to 64
-    // bits and loads the 64-bit value into a 64-bit register.
-    //
-    // Note also that this is similar to the movl_i32r instruction, except that
-    // movl_i32r *zero*-extends its 32-bit immediate, and it has smaller code
-    // size, so it's preferred for values which could use either.
-    void movq_i32r(int32_t imm, RegisterID dst) {
-        spew("movq       $%d, %s", imm, GPRegName(dst));
-        m_formatter.oneByteOp64(OP_GROUP11_EvIz, dst, GROUP11_MOV);
-        m_formatter.immediate32(imm);
-    }
-
-    void movq_i64r(int64_t imm, RegisterID dst)
-    {
-        spew("movabsq    $0x%" PRIx64 ", %s", imm, GPReg64Name(dst));
-        m_formatter.oneByteOp64(OP_MOV_EAXIv, dst);
-        m_formatter.immediate64(imm);
-    }
-
-    void movslq_rr(RegisterID src, RegisterID dst)
-    {
-        spew("movslq     %s, %s", GPReg32Name(src), GPReg64Name(dst));
-        m_formatter.oneByteOp64(OP_MOVSXD_GvEv, src, dst);
-    }
-    void movslq_mr(int32_t offset, RegisterID base, RegisterID dst)
-    {
-        spew("movslq     " MEM_ob ", %s", ADDR_ob(offset, base), GPReg64Name(dst));
-        m_formatter.oneByteOp64(OP_MOVSXD_GvEv, offset, base, dst);
-    }
-    void movslq_mr(int32_t offset, RegisterID base, RegisterID index, int scale, RegisterID dst)
-    {
-        spew("movslq     " MEM_obs ", %s", ADDR_obs(offset, base, index, scale), GPReg64Name(dst));
-        m_formatter.oneByteOp64(OP_MOVSXD_GvEv, offset, base, index, scale, dst);
-    }
-
-    MOZ_WARN_UNUSED_RESULT JmpSrc
-    movl_ripr(RegisterID dst)
-    {
-        m_formatter.oneByteRipOp(OP_MOV_GvEv, 0, (RegisterID)dst);
-        JmpSrc label(m_formatter.size());
-        spew("movl       " MEM_o32r ", %s", ADDR_o32r(label.offset()), GPReg32Name(dst));
-        return label;
-    }
-
-    MOZ_WARN_UNUSED_RESULT JmpSrc
-    movl_rrip(RegisterID src)
-    {
-        m_formatter.oneByteRipOp(OP_MOV_EvGv, 0, (RegisterID)src);
-        JmpSrc label(m_formatter.size());
-        spew("movl       %s, " MEM_o32r "", GPReg32Name(src), ADDR_o32r(label.offset()));
-        return label;
-    }
-
-    MOZ_WARN_UNUSED_RESULT JmpSrc
-    movq_ripr(RegisterID dst)
-    {
-        m_formatter.oneByteRipOp64(OP_MOV_GvEv, 0, dst);
-        JmpSrc label(m_formatter.size());
-        spew("movq       " MEM_o32r ", %s", ADDR_o32r(label.offset()), GPRegName(dst));
-        return label;
-    }
-#endif
     void movl_rm(RegisterID src, const void* addr)
     {
         if (src == rax
 #ifdef JS_CODEGEN_X64
             && !IsAddressImmediate(addr)
 #endif
             ) {
             movl_EAXm(addr);
@@ -2825,32 +2197,16 @@ public:
         m_formatter.oneByteOp(OP_LEA, offset, base, index, scale, dst);
     }
 
     void leal_mr(int32_t offset, RegisterID base, RegisterID dst)
     {
         spew("leal       " MEM_ob ", %s", ADDR_ob(offset, base), GPReg32Name(dst));
         m_formatter.oneByteOp(OP_LEA, offset, base, dst);
     }
-#ifdef JS_CODEGEN_X64
-    void leaq_mr(int32_t offset, RegisterID base, RegisterID dst)
-    {
-        spew("leaq       " MEM_ob ", %s", ADDR_ob(offset, base), GPReg64Name(dst));
-        m_formatter.oneByteOp64(OP_LEA, offset, base, dst);
-    }
-
-    MOZ_WARN_UNUSED_RESULT JmpSrc
-    leaq_rip(RegisterID dst)
-    {
-        m_formatter.oneByteRipOp64(OP_LEA, 0, dst);
-        JmpSrc label(m_formatter.size());
-        spew("leaq       " MEM_o32r ", %s", ADDR_o32r(label.offset()), GPRegName(dst));
-        return label;
-    }
-#endif
 
     // Flow control:
 
     MOZ_WARN_UNUSED_RESULT JmpSrc
     call()
     {
         m_formatter.oneByteOp(OP_CALL_rel32);
         JmpSrc r = m_formatter.immediateRel32();
@@ -2919,30 +2275,16 @@ public:
         m_formatter.oneByteOp(OP_GROUP5_Ev, offset, base, GROUP5_OP_JMPN);
     }
 
     void jmp_m(int32_t offset, RegisterID base, RegisterID index, int scale) {
         spew("jmp        *" MEM_obs, ADDR_obs(offset, base, index, scale));
         m_formatter.oneByteOp(OP_GROUP5_Ev, offset, base, index, scale, GROUP5_OP_JMPN);
     }
 
-#ifdef JS_CODEGEN_X64
-    void jmp_rip(int ripOffset) {
-        // rip-relative addressing.
-        spew("jmp        *%d(%%rip)", ripOffset);
-        m_formatter.oneByteRipOp(OP_GROUP5_Ev, ripOffset, GROUP5_OP_JMPN);
-    }
-
-    void immediate64(int64_t imm)
-    {
-        spew(".quad      %lld", (long long)imm);
-        m_formatter.immediate64(imm);
-    }
-#endif
-
     void jCC_i(Condition cond, JmpDst dst)
     {
         int32_t diff = dst.offset() - m_formatter.size();
         spew("j%s        .Llabel%d", CCName(cond), dst.offset());
 
         // The jump immediate is an offset from the end of the jump instruction.
         // A conditional jump instruction is either 1 byte opcode and 1 byte
         // offset, or 2 bytes opcode and 4 bytes offset.
@@ -3094,27 +2436,16 @@ public:
         twoByteOpSimd("vcvttps2dq", VEX_SS, OP2_CVTTPS2DQ_VdqWps, src, invalid_xmm, dst);
     }
 
     void vcvtdq2ps_rr(XMMRegisterID src, XMMRegisterID dst)
     {
         twoByteOpSimd("vcvtdq2ps", VEX_PS, OP2_CVTDQ2PS_VpsWdq, src, invalid_xmm, dst);
     }
 
-#ifdef JS_CODEGEN_X64
-    void vcvtsq2sd_rr(RegisterID src1, XMMRegisterID src0, XMMRegisterID dst)
-    {
-        twoByteOpInt64Simd("vcvtsi2sd", VEX_SD, OP2_CVTSI2SD_VsdEd, src1, src0, dst);
-    }
-    void vcvtsq2ss_rr(RegisterID src1, XMMRegisterID src0, XMMRegisterID dst)
-    {
-        twoByteOpInt64Simd("vcvtsi2ss", VEX_SS, OP2_CVTSI2SD_VsdEd, src1, src0, dst);
-    }
-#endif
-
     void vcvtsi2sd_mr(int32_t offset, RegisterID base, XMMRegisterID src0, XMMRegisterID dst)
     {
         twoByteOpSimd("vcvtsi2sd", VEX_SD, OP2_CVTSI2SD_VsdEd, offset, base, src0, dst);
     }
 
     void vcvtsi2sd_mr(int32_t offset, RegisterID base, RegisterID index, int scale, XMMRegisterID src0, XMMRegisterID dst)
     {
         twoByteOpSimd("vcvtsi2sd", VEX_SD, OP2_CVTSI2SD_VsdEd, offset, base, index, scale, src0, dst);
@@ -3125,52 +2456,26 @@ public:
         twoByteOpSimd("vcvtsi2ss", VEX_SS, OP2_CVTSI2SD_VsdEd, offset, base, src0, dst);
     }
 
     void vcvtsi2ss_mr(int32_t offset, RegisterID base, RegisterID index, int scale, XMMRegisterID src0, XMMRegisterID dst)
     {
         twoByteOpSimd("vcvtsi2ss", VEX_SS, OP2_CVTSI2SD_VsdEd, offset, base, index, scale, src0, dst);
     }
 
-#ifdef JS_CODEGEN_X86
-    void vcvtsi2sd_mr(const void* address, XMMRegisterID src0, XMMRegisterID dst)
-    {
-        twoByteOpSimd("vcvtsi2sd", VEX_SD, OP2_CVTSI2SD_VsdEd, address, src0, dst);
-    }
-#endif
-
-#ifdef JS_CODEGEN_X64
-    void vcvtsi2sdq_rr(RegisterID src, XMMRegisterID dst)
-    {
-        twoByteOpInt64Simd("vcvtsi2sdq", VEX_SD, OP2_CVTSI2SD_VsdEd, src, invalid_xmm, dst);
-    }
-#endif
-
     void vcvttsd2si_rr(XMMRegisterID src, RegisterID dst)
     {
         twoByteOpSimdInt32("vcvttsd2si", VEX_SD, OP2_CVTTSD2SI_GdWsd, src, dst);
     }
 
     void vcvttss2si_rr(XMMRegisterID src, RegisterID dst)
     {
         twoByteOpSimdInt32("vcvttss2si", VEX_SS, OP2_CVTTSD2SI_GdWsd, src, dst);
     }
 
-#ifdef JS_CODEGEN_X64
-    void vcvttsd2sq_rr(XMMRegisterID src, RegisterID dst)
-    {
-        twoByteOpSimdInt64("vcvttsd2si", VEX_SD, OP2_CVTTSD2SI_GdWsd, src, dst);
-    }
-
-    void vcvttss2sq_rr(XMMRegisterID src, RegisterID dst)
-    {
-        twoByteOpSimdInt64("vcvttss2si", VEX_SS, OP2_CVTTSD2SI_GdWsd, src, dst);
-    }
-#endif
-
     void vunpcklps_rr(XMMRegisterID src1, XMMRegisterID src0, XMMRegisterID dst)
     {
         twoByteOpSimd("vunpcklps", VEX_PS, OP2_UNPCKLPS_VsdWsd, src1, src0, dst);
     }
     void vunpcklps_mr(int32_t offset, RegisterID base, XMMRegisterID src0, XMMRegisterID dst)
     {
         twoByteOpSimd("vunpcklps", VEX_PS, OP2_UNPCKLPS_VsdWsd, offset, base, src0, dst);
     }
@@ -3392,32 +2697,16 @@ public:
         twoByteOpSimd_disp32("vmovd", VEX_PD, OP2_MOVD_EdVd, offset, base, invalid_xmm, src);
     }
 
     void vmovd_rm(XMMRegisterID src, const void* address)
     {
         twoByteOpSimd("vmovd", VEX_PD, OP2_MOVD_EdVd, address, invalid_xmm, src);
     }
 
-#ifdef JS_CODEGEN_X64
-    void vmovq_rr(XMMRegisterID src, RegisterID dst)
-    {
-        // While this is called "vmovq", it actually uses the vmovd encoding
-        // with a REX prefix modifying it to be 64-bit.
-        twoByteOpSimdInt64("vmovq", VEX_PD, OP2_MOVD_EdVd, (XMMRegisterID)dst, (RegisterID)src);
-    }
-
-    void vmovq_rr(RegisterID src, XMMRegisterID dst)
-    {
-        // While this is called "vmovq", it actually uses the vmovd encoding
-        // with a REX prefix modifying it to be 64-bit.
-        twoByteOpInt64Simd("vmovq", VEX_PD, OP2_MOVD_VdEd, src, invalid_xmm, dst);
-    }
-#endif
-
     void vmovsd_rm(XMMRegisterID src, int32_t offset, RegisterID base)
     {
         twoByteOpSimd("vmovsd", VEX_SD, OP2_MOVSD_WsdVsd, offset, base, invalid_xmm, src);
     }
 
     void vmovsd_rm_disp32(XMMRegisterID src, int32_t offset, RegisterID base)
     {
         twoByteOpSimd_disp32("vmovsd", VEX_SD, OP2_MOVSD_WsdVsd, offset, base, invalid_xmm, src);
@@ -3532,48 +2821,16 @@ public:
     {
         twoByteOpSimd("vmovdqu", VEX_SS, OP2_MOVDQ_WdqVdq, address, invalid_xmm, src);
     }
 
     void vmovups_rm(XMMRegisterID src, const void* address)
     {
         twoByteOpSimd("vmovups", VEX_PS, OP2_MOVPS_WpsVps, address, invalid_xmm, src);
     }
-#ifdef JS_CODEGEN_X64
-    MOZ_WARN_UNUSED_RESULT JmpSrc
-    vmovsd_ripr(XMMRegisterID dst)
-    {
-        return twoByteRipOpSimd("vmovsd", VEX_SD, OP2_MOVSD_VsdWsd, invalid_xmm, dst);
-    }
-    MOZ_WARN_UNUSED_RESULT JmpSrc
-    vmovss_ripr(XMMRegisterID dst)
-    {
-        return twoByteRipOpSimd("vmovss", VEX_SS, OP2_MOVSD_VsdWsd, invalid_xmm, dst);
-    }
-    MOZ_WARN_UNUSED_RESULT JmpSrc
-    vmovsd_rrip(XMMRegisterID src)
-    {
-        return twoByteRipOpSimd("vmovsd", VEX_SD, OP2_MOVSD_WsdVsd, invalid_xmm, src);
-    }
-    MOZ_WARN_UNUSED_RESULT JmpSrc
-    vmovss_rrip(XMMRegisterID src)
-    {
-        return twoByteRipOpSimd("vmovss", VEX_SS, OP2_MOVSD_WsdVsd, invalid_xmm, src);
-    }
-    MOZ_WARN_UNUSED_RESULT JmpSrc
-    vmovdqa_rrip(XMMRegisterID src)
-    {
-        return twoByteRipOpSimd("vmovdqa", VEX_PD, OP2_MOVDQ_WdqVdq, invalid_xmm, src);
-    }
-    MOZ_WARN_UNUSED_RESULT JmpSrc
-    vmovaps_rrip(XMMRegisterID src)
-    {
-        return twoByteRipOpSimd("vmovdqa", VEX_PS, OP2_MOVAPS_WsdVsd, invalid_xmm, src);
-    }
-#endif
 
     void vmovaps_rr(XMMRegisterID src, XMMRegisterID dst)
     {
 #ifdef JS_CODEGEN_X64
         // There are two opcodes that can encode this instruction. If we have
         // one register in [xmm8,xmm15] and one in [xmm0,xmm7], use the
         // opcode which swaps the operands, as that way we can get a two-byte
         // VEX in that case.
@@ -3636,40 +2893,16 @@ public:
         if (src >= xmm8 && dst < xmm8) {
             twoByteOpSimd("vmovapd", VEX_PD, OP2_MOVAPS_WsdVsd, dst, invalid_xmm, src);
             return;
         }
 #endif
         twoByteOpSimd("vmovapd", VEX_PD, OP2_MOVAPD_VsdWsd, src, invalid_xmm, dst);
     }
 
-#ifdef JS_CODEGEN_X64
-    MOZ_WARN_UNUSED_RESULT JmpSrc
-    vmovaps_ripr(XMMRegisterID dst)
-    {
-        return twoByteRipOpSimd("vmovaps", VEX_PS, OP2_MOVAPS_VsdWsd, invalid_xmm, dst);
-    }
-
-    MOZ_WARN_UNUSED_RESULT JmpSrc
-    vmovdqa_ripr(XMMRegisterID dst)
-    {
-        return twoByteRipOpSimd("vmovdqa", VEX_PD, OP2_MOVDQ_VdqWdq, invalid_xmm, dst);
-    }
-#else
-    void vmovaps_mr(const void* address, XMMRegisterID dst)
-    {
-        twoByteOpSimd("vmovaps", VEX_PS, OP2_MOVAPS_VsdWsd, address, invalid_xmm, dst);
-    }
-
-    void vmovdqa_mr(const void* address, XMMRegisterID dst)
-    {
-        twoByteOpSimd("vmovdqa", VEX_PD, OP2_MOVDQ_VdqWdq, address, invalid_xmm, dst);
-    }
-#endif // JS_CODEGEN_X64
-
     void vmovdqu_rm(XMMRegisterID src, int32_t offset, RegisterID base)
     {
         twoByteOpSimd("vmovdqu", VEX_SS, OP2_MOVDQ_WdqVdq, offset, base, invalid_xmm, src);
     }
 
     void vmovdqu_rm_disp32(XMMRegisterID src, int32_t offset, RegisterID base)
     {
         twoByteOpSimd_disp32("vmovdqu", VEX_SS, OP2_MOVDQ_WdqVdq, offset, base, invalid_xmm, src);
@@ -4032,30 +3265,16 @@ threeByteOpImmSimd("vblendps", VEX_PD, O
 
     void ret_i(int32_t imm)
     {
         spew("ret        $%d", imm);
         m_formatter.oneByteOp(OP_RET_Iz);
         m_formatter.immediate16u(imm);
     }
 
-#ifdef JS_CODEGEN_X86
-    void pusha()
-    {
-        spew("pusha");
-        m_formatter.oneByteOp(OP_PUSHA);
-    }
-
-    void popa()
-    {
-        spew("popa");
-        m_formatter.oneByteOp(OP_POPA);
-    }
-#endif
-
     void mfence() {
         spew("mfence");
         m_formatter.twoByteOp(OP_FENCE, (RegisterID)0, 6);
     }
 
     // Assembler admin methods:
 
     JmpDst label()
@@ -4189,17 +3408,17 @@ threeByteOpImmSimd("vblendps", VEX_PD, O
         SetRel32(code + from.offset(), code + to.offset());
     }
 
     void executableCopy(void* buffer)
     {
         memcpy(buffer, m_formatter.buffer(), size());
     }
 
-  private:
+  protected:
     static bool CAN_SIGN_EXTEND_8_32(int32_t value) { return value == (int32_t)(int8_t)value; }
     static bool CAN_SIGN_EXTEND_16_32(int32_t value) { return value == (int32_t)(int16_t)value; }
     static bool CAN_ZERO_EXTEND_8_32(int32_t value) { return value == (int32_t)(uint8_t)value; }
     static bool CAN_ZERO_EXTEND_8H_32(int32_t value) { return value == (value & 0xff00); }
     static bool CAN_ZERO_EXTEND_16_32(int32_t value) { return value == (int32_t)(uint16_t)value; }
     static bool CAN_ZERO_EXTEND_32_64(int32_t value) { return value >= 0; }
 
     // Methods for encoding SIMD instructions via either legacy SSE encoding or
@@ -4245,46 +3464,16 @@ threeByteOpImmSimd("vblendps", VEX_PD, O
     }
 
     const char* legacySSEOpName(const char* name)
     {
         MOZ_ASSERT(name[0] == 'v');
         return name + 1;
     }
 
- #ifdef JS_CODEGEN_X64
-    MOZ_WARN_UNUSED_RESULT JmpSrc
-    twoByteRipOpSimd(const char* name, VexOperandType ty, TwoByteOpcodeID opcode,
-                     XMMRegisterID src0, XMMRegisterID dst)
-    {
-        if (useLegacySSEEncoding(src0, dst)) {
-            m_formatter.legacySSEPrefix(ty);
-            m_formatter.twoByteRipOp(opcode, 0, dst);
-            JmpSrc label(m_formatter.size());
-            if (IsXMMReversedOperands(opcode))
-                spew("%-11s%s, " MEM_o32r "", legacySSEOpName(name), XMMRegName(dst), ADDR_o32r(label.offset()));
-            else
-                spew("%-11s" MEM_o32r ", %s", legacySSEOpName(name), ADDR_o32r(label.offset()), XMMRegName(dst));
-            return label;
-        }
-
-        m_formatter.twoByteRipOpVex(ty, opcode, 0, src0, dst);
-        JmpSrc label(m_formatter.size());
-        if (src0 == invalid_xmm) {
-            if (IsXMMReversedOperands(opcode))
-                spew("%-11s%s, " MEM_o32r "", name, XMMRegName(dst), ADDR_o32r(label.offset()));
-            else
-                spew("%-11s" MEM_o32r ", %s", name, ADDR_o32r(label.offset()), XMMRegName(dst));
-        } else {
-            spew("%-11s" MEM_o32r ", %s, %s", name, ADDR_o32r(label.offset()), XMMRegName(src0), XMMRegName(dst));
-        }
-        return label;
-    }
-#endif
-
     void twoByteOpSimd(const char* name, VexOperandType ty, TwoByteOpcodeID opcode,
                        XMMRegisterID rm, XMMRegisterID src0, XMMRegisterID dst)
     {
         if (useLegacySSEEncoding(src0, dst)) {
             if (IsXMMReversedOperands(opcode))
                 spew("%-11s%s, %s", legacySSEOpName(name), XMMRegName(dst), XMMRegName(rm));
             else
                 spew("%-11s%s, %s", legacySSEOpName(name), XMMRegName(rm), XMMRegName(dst));
@@ -4485,42 +3674,16 @@ threeByteOpImmSimd("vblendps", VEX_PD, O
             else
                 spew("%-11s%s, %s", name, GPReg32Name(rm), XMMRegName(dst));
         } else {
             spew("%-11s%s, %s, %s", name, GPReg32Name(rm), XMMRegName(src0), XMMRegName(dst));
         }
         m_formatter.twoByteOpVex(ty, opcode, rm, src0, dst);
     }
 
-#ifdef JS_CODEGEN_X64
-    void twoByteOpInt64Simd(const char* name, VexOperandType ty, TwoByteOpcodeID opcode,
-                            RegisterID rm, XMMRegisterID src0, XMMRegisterID dst)
-    {
-        if (useLegacySSEEncoding(src0, dst)) {
-            if (IsXMMReversedOperands(opcode))
-                spew("%-11s%s, %s", legacySSEOpName(name), XMMRegName(dst), GPRegName(rm));
-            else
-                spew("%-11s%s, %s", legacySSEOpName(name), GPRegName(rm), XMMRegName(dst));
-            m_formatter.legacySSEPrefix(ty);
-            m_formatter.twoByteOp64(opcode, rm, dst);
-            return;
-        }
-
-        if (src0 == invalid_xmm) {
-            if (IsXMMReversedOperands(opcode))
-                spew("%-11s%s, %s", name, XMMRegName(dst), GPRegName(rm));
-            else
-                spew("%-11s%s, %s", name, GPRegName(rm), XMMRegName(dst));
-        } else {
-            spew("%-11s%s, %s, %s", name, GPRegName(rm), XMMRegName(src0), XMMRegName(dst));
-        }
-        m_formatter.twoByteOpVex64(ty, opcode, rm, src0, dst);
-    }
-#endif
-
     void twoByteOpSimdInt32(const char* name, VexOperandType ty, TwoByteOpcodeID opcode,
                             XMMRegisterID rm, RegisterID dst)
     {
         if (useLegacySSEEncodingForOtherOutput()) {
             if (IsXMMReversedOperands(opcode))
                 spew("%-11s%s, %s", legacySSEOpName(name), GPReg32Name(dst), XMMRegName(rm));
             else if (opcode == OP2_MOVD_EdVd)
                 spew("%-11s%s, %s", legacySSEOpName(name), XMMRegName((XMMRegisterID)dst), GPReg32Name((RegisterID)rm));
@@ -4551,42 +3714,16 @@ threeByteOpImmSimd("vblendps", VEX_PD, O
             return;
         }
 
         spew("%-11s$0x%x, %s, %s", name, imm, XMMRegName(rm), GPReg32Name(dst));
         m_formatter.twoByteOpVex(ty, opcode, (RegisterID)rm, invalid_xmm, dst);
         m_formatter.immediate8u(imm);
     }
 
-#ifdef JS_CODEGEN_X64
-    void twoByteOpSimdInt64(const char* name, VexOperandType ty, TwoByteOpcodeID opcode,
-                            XMMRegisterID rm, RegisterID dst)
-    {
-        if (useLegacySSEEncodingForOtherOutput()) {
-            if (IsXMMReversedOperands(opcode))
-                spew("%-11s%s, %s", legacySSEOpName(name), GPRegName(dst), XMMRegName(rm));
-            else if (opcode == OP2_MOVD_EdVd)
-                spew("%-11s%s, %s", legacySSEOpName(name), XMMRegName((XMMRegisterID)dst), GPRegName((RegisterID)rm));
-            else
-                spew("%-11s%s, %s", legacySSEOpName(name), XMMRegName(rm), GPRegName(dst));
-            m_formatter.legacySSEPrefix(ty);
-            m_formatter.twoByteOp64(opcode, (RegisterID)rm, dst);
-            return;
-        }
-
-        if (IsXMMReversedOperands(opcode))
-            spew("%-11s%s, %s", name, GPRegName(dst), XMMRegName(rm));
-        else if (opcode == OP2_MOVD_EdVd)
-            spew("%-11s%s, %s", name, XMMRegName((XMMRegisterID)dst), GPRegName((RegisterID)rm));
-        else
-            spew("%-11s%s, %s", name, XMMRegName(rm), GPRegName(dst));
-        m_formatter.twoByteOpVex64(ty, opcode, (RegisterID)rm, invalid_xmm, (XMMRegisterID)dst);
-    }
-#endif
-
     void twoByteOpSimdFlags(const char* name, VexOperandType ty, TwoByteOpcodeID opcode,
                             XMMRegisterID rm, XMMRegisterID reg)
     {
         if (useLegacySSEEncodingForOtherOutput()) {
             spew("%-11s%s, %s", legacySSEOpName(name), XMMRegName(rm), XMMRegName(reg));
             m_formatter.legacySSEPrefix(ty);
             m_formatter.twoByteOp(opcode, (RegisterID)rm, reg);
             return;
new file mode 100644
--- /dev/null
+++ b/js/src/jit/x86/BaseAssembler-x86.h
@@ -0,0 +1,116 @@
+/* -*- Mode: C++; tab-width: 8; indent-tabs-mode: nil; c-basic-offset: 4 -*-
+ * vim: set ts=8 sts=4 et sw=4 tw=99:
+ * This Source Code Form is subject to the terms of the Mozilla Public
+ * License, v. 2.0. If a copy of the MPL was not distributed with this
+ * file, You can obtain one at http://mozilla.org/MPL/2.0/. */
+
+#ifndef jit_x86_BaseAssembler_x86_h
+#define jit_x86_BaseAssembler_x86_h
+
+#include "jit/x86-shared/BaseAssembler-x86-shared.h"
+
+namespace js {
+namespace jit {
+
+namespace X86Encoding {
+
+class BaseAssemblerX86 : public BaseAssembler
+{
+  public:
+
+    // Arithmetic operations:
+
+    void adcl_im(int32_t imm, const void* addr)
+    {
+        spew("adcl       %d, %p", imm, addr);
+        if (CAN_SIGN_EXTEND_8_32(imm)) {
+            m_formatter.oneByteOp(OP_GROUP1_EvIb, addr, GROUP1_OP_ADC);
+            m_formatter.immediate8s(imm);
+        } else {
+            m_formatter.oneByteOp(OP_GROUP1_EvIz, addr, GROUP1_OP_ADC);
+            m_formatter.immediate32(imm);
+        }
+    }
+
+    using BaseAssembler::andl_im;
+    void andl_im(int32_t imm, const void* addr)
+    {
+        spew("andl       $0x%x, %p", imm, addr);
+        if (CAN_SIGN_EXTEND_8_32(imm)) {
+            m_formatter.oneByteOp(OP_GROUP1_EvIb, addr, GROUP1_OP_AND);
+            m_formatter.immediate8s(imm);
+        } else {
+            m_formatter.oneByteOp(OP_GROUP1_EvIz, addr, GROUP1_OP_AND);
+            m_formatter.immediate32(imm);
+        }
+    }
+
+    using BaseAssembler::orl_im;
+    void orl_im(int32_t imm, const void* addr)
+    {
+        spew("orl        $0x%x, %p", imm, addr);
+        if (CAN_SIGN_EXTEND_8_32(imm)) {
+            m_formatter.oneByteOp(OP_GROUP1_EvIb, addr, GROUP1_OP_OR);
+            m_formatter.immediate8s(imm);
+        } else {
+            m_formatter.oneByteOp(OP_GROUP1_EvIz, addr, GROUP1_OP_OR);
+            m_formatter.immediate32(imm);
+        }
+    }
+
+    using BaseAssembler::subl_im;
+    void subl_im(int32_t imm, const void* addr)
+    {
+        spew("subl       $%d, %p", imm, addr);
+        if (CAN_SIGN_EXTEND_8_32(imm)) {
+            m_formatter.oneByteOp(OP_GROUP1_EvIb, addr, GROUP1_OP_SUB);
+            m_formatter.immediate8s(imm);
+        } else {
+            m_formatter.oneByteOp(OP_GROUP1_EvIz, addr, GROUP1_OP_SUB);
+            m_formatter.immediate32(imm);
+        }
+    }
+
+    // SSE operations:
+
+    using BaseAssembler::vcvtsi2sd_mr;
+    void vcvtsi2sd_mr(const void* address, XMMRegisterID src0, XMMRegisterID dst)
+    {
+        twoByteOpSimd("vcvtsi2sd", VEX_SD, OP2_CVTSI2SD_VsdEd, address, src0, dst);
+    }
+
+    using BaseAssembler::vmovaps_mr;
+    void vmovaps_mr(const void* address, XMMRegisterID dst)
+    {
+        twoByteOpSimd("vmovaps", VEX_PS, OP2_MOVAPS_VsdWsd, address, invalid_xmm, dst);
+    }
+
+    using BaseAssembler::vmovdqa_mr;
+    void vmovdqa_mr(const void* address, XMMRegisterID dst)
+    {
+        twoByteOpSimd("vmovdqa", VEX_PD, OP2_MOVDQ_VdqWdq, address, invalid_xmm, dst);
+    }
+
+    // Misc instructions:
+
+    void pusha()
+    {
+        spew("pusha");
+        m_formatter.oneByteOp(OP_PUSHA);
+    }
+
+    void popa()
+    {
+        spew("popa");
+        m_formatter.oneByteOp(OP_POPA);
+    }
+};
+
+typedef BaseAssemblerX86 BaseAssemblerSpecific;
+
+} // namespace X86Encoding
+
+} // namespace jit
+} // namespace js
+
+#endif /* jit_x86_BaseAssembler_x86_h */