Bug 1012232 - Only use the perf opcode on mips arches that support it. r=jesup, a=NPOTB
authorMike Hommey <mh+mozilla@glandium.org>
Tue, 20 May 2014 08:48:35 +0900
changeset 192328 26ba0b7f24ef
parent 192327 e8aaa68f8cb8
child 192329 b71dce806994
child 192331 693f57a7f0d9
child 192333 8b801635d8ce
push id3568
push userryanvm@gmail.com
push date2014-05-20 16:00 +0000
Treeherderresults
reviewersjesup, NPOTB
bugs1012232
milestone30.0
Bug 1012232 - Only use the perf opcode on mips arches that support it. r=jesup, a=NPOTB
media/libyuv/source/row_mips.cc
--- a/media/libyuv/source/row_mips.cc
+++ b/media/libyuv/source/row_mips.cc
@@ -13,16 +13,22 @@
 #ifdef __cplusplus
 namespace libyuv {
 extern "C" {
 #endif
 
 // The following are available on Mips platforms:
 #if !defined(LIBYUV_DISABLE_MIPS) && defined(__mips__)
 
+#include <sgidefs.h>
+
+#if (_MIPS_ISA == _MIPS_ISA_MIPS4) || (_MIPS_ISA == _MIPS_ISA_MIPS5)
+#define HAS_MIPS_PREFETCH 1
+#endif
+
 #ifdef HAS_COPYROW_MIPS
 void CopyRow_MIPS(const uint8* src, uint8* dst, int count) {
   __asm__ __volatile__ (
     ".set      noreorder                         \n"
     ".set      noat                              \n"
     "slti      $at, %[count], 8                  \n"
     "bne       $at ,$zero, $last8                \n"
     "xor       $t8, %[src], %[dst]               \n"
@@ -55,62 +61,76 @@ void CopyRow_MIPS(const uint8* src, uint
     // t0 is the "past the end" address
 
     // When in the loop we exercise "pref 30,x(a1)", the a1+x should not be past
     // the "t0-32" address
     // This means: for x=128 the last "safe" a1 address is "t0-160"
     // Alternatively, for x=64 the last "safe" a1 address is "t0-96"
     // we will use "pref 30,128(a1)", so "t0-160" is the limit
     "subu      $t9, $t0, 160                     \n"
+#ifdef HAS_MIPS_PREFETCH
     // t9 is the "last safe pref 30,128(a1)" address
     "pref      0, 0(%[src])                      \n"  // first line of src
     "pref      0, 32(%[src])                     \n"  // second line of src
     "pref      0, 64(%[src])                     \n"
     "pref      30, 32(%[dst])                    \n"
+#endif
     // In case the a1 > t9 don't use "pref 30" at all
     "sgtu      $v1, %[dst], $t9                  \n"
     "bgtz      $v1, $loop16w                     \n"
     "nop                                         \n"
     // otherwise, start with using pref30
+#ifdef HAS_MIPS_PREFETCH
     "pref      30, 64(%[dst])                    \n"
+#endif
     "$loop16w:                                    \n"
+#ifdef HAS_MIPS_PREFETCH
     "pref      0, 96(%[src])                     \n"
+#endif
     "lw        $t0, 0(%[src])                    \n"
     "bgtz      $v1, $skip_pref30_96              \n"  // skip
     "lw        $t1, 4(%[src])                    \n"
+#ifdef HAS_MIPS_PREFETCH
     "pref      30, 96(%[dst])                    \n"  // continue
+#endif
     "$skip_pref30_96:                            \n"
     "lw        $t2, 8(%[src])                    \n"
     "lw        $t3, 12(%[src])                   \n"
     "lw        $t4, 16(%[src])                   \n"
     "lw        $t5, 20(%[src])                   \n"
     "lw        $t6, 24(%[src])                   \n"
     "lw        $t7, 28(%[src])                   \n"
+#ifdef HAS_MIPS_PREFETCH
     "pref      0, 128(%[src])                    \n"
+#endif
     //  bring the next lines of src, addr 128
     "sw        $t0, 0(%[dst])                    \n"
     "sw        $t1, 4(%[dst])                    \n"
     "sw        $t2, 8(%[dst])                    \n"
     "sw        $t3, 12(%[dst])                   \n"
     "sw        $t4, 16(%[dst])                   \n"
     "sw        $t5, 20(%[dst])                   \n"
     "sw        $t6, 24(%[dst])                   \n"
     "sw        $t7, 28(%[dst])                   \n"
     "lw        $t0, 32(%[src])                   \n"
     "bgtz      $v1, $skip_pref30_128             \n"  // skip pref 30,128(a1)
     "lw        $t1, 36(%[src])                   \n"
+#ifdef HAS_MIPS_PREFETCH
     "pref      30, 128(%[dst])                   \n"  // set dest, addr 128
+#endif
     "$skip_pref30_128:                           \n"
     "lw        $t2, 40(%[src])                   \n"
     "lw        $t3, 44(%[src])                   \n"
     "lw        $t4, 48(%[src])                   \n"
     "lw        $t5, 52(%[src])                   \n"
     "lw        $t6, 56(%[src])                   \n"
     "lw        $t7, 60(%[src])                   \n"
+#ifdef HAS_MIPS_PREFETCH
     "pref      0, 160(%[src])                    \n"
+#endif
     // bring the next lines of src, addr 160
     "sw        $t0, 32(%[dst])                   \n"
     "sw        $t1, 36(%[dst])                   \n"
     "sw        $t2, 40(%[dst])                   \n"
     "sw        $t3, 44(%[dst])                   \n"
     "sw        $t4, 48(%[dst])                   \n"
     "sw        $t5, 52(%[dst])                   \n"
     "sw        $t6, 56(%[dst])                   \n"
@@ -120,17 +140,19 @@ void CopyRow_MIPS(const uint8* src, uint
     "sgtu      $v1, %[dst], $t9                  \n"
     "bne       %[dst], $a3, $loop16w             \n"
     " addiu    %[src], %[src], 64                \n"  // adding 64 to src
     "move      %[count], $t8                     \n"
 
     // Here we have src and dest word-aligned but less than 64-bytes to go
 
     "chk8w:                                      \n"
+#ifdef HAS_MIPS_PREFETCH
     "pref      0, 0x0(%[src])                    \n"
+#endif
     "andi      $t8, %[count], 0x1f               \n"  // 32-byte chunk?
     // the t8 is the reminder count past 32-bytes
     "beq       %[count], $t8, chk1w              \n"
     // count=t8,no 32-byte chunk
     " nop                                        \n"
 
     "lw        $t0, 0(%[src])                    \n"
     "lw        $t1, 4(%[src])                    \n"
@@ -208,82 +230,96 @@ void CopyRow_MIPS(const uint8* src, uint
     // There will be at most 1 32-byte chunk after it
     "subu      $a3, %[count], $t8                \n"  // the reminder
     // Here a3 counts bytes in 16w chunks
     "addu      $a3, %[dst], $a3                  \n"
     // Now a3 is the final dst after 64-byte chunks
     "addu      $t0, %[dst], %[count]             \n"  // t0 "past the end"
     "subu      $t9, $t0, 160                     \n"
     // t9 is the "last safe pref 30,128(a1)" address
+#ifdef HAS_MIPS_PREFETCH
     "pref      0, 0(%[src])                      \n"  // first line of src
     "pref      0, 32(%[src])                     \n"  // second line  addr 32
     "pref      0, 64(%[src])                     \n"
     "pref      30, 32(%[dst])                    \n"
+#endif
     // safe, as we have at least 64 bytes ahead
     // In case the a1 > t9 don't use "pref 30" at all
     "sgtu      $v1, %[dst], $t9                  \n"
     "bgtz      $v1, $ua_loop16w                  \n"
     // skip "pref 30,64(a1)" for too short arrays
     " nop                                        \n"
     // otherwise, start with using pref30
+#ifdef HAS_MIPS_PREFETCH
     "pref      30, 64(%[dst])                    \n"
+#endif
     "$ua_loop16w:                                \n"
+#ifdef HAS_MIPS_PREFETCH
     "pref      0, 96(%[src])                     \n"
+#endif
     "lwr       $t0, 0(%[src])                    \n"
     "lwl       $t0, 3(%[src])                    \n"
     "lwr       $t1, 4(%[src])                    \n"
     "bgtz      $v1, $ua_skip_pref30_96           \n"
     " lwl      $t1, 7(%[src])                    \n"
+#ifdef HAS_MIPS_PREFETCH
     "pref      30, 96(%[dst])                    \n"
+#endif
     // continue setting up the dest, addr 96
     "$ua_skip_pref30_96:                         \n"
     "lwr       $t2, 8(%[src])                    \n"
     "lwl       $t2, 11(%[src])                   \n"
     "lwr       $t3, 12(%[src])                   \n"
     "lwl       $t3, 15(%[src])                   \n"
     "lwr       $t4, 16(%[src])                   \n"
     "lwl       $t4, 19(%[src])                   \n"
     "lwr       $t5, 20(%[src])                   \n"
     "lwl       $t5, 23(%[src])                   \n"
     "lwr       $t6, 24(%[src])                   \n"
     "lwl       $t6, 27(%[src])                   \n"
     "lwr       $t7, 28(%[src])                   \n"
     "lwl       $t7, 31(%[src])                   \n"
+#ifdef HAS_MIPS_PREFETCH
     "pref      0, 128(%[src])                    \n"
+#endif
     // bring the next lines of src, addr 128
     "sw        $t0, 0(%[dst])                    \n"
     "sw        $t1, 4(%[dst])                    \n"
     "sw        $t2, 8(%[dst])                    \n"
     "sw        $t3, 12(%[dst])                   \n"
     "sw        $t4, 16(%[dst])                   \n"
     "sw        $t5, 20(%[dst])                   \n"
     "sw        $t6, 24(%[dst])                   \n"
     "sw        $t7, 28(%[dst])                   \n"
     "lwr       $t0, 32(%[src])                   \n"
     "lwl       $t0, 35(%[src])                   \n"
     "lwr       $t1, 36(%[src])                   \n"
     "bgtz      $v1, ua_skip_pref30_128           \n"
     " lwl      $t1, 39(%[src])                   \n"
+#ifdef HAS_MIPS_PREFETCH
     "pref      30, 128(%[dst])                   \n"
+#endif
     // continue setting up the dest, addr 128
     "ua_skip_pref30_128:                         \n"
 
     "lwr       $t2, 40(%[src])                   \n"
     "lwl       $t2, 43(%[src])                   \n"
     "lwr       $t3, 44(%[src])                   \n"
     "lwl       $t3, 47(%[src])                   \n"
     "lwr       $t4, 48(%[src])                   \n"
     "lwl       $t4, 51(%[src])                   \n"
     "lwr       $t5, 52(%[src])                   \n"
     "lwl       $t5, 55(%[src])                   \n"
     "lwr       $t6, 56(%[src])                   \n"
     "lwl       $t6, 59(%[src])                   \n"
     "lwr       $t7, 60(%[src])                   \n"
     "lwl       $t7, 63(%[src])                   \n"
+#ifdef HAS_MIPS_PREFETCH
     "pref      0, 160(%[src])                    \n"
+#endif
     // bring the next lines of src, addr 160
     "sw        $t0, 32(%[dst])                   \n"
     "sw        $t1, 36(%[dst])                   \n"
     "sw        $t2, 40(%[dst])                   \n"
     "sw        $t3, 44(%[dst])                   \n"
     "sw        $t4, 48(%[dst])                   \n"
     "sw        $t5, 52(%[dst])                   \n"
     "sw        $t6, 56(%[dst])                   \n"
@@ -293,17 +329,19 @@ void CopyRow_MIPS(const uint8* src, uint
     "sgtu      $v1,%[dst],$t9                    \n"
     "bne       %[dst],$a3,$ua_loop16w            \n"
     " addiu    %[src],%[src],64                  \n"  // adding 64 to src
     "move      %[count],$t8                      \n"
 
     // Here we have src and dest word-aligned but less than 64-bytes to go
 
     "ua_chk8w:                                   \n"
+#ifdef HAS_MIPS_PREFETCH
     "pref      0, 0x0(%[src])                    \n"
+#endif
     "andi      $t8, %[count], 0x1f               \n"  // 32-byte chunk?
     // the t8 is the reminder count
     "beq       %[count], $t8, $ua_chk1w          \n"
     // when count==t8, no 32-byte chunk
 
     "lwr       $t0, 0(%[src])                    \n"
     "lwl       $t0, 3(%[src])                    \n"
     "lwr       $t1, 4(%[src])                    \n"