Bug 1521158: Robustify cache-line invalidations on AARCH64. r=jandem
authorKannan Vijayan <kvijayan@mozilla.com>
Thu, 25 Apr 2019 12:01:30 -0400
changeset 530443 1b18ac7619e30bacc78e01bc154b8627fbfc41b5
parent 530442 a2f7510851a4b7603cd25691f82712b2f77ec863
child 530444 497afde99626354913b97fdab0abf760aa229cf3
push id11265
push userffxbld-merge
push dateMon, 13 May 2019 10:53:39 +0000
treeherdermozilla-beta@77e0fe8dbdd3 [default view] [failures only]
perfherder[talos] [build metrics] [platform microbench] (compared to previous push)
reviewersjandem
bugs1521158
milestone68.0a1
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Bug 1521158: Robustify cache-line invalidations on AARCH64. r=jandem
js/src/jit/arm64/vixl/MozCpu-vixl.cpp
--- a/js/src/jit/arm64/vixl/MozCpu-vixl.cpp
+++ b/js/src/jit/arm64/vixl/MozCpu-vixl.cpp
@@ -94,22 +94,24 @@ void CPU::EnsureIAndDCacheCoherency(void
   uintptr_t end = start + length;
 
   do {
     __asm__ __volatile__ (
       // Clean each line of the D cache containing the target data.
       //
       // dc       : Data Cache maintenance
       //     c    : Clean
+      //      i   : Invalidate
       //      va  : by (Virtual) Address
-      //        u : to the point of Unification
-      // The point of unification for a processor is the point by which the
-      // instruction and data caches are guaranteed to see the same copy of a
-      // memory location. See ARM DDI 0406B page B2-12 for more information.
-      "   dc    cvau, %[dline]\n"
+      //        c : to the point of Coherency
+      // Original implementation used cvau, but changed to civac due to
+      // errata on Cortex-A53 819472, 826319, 827319 and 824069.
+      // See ARM DDI 0406B page B2-12 for more information.
+      //
+      "   dc    civac, %[dline]\n"
       :
       : [dline] "r" (dline)
       // This code does not write to memory, but the "memory" dependency
       // prevents GCC from reordering the code.
       : "memory");
     dline += dsize;
   } while (dline < end);