Bug 473880 - TM: Add a way to keep stack values alive without emitting guard code. r=gal.
authorDavid Anderson <danderson@mozilla.com>
Fri, 23 Jan 2009 15:21:55 -0600
changeset 23166 7827ad2e5d448dac48680a38bdab879c4d03cd3b
parent 23165 00d1e8523f73c3c1eac79cc2c62e1e95407837d8
child 23167 8ca10f09f25cb6b9d743abdb6a91c29d9a9573c3
push id624
push userrsayre@mozilla.com
push dateThu, 05 Feb 2009 20:15:27 +0000
reviewersgal
bugs473880
milestone1.9.1b3pre
Bug 473880 - TM: Add a way to keep stack values alive without emitting guard code. r=gal.
js/src/nanojit/Assembler.cpp
js/src/nanojit/LIR.cpp
js/src/nanojit/LIR.h
js/src/nanojit/LIRopcode.tbl
--- a/js/src/nanojit/Assembler.cpp
+++ b/js/src/nanojit/Assembler.cpp
@@ -1025,17 +1025,17 @@ namespace nanojit
 		for (LInsp ins = reader->read(); ins != 0 && !error(); ins = reader->read())
 		{
 			LOpcode op = ins->opcode();			
 			switch(op)
 			{
 				default:
 					NanoAssertMsgf(false, "unsupported LIR instruction: %d (~0x40: %d)", op, op&~LIR64);
 					break;
-					
+
                 case LIR_live: {
                     countlir_live();
                     pending_lives.add(ins->oprnd1());
                     break;
                 }
 
                 case LIR_ret:  {
                     countlir_ret();
@@ -1324,17 +1324,19 @@ namespace nanojit
                         NanoAssert(label->addr == 0 && label->regs.isValid());
                         //evictRegs(~_allocator.free);
                         intersectRegisterState(label->regs);
                         label->addr = _nIns;
                     }
 					verbose_only( if (_verbose) { outputAddr=true; asm_output("[%s]", _thisfrag->lirbuf->names->formatRef(ins)); } )
 					break;
 				}
-
+				case LIR_xbarrier: {
+					break;
+				}
                 case LIR_xt:
 				case LIR_xf:
 				{
                     countlir_xcc();
 					// we only support cmp with guard right now, also assume it is 'close' and only emit the branch
                     NIns* exit = asm_exit(ins); // does intersectRegisterState()
 					LIns* cond = ins->oprnd1();
 					asm_branch(op == LIR_xf, cond, exit, false);
--- a/js/src/nanojit/LIR.cpp
+++ b/js/src/nanojit/LIR.cpp
@@ -1877,16 +1877,17 @@ namespace nanojit
             case LIR_cs:
 			case LIR_not: 
 				sprintf(s, "%s = %s %s", formatRef(i), lirNames[op], formatRef(i->oprnd1()));
 				break;
 
 			case LIR_x:
 			case LIR_xt:
 			case LIR_xf:
+			case LIR_xbarrier:
 				formatGuard(i, s);
 				break;
 
 			case LIR_add:
 			case LIR_addp:
 			case LIR_sub: 
 		 	case LIR_mul: 
 			case LIR_fadd:
--- a/js/src/nanojit/LIR.h
+++ b/js/src/nanojit/LIR.h
@@ -135,17 +135,17 @@ namespace nanojit
         }
 		inline uint32_t FASTCALL count_iargs() const {
             return _count_args(_ARGSIZE_MASK_INT);
         }
 		// fargs = args - iargs
 	};
 
     inline bool isGuard(LOpcode op) {
-        return op==LIR_x || op==LIR_xf || op==LIR_xt || op==LIR_loop;
+        return op == LIR_x || op == LIR_xf || op == LIR_xt || op == LIR_loop || op == LIR_xbarrier;
     }
 
     inline bool isCall(LOpcode op) {
         op = LOpcode(op & ~LIR64);
         return op == LIR_call || op == LIR_calli;
     }
 
     inline bool isStore(LOpcode op) {
--- a/js/src/nanojit/LIRopcode.tbl
+++ b/js/src/nanojit/LIRopcode.tbl
@@ -171,17 +171,17 @@ OPDEF(ge,       59, 2) // 0x3B 0011 1011
 OPDEF(ult,      60, 2) // 0x3C 0011 1100
 OPDEF(ugt,      61, 2) // 0x3D 0011 1101
 OPDEF(ule,      62, 2) // 0x3E 0011 1110
 OPDEF(uge,      63, 2) // 0x3F 0011 1111
 
 OPDEF64(2,          0, 2) // wraps a pair of refs
 OPDEF64(file,       1, 2)
 OPDEF64(line,       2, 2)
-OPDEF64(unused3_64, 3, 2)
+OPDEF64(xbarrier,   3, 1) // memory barrier (dummy guard)
 
 OPDEF64(unused4_64,   4, 2)
 OPDEF64(unused5_64,   5, 2)
 OPDEF64(unused6_64,   6, 2)
 OPDEF64(unused7_64,   7, 2)
 OPDEF64(unused8_64,   8, 2)
 OPDEF64(unused9_64,   9, 2)
 OPDEF64(unused10_64, 10, 2)