Bug 1036781 - Part 3: Replace MOZ_ASSUME_UNREACHABLE with MOZ_CRASH in js/src/jit for x86 and x64. r=jandem
authorChris Peterson <cpeterson@mozilla.com>
Wed, 20 Aug 2014 22:36:57 -0700
changeset 200754 ff9ac3b549cc6f6415c6ff9b66b4d9059c767698
parent 200753 7a6008e82204cb0221305eb0bb38215c34e72a32
child 200755 151a4beda6efc3a54c5b3717e84fc72598129870
push id1
push userroot
push dateMon, 20 Oct 2014 17:29:22 +0000
reviewersjandem
bugs1036781
milestone34.0a1
Bug 1036781 - Part 3: Replace MOZ_ASSUME_UNREACHABLE with MOZ_CRASH in js/src/jit for x86 and x64. r=jandem
js/src/jit/shared/Assembler-x86-shared.cpp
js/src/jit/shared/Assembler-x86-shared.h
js/src/jit/shared/CodeGenerator-x86-shared.cpp
js/src/jit/shared/MacroAssembler-x86-shared.h
js/src/jit/shared/MoveEmitter-x86-shared.cpp
js/src/jit/x64/Assembler-x64.cpp
js/src/jit/x64/Assembler-x64.h
js/src/jit/x64/Bailouts-x64.cpp
js/src/jit/x64/BaselineIC-x64.cpp
js/src/jit/x64/CodeGenerator-x64.cpp
js/src/jit/x64/Lowering-x64.cpp
js/src/jit/x64/MacroAssembler-x64.cpp
js/src/jit/x64/MacroAssembler-x64.h
js/src/jit/x64/Trampoline-x64.cpp
js/src/jit/x86/MacroAssembler-x86.cpp
--- a/js/src/jit/shared/Assembler-x86-shared.cpp
+++ b/js/src/jit/shared/Assembler-x86-shared.cpp
@@ -123,11 +123,11 @@ AssemblerX86Shared::InvertCondition(Cond
         return BelowOrEqual;
       case AboveOrEqual:
         return Below;
       case Below:
         return AboveOrEqual;
       case BelowOrEqual:
         return Above;
       default:
-        MOZ_ASSUME_UNREACHABLE("unexpected condition");
+        MOZ_CRASH("unexpected condition");
     }
 }
--- a/js/src/jit/shared/Assembler-x86-shared.h
+++ b/js/src/jit/shared/Assembler-x86-shared.h
@@ -241,17 +241,17 @@ class AssemblerX86Shared : public Assemb
           case DoubleLessThanOrEqualOrUnordered:
             return NaN_HandledByCond;
           case DoubleEqual:
             return NaN_IsFalse;
           case DoubleNotEqualOrUnordered:
             return NaN_IsTrue;
         }
 
-        MOZ_ASSUME_UNREACHABLE("Unknown double condition");
+        MOZ_CRASH("Unknown double condition");
     }
 
     static void StaticAsserts() {
         // DoubleConditionBits should not interfere with x86 condition codes.
         JS_STATIC_ASSERT(!((Equal | NotEqual | Above | AboveOrEqual | Below |
                             BelowOrEqual | Parity | NoParity) & DoubleConditionBits));
     }
 
@@ -365,17 +365,17 @@ class AssemblerX86Shared : public Assemb
             break;
           case Operand::MEM_SCALE:
             masm.movl_mr(src.disp(), src.base(), src.index(), src.scale(), dest.code());
             break;
           case Operand::MEM_ADDRESS32:
             masm.movl_mr(src.address(), dest.code());
             break;
           default:
-            MOZ_ASSUME_UNREACHABLE("unexpected operand kind");
+            MOZ_CRASH("unexpected operand kind");
         }
     }
     void movl(Register src, const Operand &dest) {
         switch (dest.kind()) {
           case Operand::REG:
             masm.movl_rr(src.code(), dest.reg());
             break;
           case Operand::MEM_REG_DISP:
@@ -383,32 +383,32 @@ class AssemblerX86Shared : public Assemb
             break;
           case Operand::MEM_SCALE:
             masm.movl_rm(src.code(), dest.disp(), dest.base(), dest.index(), dest.scale());
             break;
           case Operand::MEM_ADDRESS32:
             masm.movl_rm(src.code(), dest.address());
             break;
           default:
-            MOZ_ASSUME_UNREACHABLE("unexpected operand kind");
+            MOZ_CRASH("unexpected operand kind");
         }
     }
     void movl(Imm32 imm32, const Operand &dest) {
         switch (dest.kind()) {
           case Operand::REG:
             masm.movl_i32r(imm32.value, dest.reg());
             break;
           case Operand::MEM_REG_DISP:
             masm.movl_i32m(imm32.value, dest.disp(), dest.base());
             break;
           case Operand::MEM_SCALE:
             masm.movl_i32m(imm32.value, dest.disp(), dest.base(), dest.index(), dest.scale());
             break;
           default:
-            MOZ_ASSUME_UNREACHABLE("unexpected operand kind");
+            MOZ_CRASH("unexpected operand kind");
         }
     }
 
     void xchgl(Register src, Register dest) {
         masm.xchgl_rr(src.code(), dest.code());
     }
 
     // Eventually movapd should be overloaded to support loads and
@@ -427,56 +427,56 @@ class AssemblerX86Shared : public Assemb
         switch (src.kind()) {
           case Operand::MEM_REG_DISP:
             masm.movaps_mr(src.disp(), src.base(), dest.code());
             break;
           case Operand::MEM_SCALE:
             masm.movaps_mr(src.disp(), src.base(), src.index(), src.scale(), dest.code());
             break;
           default:
-            MOZ_ASSUME_UNREACHABLE("unexpected operand kind");
+            MOZ_CRASH("unexpected operand kind");
         }
     }
     void movaps(FloatRegister src, const Operand &dest) {
         JS_ASSERT(HasSSE2());
         switch (dest.kind()) {
           case Operand::MEM_REG_DISP:
             masm.movaps_rm(src.code(), dest.disp(), dest.base());
             break;
           case Operand::MEM_SCALE:
             masm.movaps_rm(src.code(), dest.disp(), dest.base(), dest.index(), dest.scale());
             break;
           default:
-            MOZ_ASSUME_UNREACHABLE("unexpected operand kind");
+            MOZ_CRASH("unexpected operand kind");
         }
     }
     void movups(const Operand &src, FloatRegister dest) {
         JS_ASSERT(HasSSE2());
         switch (src.kind()) {
           case Operand::MEM_REG_DISP:
             masm.movups_mr(src.disp(), src.base(), dest.code());
             break;
           case Operand::MEM_SCALE:
             masm.movups_mr(src.disp(), src.base(), src.index(), src.scale(), dest.code());
             break;
           default:
-            MOZ_ASSUME_UNREACHABLE("unexpected operand kind");
+            MOZ_CRASH("unexpected operand kind");
         }
     }
     void movups(FloatRegister src, const Operand &dest) {
         JS_ASSERT(HasSSE2());
         switch (dest.kind()) {
           case Operand::MEM_REG_DISP:
             masm.movups_rm(src.code(), dest.disp(), dest.base());
             break;
           case Operand::MEM_SCALE:
             masm.movups_rm(src.code(), dest.disp(), dest.base(), dest.index(), dest.scale());
             break;
           default:
-            MOZ_ASSUME_UNREACHABLE("unexpected operand kind");
+            MOZ_CRASH("unexpected operand kind");
         }
     }
 
     // movsd and movss are only provided in load/store form since the
     // register-to-register form has different semantics (it doesn't clobber
     // the whole output register) and isn't needed currently.
     void movsd(const Address &src, FloatRegister dest) {
         masm.movsd_mr(src.offset, src.base.code(), dest.code());
@@ -507,56 +507,56 @@ class AssemblerX86Shared : public Assemb
         switch (src.kind()) {
           case Operand::MEM_REG_DISP:
             masm.movdqu_mr(src.disp(), src.base(), dest.code());
             break;
           case Operand::MEM_SCALE:
             masm.movdqu_mr(src.disp(), src.base(), src.index(), src.scale(), dest.code());
             break;
           default:
-            MOZ_ASSUME_UNREACHABLE("unexpected operand kind");
+            MOZ_CRASH("unexpected operand kind");
         }
     }
     void movdqu(FloatRegister src, const Operand &dest) {
         JS_ASSERT(HasSSE2());
         switch (dest.kind()) {
           case Operand::MEM_REG_DISP:
             masm.movdqu_rm(src.code(), dest.disp(), dest.base());
             break;
           case Operand::MEM_SCALE:
             masm.movdqu_rm(src.code(), dest.disp(), dest.base(), dest.index(), dest.scale());
             break;
           default:
-            MOZ_ASSUME_UNREACHABLE("unexpected operand kind");
+            MOZ_CRASH("unexpected operand kind");
         }
     }
     void movdqa(const Operand &src, FloatRegister dest) {
         JS_ASSERT(HasSSE2());
         switch (src.kind()) {
           case Operand::MEM_REG_DISP:
             masm.movdqa_mr(src.disp(), src.base(), dest.code());
             break;
           case Operand::MEM_SCALE:
             masm.movdqa_mr(src.disp(), src.base(), src.index(), src.scale(), dest.code());
             break;
           default:
-            MOZ_ASSUME_UNREACHABLE("unexpected operand kind");
+            MOZ_CRASH("unexpected operand kind");
         }
     }
     void movdqa(FloatRegister src, const Operand &dest) {
         JS_ASSERT(HasSSE2());
         switch (dest.kind()) {
           case Operand::MEM_REG_DISP:
             masm.movdqa_rm(src.code(), dest.disp(), dest.base());
             break;
           case Operand::MEM_SCALE:
             masm.movdqa_rm(src.code(), dest.disp(), dest.base(), dest.index(), dest.scale());
             break;
           default:
-            MOZ_ASSUME_UNREACHABLE("unexpected operand kind");
+            MOZ_CRASH("unexpected operand kind");
         }
     }
     void movdqa(FloatRegister src, FloatRegister dest) {
         JS_ASSERT(HasSSE2());
         masm.movdqa_rr(src.code(), dest.code());
     }
     void cvtss2sd(FloatRegister src, FloatRegister dest) {
         JS_ASSERT(HasSSE2());
@@ -570,119 +570,119 @@ class AssemblerX86Shared : public Assemb
         switch (src.kind()) {
           case Operand::MEM_REG_DISP:
             masm.movzbl_mr(src.disp(), src.base(), dest.code());
             break;
           case Operand::MEM_SCALE:
             masm.movzbl_mr(src.disp(), src.base(), src.index(), src.scale(), dest.code());
             break;
           default:
-            MOZ_ASSUME_UNREACHABLE("unexpected operand kind");
+            MOZ_CRASH("unexpected operand kind");
         }
     }
     void movsbl(const Operand &src, Register dest) {
         switch (src.kind()) {
           case Operand::MEM_REG_DISP:
             masm.movsbl_mr(src.disp(), src.base(), dest.code());
             break;
           case Operand::MEM_SCALE:
             masm.movsbl_mr(src.disp(), src.base(), src.index(), src.scale(), dest.code());
             break;
           default:
-            MOZ_ASSUME_UNREACHABLE("unexpected operand kind");
+            MOZ_CRASH("unexpected operand kind");
         }
     }
     void movb(Register src, const Operand &dest) {
         switch (dest.kind()) {
           case Operand::MEM_REG_DISP:
             masm.movb_rm(src.code(), dest.disp(), dest.base());
             break;
           case Operand::MEM_SCALE:
             masm.movb_rm(src.code(), dest.disp(), dest.base(), dest.index(), dest.scale());
             break;
           default:
-            MOZ_ASSUME_UNREACHABLE("unexpected operand kind");
+            MOZ_CRASH("unexpected operand kind");
         }
     }
     void movb(Imm32 src, const Operand &dest) {
         switch (dest.kind()) {
           case Operand::MEM_REG_DISP:
             masm.movb_i8m(src.value, dest.disp(), dest.base());
             break;
           case Operand::MEM_SCALE:
             masm.movb_i8m(src.value, dest.disp(), dest.base(), dest.index(), dest.scale());
             break;
           default:
-            MOZ_ASSUME_UNREACHABLE("unexpected operand kind");
+            MOZ_CRASH("unexpected operand kind");
         }
     }
     void movzwl(const Operand &src, Register dest) {
         switch (src.kind()) {
           case Operand::REG:
             masm.movzwl_rr(src.reg(), dest.code());
             break;
           case Operand::MEM_REG_DISP:
             masm.movzwl_mr(src.disp(), src.base(), dest.code());
             break;
           case Operand::MEM_SCALE:
             masm.movzwl_mr(src.disp(), src.base(), src.index(), src.scale(), dest.code());
             break;
           default:
-            MOZ_ASSUME_UNREACHABLE("unexpected operand kind");
+            MOZ_CRASH("unexpected operand kind");
         }
     }
     void movzwl(Register src, Register dest) {
         masm.movzwl_rr(src.code(), dest.code());
     }
     void movw(Register src, const Operand &dest) {
         switch (dest.kind()) {
           case Operand::MEM_REG_DISP:
             masm.movw_rm(src.code(), dest.disp(), dest.base());
             break;
           case Operand::MEM_SCALE:
             masm.movw_rm(src.code(), dest.disp(), dest.base(), dest.index(), dest.scale());
             break;
           default:
-            MOZ_ASSUME_UNREACHABLE("unexpected operand kind");
+            MOZ_CRASH("unexpected operand kind");
         }
     }
     void movw(Imm32 src, const Operand &dest) {
         switch (dest.kind()) {
           case Operand::MEM_REG_DISP:
             masm.movw_i16m(src.value, dest.disp(), dest.base());
             break;
           case Operand::MEM_SCALE:
             masm.movw_i16m(src.value, dest.disp(), dest.base(), dest.index(), dest.scale());
             break;
           default:
-            MOZ_ASSUME_UNREACHABLE("unexpected operand kind");
+            MOZ_CRASH("unexpected operand kind");
         }
     }
     void movswl(const Operand &src, Register dest) {
         switch (src.kind()) {
           case Operand::MEM_REG_DISP:
             masm.movswl_mr(src.disp(), src.base(), dest.code());
             break;
           case Operand::MEM_SCALE:
             masm.movswl_mr(src.disp(), src.base(), src.index(), src.scale(), dest.code());
             break;
           default:
-            MOZ_ASSUME_UNREACHABLE("unexpected operand kind");
+            MOZ_CRASH("unexpected operand kind");
         }
     }
     void leal(const Operand &src, Register dest) {
         switch (src.kind()) {
           case Operand::MEM_REG_DISP:
             masm.leal_mr(src.disp(), src.base(), dest.code());
             break;
           case Operand::MEM_SCALE:
             masm.leal_mr(src.disp(), src.base(), src.index(), src.scale(), dest.code());
             break;
           default:
-            MOZ_ASSUME_UNREACHABLE("unexpected operand kind");
+            MOZ_CRASH("unexpected operand kind");
         }
     }
 
   protected:
     JmpSrc jSrc(Condition cond, Label *label) {
         JmpSrc j = masm.jCC(static_cast<X86Assembler::Condition>(cond));
         if (label->bound()) {
             // The jump can be immediately patched to the correct destination.
@@ -758,17 +758,17 @@ class AssemblerX86Shared : public Assemb
             break;
           case Operand::MEM_SCALE:
             masm.jmp_m(op.disp(), op.base(), op.index(), op.scale());
             break;
           case Operand::REG:
             masm.jmp_r(op.reg());
             break;
           default:
-            MOZ_ASSUME_UNREACHABLE("unexpected operand kind");
+            MOZ_CRASH("unexpected operand kind");
         }
     }
     void cmpEAX(Label *label) { cmpSrc(label); }
     void bind(Label *label) {
         X86Assembler::JmpDst dst(masm.label());
         if (label->used()) {
             bool more;
             X86Assembler::JmpSrc jmp(label->offset());
@@ -857,17 +857,17 @@ class AssemblerX86Shared : public Assemb
         switch (op.kind()) {
           case Operand::REG:
             masm.call(op.reg());
             break;
           case Operand::MEM_REG_DISP:
             masm.call_m(op.disp(), op.base());
             break;
           default:
-            MOZ_ASSUME_UNREACHABLE("unexpected operand kind");
+            MOZ_CRASH("unexpected operand kind");
         }
     }
 
     void breakpoint() {
         masm.int3();
     }
 
 #ifdef DEBUG
@@ -892,17 +892,17 @@ class AssemblerX86Shared : public Assemb
         switch (rhs.kind()) {
           case Operand::REG:
             masm.cmpl_rr(rhs.reg(), lhs.code());
             break;
           case Operand::MEM_REG_DISP:
             masm.cmpl_mr(rhs.disp(), rhs.base(), lhs.code());
             break;
           default:
-            MOZ_ASSUME_UNREACHABLE("unexpected operand kind");
+            MOZ_CRASH("unexpected operand kind");
         }
     }
     void cmpl(Register src, Imm32 imm) {
         masm.cmpl_ir(imm.value, src.code());
     }
     void cmpl(const Operand &op, Imm32 imm) {
         switch (op.kind()) {
           case Operand::REG:
@@ -913,47 +913,47 @@ class AssemblerX86Shared : public Assemb
             break;
           case Operand::MEM_SCALE:
             masm.cmpl_im(imm.value, op.disp(), op.base(), op.index(), op.scale());
             break;
           case Operand::MEM_ADDRESS32:
             masm.cmpl_im(imm.value, op.address());
             break;
           default:
-            MOZ_ASSUME_UNREACHABLE("unexpected operand kind");
+            MOZ_CRASH("unexpected operand kind");
         }
     }
     void cmpl(const Operand &lhs, Register rhs) {
         switch (lhs.kind()) {
           case Operand::REG:
             masm.cmpl_rr(rhs.code(), lhs.reg());
             break;
           case Operand::MEM_REG_DISP:
             masm.cmpl_rm(rhs.code(), lhs.disp(), lhs.base());
             break;
           case Operand::MEM_ADDRESS32:
             masm.cmpl_rm(rhs.code(), lhs.address());
             break;
           default:
-            MOZ_ASSUME_UNREACHABLE("unexpected operand kind");
+            MOZ_CRASH("unexpected operand kind");
         }
     }
     void cmpl(const Operand &op, ImmWord imm) {
         switch (op.kind()) {
           case Operand::REG:
             masm.cmpl_ir(imm.value, op.reg());
             break;
           case Operand::MEM_REG_DISP:
             masm.cmpl_im(imm.value, op.disp(), op.base());
             break;
           case Operand::MEM_ADDRESS32:
             masm.cmpl_im(imm.value, op.address());
             break;
           default:
-            MOZ_ASSUME_UNREACHABLE("unexpected operand kind");
+            MOZ_CRASH("unexpected operand kind");
         }
     }
     void cmpl(const Operand &op, ImmPtr imm) {
         cmpl(op, ImmWord(uintptr_t(imm.value)));
     }
     CodeOffsetLabel cmplWithPatch(Register lhs, Imm32 rhs) {
         masm.cmpl_ir_force32(rhs.value, lhs.code());
         return CodeOffsetLabel(masm.currentOffset());
@@ -985,17 +985,17 @@ class AssemblerX86Shared : public Assemb
             break;
           case Operand::MEM_REG_DISP:
             masm.testl_i32m(rhs.value, lhs.disp(), lhs.base());
             break;
           case Operand::MEM_ADDRESS32:
             masm.testl_i32m(rhs.value, lhs.address());
             break;
           default:
-            MOZ_ASSUME_UNREACHABLE("unexpected operand kind");
+            MOZ_CRASH("unexpected operand kind");
             break;
         }
     }
 
     void addl(Imm32 imm, Register dest) {
         masm.addl_ir(imm.value, dest.code());
     }
     void addl(Imm32 imm, const Operand &op) {
@@ -1005,32 +1005,32 @@ class AssemblerX86Shared : public Assemb
             break;
           case Operand::MEM_REG_DISP:
             masm.addl_im(imm.value, op.disp(), op.base());
             break;
           case Operand::MEM_ADDRESS32:
             masm.addl_im(imm.value, op.address());
             break;
           default:
-            MOZ_ASSUME_UNREACHABLE("unexpected operand kind");
+            MOZ_CRASH("unexpected operand kind");
         }
     }
     void subl(Imm32 imm, Register dest) {
         masm.subl_ir(imm.value, dest.code());
     }
     void subl(Imm32 imm, const Operand &op) {
         switch (op.kind()) {
           case Operand::REG:
             masm.subl_ir(imm.value, op.reg());
             break;
           case Operand::MEM_REG_DISP:
             masm.subl_im(imm.value, op.disp(), op.base());
             break;
           default:
-            MOZ_ASSUME_UNREACHABLE("unexpected operand kind");
+            MOZ_CRASH("unexpected operand kind");
         }
     }
     void addl(Register src, Register dest) {
         masm.addl_rr(src.code(), dest.code());
     }
     void subl(Register src, Register dest) {
         masm.subl_rr(src.code(), dest.code());
     }
@@ -1038,29 +1038,29 @@ class AssemblerX86Shared : public Assemb
         switch (src.kind()) {
           case Operand::REG:
             masm.subl_rr(src.reg(), dest.code());
             break;
           case Operand::MEM_REG_DISP:
             masm.subl_mr(src.disp(), src.base(), dest.code());
             break;
           default:
-            MOZ_ASSUME_UNREACHABLE("unexpected operand kind");
+            MOZ_CRASH("unexpected operand kind");
         }
     }
     void subl(Register src, const Operand &dest) {
         switch (dest.kind()) {
           case Operand::REG:
             masm.subl_rr(src.code(), dest.reg());
             break;
           case Operand::MEM_REG_DISP:
             masm.subl_rm(src.code(), dest.disp(), dest.base());
             break;
           default:
-            MOZ_ASSUME_UNREACHABLE("unexpected operand kind");
+            MOZ_CRASH("unexpected operand kind");
         }
     }
     void orl(Register reg, Register dest) {
         masm.orl_rr(reg.code(), dest.code());
     }
     void orl(Imm32 imm, Register reg) {
         masm.orl_ir(imm.value, reg.code());
     }
@@ -1068,17 +1068,17 @@ class AssemblerX86Shared : public Assemb
         switch (op.kind()) {
           case Operand::REG:
             masm.orl_ir(imm.value, op.reg());
             break;
           case Operand::MEM_REG_DISP:
             masm.orl_im(imm.value, op.disp(), op.base());
             break;
           default:
-            MOZ_ASSUME_UNREACHABLE("unexpected operand kind");
+            MOZ_CRASH("unexpected operand kind");
         }
     }
     void xorl(Register src, Register dest) {
         masm.xorl_rr(src.code(), dest.code());
     }
     void xorl(Imm32 imm, Register reg) {
         masm.xorl_ir(imm.value, reg.code());
     }
@@ -1086,17 +1086,17 @@ class AssemblerX86Shared : public Assemb
         switch (op.kind()) {
           case Operand::REG:
             masm.xorl_ir(imm.value, op.reg());
             break;
           case Operand::MEM_REG_DISP:
             masm.xorl_im(imm.value, op.disp(), op.base());
             break;
           default:
-            MOZ_ASSUME_UNREACHABLE("unexpected operand kind");
+            MOZ_CRASH("unexpected operand kind");
         }
     }
     void andl(Register src, Register dest) {
         masm.andl_rr(src.code(), dest.code());
     }
     void andl(Imm32 imm, Register dest) {
         masm.andl_ir(imm.value, dest.code());
     }
@@ -1104,65 +1104,65 @@ class AssemblerX86Shared : public Assemb
         switch (op.kind()) {
           case Operand::REG:
             masm.andl_ir(imm.value, op.reg());
             break;
           case Operand::MEM_REG_DISP:
             masm.andl_im(imm.value, op.disp(), op.base());
             break;
           default:
-            MOZ_ASSUME_UNREACHABLE("unexpected operand kind");
+            MOZ_CRASH("unexpected operand kind");
         }
     }
     void addl(const Operand &src, Register dest) {
         switch (src.kind()) {
           case Operand::REG:
             masm.addl_rr(src.reg(), dest.code());
             break;
           case Operand::MEM_REG_DISP:
             masm.addl_mr(src.disp(), src.base(), dest.code());
             break;
           default:
-            MOZ_ASSUME_UNREACHABLE("unexpected operand kind");
+            MOZ_CRASH("unexpected operand kind");
         }
     }
     void orl(const Operand &src, Register dest) {
         switch (src.kind()) {
           case Operand::REG:
             masm.orl_rr(src.reg(), dest.code());
             break;
           case Operand::MEM_REG_DISP:
             masm.orl_mr(src.disp(), src.base(), dest.code());
             break;
           default:
-            MOZ_ASSUME_UNREACHABLE("unexpected operand kind");
+            MOZ_CRASH("unexpected operand kind");
         }
     }
     void xorl(const Operand &src, Register dest) {
         switch (src.kind()) {
           case Operand::REG:
             masm.xorl_rr(src.reg(), dest.code());
             break;
           case Operand::MEM_REG_DISP:
             masm.xorl_mr(src.disp(), src.base(), dest.code());
             break;
           default:
-            MOZ_ASSUME_UNREACHABLE("unexpected operand kind");
+            MOZ_CRASH("unexpected operand kind");
         }
     }
     void andl(const Operand &src, Register dest) {
         switch (src.kind()) {
           case Operand::REG:
             masm.andl_rr(src.reg(), dest.code());
             break;
           case Operand::MEM_REG_DISP:
             masm.andl_mr(src.disp(), src.base(), dest.code());
             break;
           default:
-            MOZ_ASSUME_UNREACHABLE("unexpected operand kind");
+            MOZ_CRASH("unexpected operand kind");
         }
     }
     void imull(Register multiplier) {
         masm.imull_r(multiplier.code());
     }
     void imull(Imm32 imm, Register dest) {
         masm.imull_i32r(dest.code(), imm.value, dest.code());
     }
@@ -1176,44 +1176,44 @@ class AssemblerX86Shared : public Assemb
         switch (src.kind()) {
           case Operand::REG:
             masm.imull_rr(src.reg(), dest.code());
             break;
           case Operand::MEM_REG_DISP:
             masm.imull_mr(src.disp(), src.base(), dest.code());
             break;
           default:
-            MOZ_ASSUME_UNREACHABLE("unexpected operand kind");
+            MOZ_CRASH("unexpected operand kind");
         }
     }
     void negl(const Operand &src) {
         switch (src.kind()) {
           case Operand::REG:
             masm.negl_r(src.reg());
             break;
           case Operand::MEM_REG_DISP:
             masm.negl_m(src.disp(), src.base());
             break;
           default:
-            MOZ_ASSUME_UNREACHABLE("unexpected operand kind");
+            MOZ_CRASH("unexpected operand kind");
         }
     }
     void negl(Register reg) {
         masm.negl_r(reg.code());
     }
     void notl(const Operand &src) {
         switch (src.kind()) {
           case Operand::REG:
             masm.notl_r(src.reg());
             break;
           case Operand::MEM_REG_DISP:
             masm.notl_m(src.disp(), src.base());
             break;
           default:
-            MOZ_ASSUME_UNREACHABLE("unexpected operand kind");
+            MOZ_CRASH("unexpected operand kind");
         }
     }
     void notl(Register reg) {
         masm.notl_r(reg.code());
     }
     void shrl(const Imm32 imm, Register dest) {
         masm.shrl_i8r(imm.value, dest.code());
     }
@@ -1234,76 +1234,76 @@ class AssemblerX86Shared : public Assemb
     }
 
     void incl(const Operand &op) {
         switch (op.kind()) {
           case Operand::MEM_REG_DISP:
             masm.incl_m32(op.disp(), op.base());
             break;
           default:
-            MOZ_ASSUME_UNREACHABLE("unexpected operand kind");
+            MOZ_CRASH("unexpected operand kind");
         }
     }
     void lock_incl(const Operand &op) {
         masm.prefix_lock();
         incl(op);
     }
 
     void decl(const Operand &op) {
         switch (op.kind()) {
           case Operand::MEM_REG_DISP:
             masm.decl_m32(op.disp(), op.base());
             break;
           default:
-            MOZ_ASSUME_UNREACHABLE("unexpected operand kind");
+            MOZ_CRASH("unexpected operand kind");
         }
     }
     void lock_decl(const Operand &op) {
         masm.prefix_lock();
         decl(op);
     }
 
     void lock_cmpxchg32(Register src, const Operand &op) {
         masm.prefix_lock();
         switch (op.kind()) {
           case Operand::MEM_REG_DISP:
             masm.cmpxchg32(src.code(), op.disp(), op.base());
             break;
           default:
-            MOZ_ASSUME_UNREACHABLE("unexpected operand kind");
+            MOZ_CRASH("unexpected operand kind");
         }
     }
 
     void xaddl(Register srcdest, const Operand &mem) {
         switch (mem.kind()) {
           case Operand::MEM_REG_DISP:
             masm.xaddl_rm(srcdest.code(), mem.disp(), mem.base());
             break;
           case Operand::MEM_SCALE:
             masm.xaddl_rm(srcdest.code(), mem.disp(), mem.base(), mem.index(), mem.scale());
             break;
           default:
-            MOZ_ASSUME_UNREACHABLE("unexpected operand kind");
+            MOZ_CRASH("unexpected operand kind");
         }
     }
 
     void push(const Imm32 imm) {
         masm.push_i32(imm.value);
     }
 
     void push(const Operand &src) {
         switch (src.kind()) {
           case Operand::REG:
             masm.push_r(src.reg());
             break;
           case Operand::MEM_REG_DISP:
             masm.push_m(src.disp(), src.base());
             break;
           default:
-            MOZ_ASSUME_UNREACHABLE("unexpected operand kind");
+            MOZ_CRASH("unexpected operand kind");
         }
     }
     void push(Register src) {
         masm.push_r(src.code());
     }
     void push(const Address &src) {
         masm.push_m(src.offset, src.base.code());
     }
@@ -1312,17 +1312,17 @@ class AssemblerX86Shared : public Assemb
         switch (src.kind()) {
           case Operand::REG:
             masm.pop_r(src.reg());
             break;
           case Operand::MEM_REG_DISP:
             masm.pop_m(src.disp(), src.base());
             break;
           default:
-            MOZ_ASSUME_UNREACHABLE("unexpected operand kind");
+            MOZ_CRASH("unexpected operand kind");
         }
     }
     void pop(Register src) {
         masm.pop_r(src.code());
     }
     void pop(const Address &src) {
         masm.pop_m(src.offset, src.base.code());
     }
@@ -1371,17 +1371,17 @@ class AssemblerX86Shared : public Assemb
         switch (src.kind()) {
           case Operand::REG:
             masm.pinsrd_rr(src.reg(), dest.code());
             break;
           case Operand::MEM_REG_DISP:
             masm.pinsrd_mr(src.disp(), src.base(), dest.code());
             break;
           default:
-            MOZ_ASSUME_UNREACHABLE("unexpected operand kind");
+            MOZ_CRASH("unexpected operand kind");
         }
     }
     void psrldq(Imm32 shift, FloatRegister dest) {
         JS_ASSERT(HasSSE2());
         masm.psrldq_ir(shift.value, dest.code());
     }
     void psllq(Imm32 shift, FloatRegister dest) {
         JS_ASSERT(HasSSE2());
@@ -1400,17 +1400,17 @@ class AssemblerX86Shared : public Assemb
             break;
           case Operand::MEM_REG_DISP:
             masm.cvtsi2sd_mr(src.disp(), src.base(), dest.code());
             break;
           case Operand::MEM_SCALE:
             masm.cvtsi2sd_mr(src.disp(), src.base(), src.index(), src.scale(), dest.code());
             break;
           default:
-            MOZ_ASSUME_UNREACHABLE("unexpected operand kind");
+            MOZ_CRASH("unexpected operand kind");
         }
     }
     void cvttsd2si(FloatRegister src, Register dest) {
         JS_ASSERT(HasSSE2());
         masm.cvttsd2si_rr(src.code(), dest.code());
     }
     void cvttss2si(FloatRegister src, Register dest) {
         JS_ASSERT(HasSSE2());
@@ -1424,17 +1424,17 @@ class AssemblerX86Shared : public Assemb
             break;
           case Operand::MEM_REG_DISP:
             masm.cvtsi2ss_mr(src.disp(), src.base(), dest.code());
             break;
           case Operand::MEM_SCALE:
             masm.cvtsi2ss_mr(src.disp(), src.base(), src.index(), src.scale(), dest.code());
             break;
           default:
-            MOZ_ASSUME_UNREACHABLE("unexpected operand kind");
+            MOZ_CRASH("unexpected operand kind");
         }
     }
     void cvtsi2ss(Register src, FloatRegister dest) {
         JS_ASSERT(HasSSE2());
         masm.cvtsi2ss_rr(src.code(), dest.code());
     }
     void cvtsi2sd(Register src, FloatRegister dest) {
         JS_ASSERT(HasSSE2());
@@ -1480,97 +1480,97 @@ class AssemblerX86Shared : public Assemb
             break;
           case Operand::MEM_REG_DISP:
             masm.paddd_mr(src.disp(), src.base(), dest.code());
             break;
           case Operand::MEM_ADDRESS32:
             masm.paddd_mr(src.address(), dest.code());
             break;
           default:
-            MOZ_ASSUME_UNREACHABLE("unexpected operand kind");
+            MOZ_CRASH("unexpected operand kind");
         }
     }
     void psubd(const Operand &src, FloatRegister dest) {
         JS_ASSERT(HasSSE2());
         switch (src.kind()) {
           case Operand::FPREG:
             masm.psubd_rr(src.fpu(), dest.code());
             break;
           case Operand::MEM_REG_DISP:
             masm.psubd_mr(src.disp(), src.base(), dest.code());
             break;
           case Operand::MEM_ADDRESS32:
             masm.psubd_mr(src.address(), dest.code());
             break;
           default:
-            MOZ_ASSUME_UNREACHABLE("unexpected operand kind");
+            MOZ_CRASH("unexpected operand kind");
         }
     }
     void addps(const Operand &src, FloatRegister dest) {
         JS_ASSERT(HasSSE2());
         switch (src.kind()) {
           case Operand::FPREG:
             masm.addps_rr(src.fpu(), dest.code());
             break;
           case Operand::MEM_REG_DISP:
             masm.addps_mr(src.disp(), src.base(), dest.code());
             break;
           case Operand::MEM_ADDRESS32:
             masm.addps_mr(src.address(), dest.code());
             break;
           default:
-            MOZ_ASSUME_UNREACHABLE("unexpected operand kind");
+            MOZ_CRASH("unexpected operand kind");
         }
     }
     void subps(const Operand &src, FloatRegister dest) {
         JS_ASSERT(HasSSE2());
         switch (src.kind()) {
           case Operand::FPREG:
             masm.subps_rr(src.fpu(), dest.code());
             break;
           case Operand::MEM_REG_DISP:
             masm.subps_mr(src.disp(), src.base(), dest.code());
             break;
           case Operand::MEM_ADDRESS32:
             masm.subps_mr(src.address(), dest.code());
             break;
           default:
-            MOZ_ASSUME_UNREACHABLE("unexpected operand kind");
+            MOZ_CRASH("unexpected operand kind");
         }
     }
     void mulps(const Operand &src, FloatRegister dest) {
         JS_ASSERT(HasSSE2());
         switch (src.kind()) {
           case Operand::FPREG:
             masm.mulps_rr(src.fpu(), dest.code());
             break;
           case Operand::MEM_REG_DISP:
             masm.mulps_mr(src.disp(), src.base(), dest.code());
             break;
           case Operand::MEM_ADDRESS32:
             masm.mulps_mr(src.address(), dest.code());
             break;
           default:
-            MOZ_ASSUME_UNREACHABLE("unexpected operand kind");
+            MOZ_CRASH("unexpected operand kind");
         }
     }
     void divps(const Operand &src, FloatRegister dest) {
         JS_ASSERT(HasSSE2());
         switch (src.kind()) {
           case Operand::FPREG:
             masm.divps_rr(src.fpu(), dest.code());
             break;
           case Operand::MEM_REG_DISP:
             masm.divps_mr(src.disp(), src.base(), dest.code());
             break;
           case Operand::MEM_ADDRESS32:
             masm.divps_mr(src.address(), dest.code());
             break;
           default:
-            MOZ_ASSUME_UNREACHABLE("unexpected operand kind");
+            MOZ_CRASH("unexpected operand kind");
         }
     }
     void pxor(FloatRegister src, FloatRegister dest) {
         JS_ASSERT(HasSSE2());
         masm.pxor_rr(src.code(), dest.code());
     }
     void pshufd(uint32_t mask, FloatRegister src, FloatRegister dest) {
         JS_ASSERT(HasSSE2());
@@ -1600,33 +1600,33 @@ class AssemblerX86Shared : public Assemb
             break;
           case Operand::MEM_REG_DISP:
             masm.addsd_mr(src.disp(), src.base(), dest.code());
             break;
           case Operand::MEM_ADDRESS32:
             masm.addsd_mr(src.address(), dest.code());
             break;
           default:
-            MOZ_ASSUME_UNREACHABLE("unexpected operand kind");
+            MOZ_CRASH("unexpected operand kind");
         }
     }
     void addss(const Operand &src, FloatRegister dest) {
         JS_ASSERT(HasSSE2());
         switch (src.kind()) {
           case Operand::FPREG:
             masm.addss_rr(src.fpu(), dest.code());
             break;
           case Operand::MEM_REG_DISP:
             masm.addss_mr(src.disp(), src.base(), dest.code());
             break;
           case Operand::MEM_ADDRESS32:
             masm.addss_mr(src.address(), dest.code());
             break;
           default:
-            MOZ_ASSUME_UNREACHABLE("unexpected operand kind");
+            MOZ_CRASH("unexpected operand kind");
         }
     }
     void subsd(FloatRegister src, FloatRegister dest) {
         JS_ASSERT(HasSSE2());
         masm.subsd_rr(src.code(), dest.code());
     }
     void subss(FloatRegister src, FloatRegister dest) {
         JS_ASSERT(HasSSE2());
@@ -1637,60 +1637,60 @@ class AssemblerX86Shared : public Assemb
         switch (src.kind()) {
           case Operand::FPREG:
             masm.subsd_rr(src.fpu(), dest.code());
             break;
           case Operand::MEM_REG_DISP:
             masm.subsd_mr(src.disp(), src.base(), dest.code());
             break;
           default:
-            MOZ_ASSUME_UNREACHABLE("unexpected operand kind");
+            MOZ_CRASH("unexpected operand kind");
         }
     }
     void subss(const Operand &src, FloatRegister dest) {
         JS_ASSERT(HasSSE2());
         switch (src.kind()) {
           case Operand::FPREG:
             masm.subss_rr(src.fpu(), dest.code());
             break;
           case Operand::MEM_REG_DISP:
             masm.subss_mr(src.disp(), src.base(), dest.code());
             break;
           default:
-            MOZ_ASSUME_UNREACHABLE("unexpected operand kind");
+            MOZ_CRASH("unexpected operand kind");
         }
     }
     void mulsd(FloatRegister src, FloatRegister dest) {
         JS_ASSERT(HasSSE2());
         masm.mulsd_rr(src.code(), dest.code());
     }
     void mulsd(const Operand &src, FloatRegister dest) {
         JS_ASSERT(HasSSE2());
         switch (src.kind()) {
           case Operand::FPREG:
             masm.mulsd_rr(src.fpu(), dest.code());
             break;
           case Operand::MEM_REG_DISP:
             masm.mulsd_mr(src.disp(), src.base(), dest.code());
             break;
           default:
-            MOZ_ASSUME_UNREACHABLE("unexpected operand kind");
+            MOZ_CRASH("unexpected operand kind");
         }
     }
     void mulss(const Operand &src, FloatRegister dest) {
         JS_ASSERT(HasSSE2());
         switch (src.kind()) {
           case Operand::FPREG:
             masm.mulss_rr(src.fpu(), dest.code());
             break;
           case Operand::MEM_REG_DISP:
             masm.mulss_mr(src.disp(), src.base(), dest.code());
             break;
           default:
-            MOZ_ASSUME_UNREACHABLE("unexpected operand kind");
+            MOZ_CRASH("unexpected operand kind");
         }
     }
     void mulss(FloatRegister src, FloatRegister dest) {
         JS_ASSERT(HasSSE2());
         masm.mulss_rr(src.code(), dest.code());
     }
     void divsd(FloatRegister src, FloatRegister dest) {
         JS_ASSERT(HasSSE2());
@@ -1705,30 +1705,30 @@ class AssemblerX86Shared : public Assemb
         switch (src.kind()) {
           case Operand::FPREG:
             masm.divsd_rr(src.fpu(), dest.code());
             break;
           case Operand::MEM_REG_DISP:
             masm.divsd_mr(src.disp(), src.base(), dest.code());
             break;
           default:
-            MOZ_ASSUME_UNREACHABLE("unexpected operand kind");
+            MOZ_CRASH("unexpected operand kind");
         }
     }
     void divss(const Operand &src, FloatRegister dest) {
         JS_ASSERT(HasSSE2());
         switch (src.kind()) {
           case Operand::FPREG:
             masm.divss_rr(src.fpu(), dest.code());
             break;
           case Operand::MEM_REG_DISP:
             masm.divss_mr(src.disp(), src.base(), dest.code());
             break;
           default:
-            MOZ_ASSUME_UNREACHABLE("unexpected operand kind");
+            MOZ_CRASH("unexpected operand kind");
         }
     }
     void xorpd(FloatRegister src, FloatRegister dest) {
         JS_ASSERT(HasSSE2());
         masm.xorpd_rr(src.code(), dest.code());
     }
     void xorps(FloatRegister src, FloatRegister dest) {
         JS_ASSERT(HasSSE2());
@@ -1775,71 +1775,71 @@ class AssemblerX86Shared : public Assemb
         switch (src.kind()) {
           case Operand::FPREG:
             masm.minsd_rr(src.fpu(), dest.code());
             break;
           case Operand::MEM_REG_DISP:
             masm.minsd_mr(src.disp(), src.base(), dest.code());
             break;
           default:
-            MOZ_ASSUME_UNREACHABLE("unexpected operand kind");
+            MOZ_CRASH("unexpected operand kind");
         }
     }
     void maxsd(FloatRegister src, FloatRegister dest) {
         JS_ASSERT(HasSSE2());
         masm.maxsd_rr(src.code(), dest.code());
     }
     void maxsd(const Operand &src, FloatRegister dest) {
         JS_ASSERT(HasSSE2());
         switch (src.kind()) {
           case Operand::FPREG:
             masm.maxsd_rr(src.fpu(), dest.code());
             break;
           case Operand::MEM_REG_DISP:
             masm.maxsd_mr(src.disp(), src.base(), dest.code());
             break;
           default:
-            MOZ_ASSUME_UNREACHABLE("unexpected operand kind");
+            MOZ_CRASH("unexpected operand kind");
         }
     }
     void fisttp(const Operand &dest) {
         JS_ASSERT(HasSSE3());
         switch (dest.kind()) {
           case Operand::MEM_REG_DISP:
             masm.fisttp_m(dest.disp(), dest.base());
             break;
           default:
-            MOZ_ASSUME_UNREACHABLE("unexpected operand kind");
+            MOZ_CRASH("unexpected operand kind");
         }
     }
     void fld(const Operand &dest) {
         switch (dest.kind()) {
           case Operand::MEM_REG_DISP:
             masm.fld_m(dest.disp(), dest.base());
             break;
           default:
-            MOZ_ASSUME_UNREACHABLE("unexpected operand kind");
+            MOZ_CRASH("unexpected operand kind");
         }
     }
     void fstp(const Operand &src) {
         switch (src.kind()) {
           case Operand::MEM_REG_DISP:
             masm.fstp_m(src.disp(), src.base());
             break;
           default:
-            MOZ_ASSUME_UNREACHABLE("unexpected operand kind");
+            MOZ_CRASH("unexpected operand kind");
         }
     }
     void fstp32(const Operand &src) {
         switch (src.kind()) {
           case Operand::MEM_REG_DISP:
             masm.fstp32_m(src.disp(), src.base());
             break;
           default:
-            MOZ_ASSUME_UNREACHABLE("unexpected operand kind");
+            MOZ_CRASH("unexpected operand kind");
         }
     }
 
     // Defined for compatibility with ARM's assembler
     uint32_t actualOffset(uint32_t x) {
         return x;
     }
 
@@ -1880,24 +1880,24 @@ class AssemblerX86Shared : public Assemb
         JS_ASSERT(*ptr == (uintptr_t)expectedData.value);
         *ptr = (uintptr_t)newData.value;
     }
     static void PatchDataWithValueCheck(CodeLocationLabel data, ImmPtr newData, ImmPtr expectedData) {
         PatchDataWithValueCheck(data, PatchedImmPtr(newData.value), PatchedImmPtr(expectedData.value));
     }
 
     static void PatchInstructionImmediate(uint8_t *code, PatchedImmPtr imm) {
-        MOZ_ASSUME_UNREACHABLE("Unused.");
+        MOZ_CRASH("Unused.");
     }
 
     static uint32_t NopSize() {
         return 1;
     }
     static uint8_t *NextInstruction(uint8_t *cur, uint32_t *count) {
-        MOZ_ASSUME_UNREACHABLE("nextInstruction NYI on x86");
+        MOZ_CRASH("nextInstruction NYI on x86");
     }
 
     // Toggle a jmp or cmp emitted by toggledJump().
     static void ToggleToJmp(CodeLocationLabel inst) {
         uint8_t *ptr = (uint8_t *)inst.raw();
         JS_ASSERT(*ptr == 0x3D);
         *ptr = 0xE9;
     }
--- a/js/src/jit/shared/CodeGenerator-x86-shared.cpp
+++ b/js/src/jit/shared/CodeGenerator-x86-shared.cpp
@@ -1333,17 +1333,17 @@ CodeGeneratorX86Shared::visitBitOpI(LBit
             break;
         case JSOP_BITAND:
             if (rhs->isConstant())
                 masm.andl(Imm32(ToInt32(rhs)), ToOperand(lhs));
             else
                 masm.andl(ToOperand(rhs), ToRegister(lhs));
             break;
         default:
-            MOZ_ASSUME_UNREACHABLE("unexpected binary opcode");
+            MOZ_CRASH("unexpected binary opcode");
     }
 
     return true;
 }
 
 bool
 CodeGeneratorX86Shared::visitShiftI(LShiftI *ins)
 {
@@ -1367,17 +1367,17 @@ CodeGeneratorX86Shared::visitShiftI(LShi
             } else if (ins->mir()->toUrsh()->fallible()) {
                 // x >>> 0 can overflow.
                 masm.testl(lhs, lhs);
                 if (!bailoutIf(Assembler::Signed, ins->snapshot()))
                     return false;
             }
             break;
           default:
-            MOZ_ASSUME_UNREACHABLE("Unexpected shift op");
+            MOZ_CRASH("Unexpected shift op");
         }
     } else {
         JS_ASSERT(ToRegister(rhs) == ecx);
         switch (ins->bitop()) {
           case JSOP_LSH:
             masm.shll_cl(lhs);
             break;
           case JSOP_RSH:
@@ -1388,17 +1388,17 @@ CodeGeneratorX86Shared::visitShiftI(LShi
             if (ins->mir()->toUrsh()->fallible()) {
                 // x >>> 0 can overflow.
                 masm.testl(lhs, lhs);
                 if (!bailoutIf(Assembler::Signed, ins->snapshot()))
                     return false;
             }
             break;
           default:
-            MOZ_ASSUME_UNREACHABLE("Unexpected shift op");
+            MOZ_CRASH("Unexpected shift op");
         }
     }
 
     return true;
 }
 
 bool
 CodeGeneratorX86Shared::visitUrshD(LUrshD *ins)
@@ -1530,17 +1530,17 @@ CodeGeneratorX86Shared::visitMathD(LMath
         break;
       case JSOP_MUL:
         masm.mulsd(rhs, lhs);
         break;
       case JSOP_DIV:
         masm.divsd(rhs, lhs);
         break;
       default:
-        MOZ_ASSUME_UNREACHABLE("unexpected opcode");
+        MOZ_CRASH("unexpected opcode");
     }
     return true;
 }
 
 bool
 CodeGeneratorX86Shared::visitMathF(LMathF *math)
 {
     FloatRegister lhs = ToFloatRegister(math->lhs());
@@ -1557,18 +1557,17 @@ CodeGeneratorX86Shared::visitMathF(LMath
         break;
       case JSOP_MUL:
         masm.mulss(rhs, lhs);
         break;
       case JSOP_DIV:
         masm.divss(rhs, lhs);
         break;
       default:
-        MOZ_ASSUME_UNREACHABLE("unexpected opcode");
-        return false;
+        MOZ_CRASH("unexpected opcode");
     }
     return true;
 }
 
 bool
 CodeGeneratorX86Shared::visitFloor(LFloor *lir)
 {
     FloatRegister input = ToFloatRegister(lir->input());
@@ -2104,17 +2103,17 @@ CodeGeneratorX86Shared::visitSimdValueX4
       case MIRType_Float32x4: {
         for (size_t i = 0; i < 4; ++i) {
             FloatRegister r = ToFloatRegister(ins->getOperand(i));
             masm.storeFloat32(r, Address(StackPointer, i * sizeof(float)));
         }
         masm.loadAlignedFloat32x4(Address(StackPointer, 0), output);
         break;
       }
-      default: MOZ_ASSUME_UNREACHABLE("Unknown SIMD kind");
+      default: MOZ_CRASH("Unknown SIMD kind");
     }
 
     masm.freeStack(Simd128DataSize);
     return true;
 }
 
 bool
 CodeGeneratorX86Shared::visitSimdExtractElementI(LSimdExtractElementI *ins)
@@ -2172,17 +2171,17 @@ CodeGeneratorX86Shared::visitSimdBinaryA
         return true;
       case MSimdBinaryArith::Mul:
         // we can do mul with a single instruction only if we have SSE4.1
         // using the PMULLD instruction.
       case MSimdBinaryArith::Div:
         // x86 doesn't have SIMD i32 div.
         break;
     }
-    MOZ_ASSUME_UNREACHABLE("unexpected SIMD op");
+    MOZ_CRASH("unexpected SIMD op");
 }
 
 bool
 CodeGeneratorX86Shared::visitSimdBinaryArithFx4(LSimdBinaryArithFx4 *ins)
 {
     FloatRegister lhs = ToFloatRegister(ins->lhs());
     Operand rhs = ToOperand(ins->rhs());
     JS_ASSERT(ToFloatRegister(ins->output()) == lhs);
@@ -2197,17 +2196,17 @@ CodeGeneratorX86Shared::visitSimdBinaryA
         return true;
       case MSimdBinaryArith::Mul:
         masm.packedMulFloat32(rhs, lhs);
         return true;
       case MSimdBinaryArith::Div:
         masm.packedDivFloat32(rhs, lhs);
         return true;
     }
-    MOZ_ASSUME_UNREACHABLE("unexpected SIMD op");
+    MOZ_CRASH("unexpected SIMD op");
 }
 
 bool
 CodeGeneratorX86Shared::visitForkJoinGetSlice(LForkJoinGetSlice *ins)
 {
     MOZ_ASSERT(gen->info().executionMode() == ParallelExecution);
     MOZ_ASSERT(ToRegister(ins->forkJoinContext()) == ForkJoinGetSliceReg_cx);
     MOZ_ASSERT(ToRegister(ins->temp1()) == eax);
--- a/js/src/jit/shared/MacroAssembler-x86-shared.h
+++ b/js/src/jit/shared/MacroAssembler-x86-shared.h
@@ -397,17 +397,17 @@ class MacroAssemblerX86Shared : public A
         switch (src.kind()) {
           case Operand::MEM_REG_DISP:
             loadDouble(src.toAddress(), dest);
             break;
           case Operand::MEM_SCALE:
             loadDouble(src.toBaseIndex(), dest);
             break;
           default:
-            MOZ_ASSUME_UNREACHABLE("unexpected operand kind");
+            MOZ_CRASH("unexpected operand kind");
         }
     }
     void storeDouble(FloatRegister src, const Address &dest) {
         movsd(src, dest);
     }
     void storeDouble(FloatRegister src, const BaseIndex &dest) {
         movsd(src, dest);
     }
@@ -415,17 +415,17 @@ class MacroAssemblerX86Shared : public A
         switch (dest.kind()) {
           case Operand::MEM_REG_DISP:
             storeDouble(src, dest.toAddress());
             break;
           case Operand::MEM_SCALE:
             storeDouble(src, dest.toBaseIndex());
             break;
           default:
-            MOZ_ASSUME_UNREACHABLE("unexpected operand kind");
+            MOZ_CRASH("unexpected operand kind");
         }
     }
     void moveDouble(FloatRegister src, FloatRegister dest) {
         // Use movapd instead of movsd to avoid dependencies.
         movapd(src, dest);
     }
     void zeroDouble(FloatRegister reg) {
         xorpd(reg, reg);
@@ -575,17 +575,17 @@ class MacroAssemblerX86Shared : public A
         switch (src.kind()) {
           case Operand::MEM_REG_DISP:
             loadFloat32(src.toAddress(), dest);
             break;
           case Operand::MEM_SCALE:
             loadFloat32(src.toBaseIndex(), dest);
             break;
           default:
-            MOZ_ASSUME_UNREACHABLE("unexpected operand kind");
+            MOZ_CRASH("unexpected operand kind");
         }
     }
     void storeFloat32(FloatRegister src, const Address &dest) {
         movss(src, dest);
     }
     void storeFloat32(FloatRegister src, const BaseIndex &dest) {
         movss(src, dest);
     }
@@ -593,17 +593,17 @@ class MacroAssemblerX86Shared : public A
         switch (dest.kind()) {
           case Operand::MEM_REG_DISP:
             storeFloat32(src, dest.toAddress());
             break;
           case Operand::MEM_SCALE:
             storeFloat32(src, dest.toBaseIndex());
             break;
           default:
-            MOZ_ASSUME_UNREACHABLE("unexpected operand kind");
+            MOZ_CRASH("unexpected operand kind");
         }
     }
     void moveFloat32(FloatRegister src, FloatRegister dest) {
         // Use movaps instead of movss to avoid dependencies.
         movaps(src, dest);
     }
 
     // Checks whether a double is representable as a 32-bit integer. If so, the
--- a/js/src/jit/shared/MoveEmitter-x86-shared.cpp
+++ b/js/src/jit/shared/MoveEmitter-x86-shared.cpp
@@ -143,17 +143,17 @@ MoveEmitterX86::emit(const MoveResolver 
             break;
           case MoveOp::INT32X4:
             emitInt32X4Move(from, to);
             break;
           case MoveOp::FLOAT32X4:
             emitFloat32X4Move(from, to);
             break;
           default:
-            MOZ_ASSUME_UNREACHABLE("Unexpected move type");
+            MOZ_CRASH("Unexpected move type");
         }
     }
 }
 
 MoveEmitterX86::~MoveEmitterX86()
 {
     assertDone();
 }
@@ -273,17 +273,17 @@ MoveEmitterX86::breakCycle(const MoveOpe
             masm.store32(to.reg(), cycleSlot());
         }
         break;
 #endif
       case MoveOp::GENERAL:
         masm.Push(toOperand(to));
         break;
       default:
-        MOZ_ASSUME_UNREACHABLE("Unexpected move type");
+        MOZ_CRASH("Unexpected move type");
     }
 }
 
 void
 MoveEmitterX86::completeCycle(const MoveOperand &to, MoveOp::Type type)
 {
     // There is some pattern:
     //   (A -> B)
@@ -345,17 +345,17 @@ MoveEmitterX86::completeCycle(const Move
         }
         break;
 #endif
       case MoveOp::GENERAL:
         JS_ASSERT(masm.framePushed() - pushedAtStart_ >= sizeof(intptr_t));
         masm.Pop(toPopOperand(to));
         break;
       default:
-        MOZ_ASSUME_UNREACHABLE("Unexpected move type");
+        MOZ_CRASH("Unexpected move type");
     }
 }
 
 void
 MoveEmitterX86::emitInt32Move(const MoveOperand &from, const MoveOperand &to)
 {
     if (from.isGeneralReg()) {
         masm.move32(from.reg(), toOperand(to));
--- a/js/src/jit/x64/Assembler-x64.cpp
+++ b/js/src/jit/x64/Assembler-x64.cpp
@@ -39,17 +39,17 @@ ABIArgGenerator::next(MIRType type)
       case MIRType_Pointer:
         current_ = ABIArg(IntArgRegs[regIndex_++]);
         break;
       case MIRType_Float32:
       case MIRType_Double:
         current_ = ABIArg(FloatArgRegs[regIndex_++]);
         break;
       default:
-        MOZ_ASSUME_UNREACHABLE("Unexpected argument type");
+        MOZ_CRASH("Unexpected argument type");
     }
     return current_;
 #else
     switch (type) {
       case MIRType_Int32:
       case MIRType_Pointer:
         if (intRegIndex_ == NumIntArgRegs) {
             current_ = ABIArg(stackOffset_);
@@ -63,17 +63,17 @@ ABIArgGenerator::next(MIRType type)
         if (floatRegIndex_ == NumFloatArgRegs) {
             current_ = ABIArg(stackOffset_);
             stackOffset_ += sizeof(uint64_t);
             break;
         }
         current_ = ABIArg(FloatArgRegs[floatRegIndex_++]);
         break;
       default:
-        MOZ_ASSUME_UNREACHABLE("Unexpected argument type");
+        MOZ_CRASH("Unexpected argument type");
     }
     return current_;
 #endif
 }
 
 // Avoid r11, which is the MacroAssembler's ScratchReg.
 const Register ABIArgGenerator::NonArgReturnReg0 = r10;
 const Register ABIArgGenerator::NonArgReturnReg1 = r12;
--- a/js/src/jit/x64/Assembler-x64.h
+++ b/js/src/jit/x64/Assembler-x64.h
@@ -353,17 +353,17 @@ class Assembler : public AssemblerX86Sha
             break;
           case Operand::MEM_SCALE:
             masm.movq_mr(src.disp(), src.base(), src.index(), src.scale(), dest.code());
             break;
           case Operand::MEM_ADDRESS32:
             masm.movq_mr(src.address(), dest.code());
             break;
           default:
-            MOZ_ASSUME_UNREACHABLE("unexpected operand kind");
+            MOZ_CRASH("unexpected operand kind");
         }
     }
     void movq(Register src, const Operand &dest) {
         switch (dest.kind()) {
           case Operand::REG:
             masm.movq_rr(src.code(), dest.reg());
             break;
           case Operand::MEM_REG_DISP:
@@ -371,17 +371,17 @@ class Assembler : public AssemblerX86Sha
             break;
           case Operand::MEM_SCALE:
             masm.movq_rm(src.code(), dest.disp(), dest.base(), dest.index(), dest.scale());
             break;
           case Operand::MEM_ADDRESS32:
             masm.movq_rm(src.code(), dest.address());
             break;
           default:
-            MOZ_ASSUME_UNREACHABLE("unexpected operand kind");
+            MOZ_CRASH("unexpected operand kind");
         }
     }
     void movq(Imm32 imm32, const Operand &dest) {
         switch (dest.kind()) {
           case Operand::REG:
             masm.movl_i32r(imm32.value, dest.reg());
             break;
           case Operand::MEM_REG_DISP:
@@ -389,17 +389,17 @@ class Assembler : public AssemblerX86Sha
             break;
           case Operand::MEM_SCALE:
             masm.movq_i32m(imm32.value, dest.disp(), dest.base(), dest.index(), dest.scale());
             break;
           case Operand::MEM_ADDRESS32:
             masm.movq_i32m(imm32.value, dest.address());
             break;
           default:
-            MOZ_ASSUME_UNREACHABLE("unexpected operand kind");
+            MOZ_CRASH("unexpected operand kind");
         }
     }
     void movq(Register src, FloatRegister dest) {
         masm.movq_rr(src.code(), dest.code());
     }
     void movq(FloatRegister src, Register dest) {
         masm.movq_rr(src.code(), dest.code());
     }
@@ -427,17 +427,17 @@ class Assembler : public AssemblerX86Sha
             break;
           case Operand::MEM_SCALE:
             masm.andq_mr(src.disp(), src.base(), src.index(), src.scale(), dest.code());
             break;
           case Operand::MEM_ADDRESS32:
             masm.andq_mr(src.address(), dest.code());
             break;
           default:
-            MOZ_ASSUME_UNREACHABLE("unexpected operand kind");
+            MOZ_CRASH("unexpected operand kind");
         }
     }
 
     void addq(Imm32 imm, Register dest) {
         masm.addq_ir(imm.value, dest.code());
     }
     void addq(Imm32 imm, const Operand &dest) {
         switch (dest.kind()) {
@@ -446,17 +446,17 @@ class Assembler : public AssemblerX86Sha
             break;
           case Operand::MEM_REG_DISP:
             masm.addq_im(imm.value, dest.disp(), dest.base());
             break;
           case Operand::MEM_ADDRESS32:
             masm.addq_im(imm.value, dest.address());
             break;
           default:
-            MOZ_ASSUME_UNREACHABLE("unexpected operand kind");
+            MOZ_CRASH("unexpected operand kind");
         }
     }
     void addq(Register src, Register dest) {
         masm.addq_rr(src.code(), dest.code());
     }
     void addq(const Operand &src, Register dest) {
         switch (src.kind()) {
           case Operand::REG:
@@ -464,17 +464,17 @@ class Assembler : public AssemblerX86Sha
             break;
           case Operand::MEM_REG_DISP:
             masm.addq_mr(src.disp(), src.base(), dest.code());
             break;
           case Operand::MEM_ADDRESS32:
             masm.addq_mr(src.address(), dest.code());
             break;
           default:
-            MOZ_ASSUME_UNREACHABLE("unexpected operand kind");
+            MOZ_CRASH("unexpected operand kind");
         }
     }
 
     void subq(Imm32 imm, Register dest) {
         masm.subq_ir(imm.value, dest.code());
     }
     void subq(Register src, Register dest) {
         masm.subq_rr(src.code(), dest.code());
@@ -486,29 +486,29 @@ class Assembler : public AssemblerX86Sha
             break;
           case Operand::MEM_REG_DISP:
             masm.subq_mr(src.disp(), src.base(), dest.code());
             break;
           case Operand::MEM_ADDRESS32:
             masm.subq_mr(src.address(), dest.code());
             break;
           default:
-            MOZ_ASSUME_UNREACHABLE("unexpected operand kind");
+            MOZ_CRASH("unexpected operand kind");
         }
     }
     void subq(Register src, const Operand &dest) {
         switch (dest.kind()) {
           case Operand::REG:
             masm.subq_rr(src.code(), dest.reg());
             break;
           case Operand::MEM_REG_DISP:
             masm.subq_rm(src.code(), dest.disp(), dest.base());
             break;
           default:
-            MOZ_ASSUME_UNREACHABLE("unexpected operand kind");
+            MOZ_CRASH("unexpected operand kind");
         }
     }
     void shlq(Imm32 imm, Register dest) {
         masm.shlq_i8r(imm.value, dest.code());
     }
     void shrq(Imm32 imm, Register dest) {
         masm.shrq_i8r(imm.value, dest.code());
     }
@@ -528,17 +528,17 @@ class Assembler : public AssemblerX86Sha
             break;
           case Operand::MEM_REG_DISP:
             masm.orq_mr(src.disp(), src.base(), dest.code());
             break;
           case Operand::MEM_ADDRESS32:
             masm.orq_mr(src.address(), dest.code());
             break;
           default:
-            MOZ_ASSUME_UNREACHABLE("unexpected operand kind");
+            MOZ_CRASH("unexpected operand kind");
         }
     }
     void xorq(Register src, Register dest) {
         masm.xorq_rr(src.code(), dest.code());
     }
     void xorq(Imm32 imm, Register dest) {
         masm.xorq_ir(imm.value, dest.code());
     }
@@ -587,17 +587,17 @@ class Assembler : public AssemblerX86Sha
         switch (src.kind()) {
           case Operand::MEM_REG_DISP:
             masm.leaq_mr(src.disp(), src.base(), dest.code());
             break;
           case Operand::MEM_SCALE:
             masm.leaq_mr(src.disp(), src.base(), src.index(), src.scale(), dest.code());
             break;
           default:
-            MOZ_ASSUME_UNREACHABLE("unexepcted operand kind");
+            MOZ_CRASH("unexepcted operand kind");
         }
     }
 
     CodeOffsetLabel loadRipRelativeInt32(Register dest) {
         return CodeOffsetLabel(masm.movl_ripr(dest.code()).offset());
     }
     CodeOffsetLabel loadRipRelativeInt64(Register dest) {
         return CodeOffsetLabel(masm.movq_ripr(dest.code()).offset());
@@ -630,44 +630,44 @@ class Assembler : public AssemblerX86Sha
             break;
           case Operand::MEM_REG_DISP:
             masm.cmpq_rm(rhs.code(), lhs.disp(), lhs.base());
             break;
           case Operand::MEM_ADDRESS32:
             masm.cmpq_rm(rhs.code(), lhs.address());
             break;
           default:
-            MOZ_ASSUME_UNREACHABLE("unexpected operand kind");
+            MOZ_CRASH("unexpected operand kind");
         }
     }
     void cmpq(const Operand &lhs, Imm32 rhs) {
         switch (lhs.kind()) {
           case Operand::REG:
             masm.cmpq_ir(rhs.value, lhs.reg());
             break;
           case Operand::MEM_REG_DISP:
             masm.cmpq_im(rhs.value, lhs.disp(), lhs.base());
             break;
           case Operand::MEM_ADDRESS32:
             masm.cmpq_im(rhs.value, lhs.address());
             break;
           default:
-            MOZ_ASSUME_UNREACHABLE("unexpected operand kind");
+            MOZ_CRASH("unexpected operand kind");
         }
     }
     void cmpq(Register lhs, const Operand &rhs) {
         switch (rhs.kind()) {
           case Operand::REG:
             masm.cmpq_rr(rhs.reg(), lhs.code());
             break;
           case Operand::MEM_REG_DISP:
             masm.cmpq_mr(rhs.disp(), rhs.base(), lhs.code());
             break;
           default:
-            MOZ_ASSUME_UNREACHABLE("unexpected operand kind");
+            MOZ_CRASH("unexpected operand kind");
         }
     }
     void cmpq(Register lhs, Register rhs) {
         masm.cmpq_rr(rhs.code(), lhs.code());
     }
     void cmpq(Register lhs, Imm32 rhs) {
         masm.cmpq_ir(rhs.value, lhs.code());
     }
@@ -682,17 +682,17 @@ class Assembler : public AssemblerX86Sha
         switch (lhs.kind()) {
           case Operand::REG:
             masm.testq_i32r(rhs.value, lhs.reg());
             break;
           case Operand::MEM_REG_DISP:
             masm.testq_i32m(rhs.value, lhs.disp(), lhs.base());
             break;
           default:
-            MOZ_ASSUME_UNREACHABLE("unexpected operand kind");
+            MOZ_CRASH("unexpected operand kind");
             break;
         }
     }
 
     void jmp(ImmPtr target, Relocation::Kind reloc = Relocation::HARDCODED) {
         JmpSrc src = masm.jmp();
         addPendingJump(src, target, reloc);
     }
--- a/js/src/jit/x64/Bailouts-x64.cpp
+++ b/js/src/jit/x64/Bailouts-x64.cpp
@@ -55,17 +55,17 @@ IonBailoutIterator::IonBailoutIterator(c
 
     kind_ = Kind_BailoutIterator;
     current_ = fp;
     type_ = JitFrame_IonJS;
     topFrameSize_ = current_ - sp;
     switch (mode_) {
       case SequentialExecution: topIonScript_ = script()->ionScript(); break;
       case ParallelExecution: topIonScript_ = script()->parallelIonScript(); break;
-      default: MOZ_ASSUME_UNREACHABLE("No such execution mode");
+      default: MOZ_CRASH("No such execution mode");
     }
     snapshotOffset_ = bailout->snapshotOffset();
 }
 
 IonBailoutIterator::IonBailoutIterator(const JitActivationIterator &activations,
                                        InvalidationBailoutStack *bailout)
   : JitFrameIterator(activations),
     machine_(bailout->machine())
--- a/js/src/jit/x64/BaselineIC-x64.cpp
+++ b/js/src/jit/x64/BaselineIC-x64.cpp
@@ -179,17 +179,17 @@ ICBinaryArith_Int32::Compiler::generateS
             masm.convertUInt32ToDouble(ExtractTemp0, ScratchDoubleReg);
             masm.boxDouble(ScratchDoubleReg, R0);
         } else {
             masm.j(Assembler::Signed, &revertRegister);
             masm.boxValue(JSVAL_TYPE_INT32, ExtractTemp0, R0.valueReg());
         }
         break;
       default:
-        MOZ_ASSUME_UNREACHABLE("Unhandled op in BinaryArith_Int32");
+        MOZ_CRASH("Unhandled op in BinaryArith_Int32");
     }
 
     // Return from stub.
     EmitReturnFromIC(masm);
 
     if (op_ == JSOP_MUL) {
         masm.bind(&maybeNegZero);
 
@@ -228,17 +228,17 @@ ICUnaryArith_Int32::Compiler::generateSt
         masm.notl(R0.valueReg());
         break;
       case JSOP_NEG:
         // Guard against 0 and MIN_INT, both result in a double.
         masm.branchTest32(Assembler::Zero, R0.valueReg(), Imm32(0x7fffffff), &failure);
         masm.negl(R0.valueReg());
         break;
       default:
-        MOZ_ASSUME_UNREACHABLE("Unexpected op");
+        MOZ_CRASH("Unexpected op");
     }
 
     masm.tagValue(JSVAL_TYPE_INT32, R0.valueReg(), R0);
 
     EmitReturnFromIC(masm);
 
     masm.bind(&failure);
     EmitStubGuardFailure(masm);
--- a/js/src/jit/x64/CodeGenerator-x64.cpp
+++ b/js/src/jit/x64/CodeGenerator-x64.cpp
@@ -49,17 +49,17 @@ FrameSizeClass
 FrameSizeClass::ClassLimit()
 {
     return FrameSizeClass(0);
 }
 
 uint32_t
 FrameSizeClass::frameSize() const
 {
-    MOZ_ASSUME_UNREACHABLE("x64 does not use frame size classes");
+    MOZ_CRASH("x64 does not use frame size classes");
 }
 
 bool
 CodeGeneratorX64::visitValue(LValue *value)
 {
     LDefinition *reg = value->getDef(0);
     masm.moveValue(value->value(), ToRegister(reg));
     return true;
@@ -105,17 +105,17 @@ CodeGeneratorX64::visitUnbox(LUnbox *unb
             break;
           case MIRType_String:
             cond = masm.testString(Assembler::NotEqual, value);
             break;
           case MIRType_Symbol:
             cond = masm.testSymbol(Assembler::NotEqual, value);
             break;
           default:
-            MOZ_ASSUME_UNREACHABLE("Given MIRType cannot be unboxed.");
+            MOZ_CRASH("Given MIRType cannot be unboxed.");
         }
         if (!bailoutIf(cond, unbox->snapshot()))
             return false;
     }
 
     switch (mir->type()) {
       case MIRType_Int32:
         masm.unboxInt32(value, ToRegister(result));
@@ -128,17 +128,17 @@ CodeGeneratorX64::visitUnbox(LUnbox *unb
         break;
       case MIRType_String:
         masm.unboxString(value, ToRegister(result));
         break;
       case MIRType_Symbol:
         masm.unboxSymbol(value, ToRegister(result));
         break;
       default:
-        MOZ_ASSUME_UNREACHABLE("Given MIRType cannot be unboxed.");
+        MOZ_CRASH("Given MIRType cannot be unboxed.");
     }
 
     return true;
 }
 
 bool
 CodeGeneratorX64::visitCompareB(LCompareB *lir)
 {
@@ -226,23 +226,23 @@ CodeGeneratorX64::visitAsmJSUInt32ToFloa
 {
     masm.convertUInt32ToFloat32(ToRegister(lir->input()), ToFloatRegister(lir->output()));
     return true;
 }
 
 bool
 CodeGeneratorX64::visitLoadTypedArrayElementStatic(LLoadTypedArrayElementStatic *ins)
 {
-    MOZ_ASSUME_UNREACHABLE("NYI");
+    MOZ_CRASH("NYI");
 }
 
 bool
 CodeGeneratorX64::visitStoreTypedArrayElementStatic(LStoreTypedArrayElementStatic *ins)
 {
-    MOZ_ASSUME_UNREACHABLE("NYI");
+    MOZ_CRASH("NYI");
 }
 
 bool
 CodeGeneratorX64::visitAsmJSLoadHeap(LAsmJSLoadHeap *ins)
 {
     MAsmJSLoadHeap *mir = ins->mir();
     Scalar::Type vt = mir->viewType();
     const LAllocation *ptr = ins->ptr();
@@ -275,17 +275,17 @@ CodeGeneratorX64::visitAsmJSLoadHeap(LAs
       case Scalar::Int8:    masm.movsbl(srcAddr, ToRegister(out)); break;
       case Scalar::Uint8:   masm.movzbl(srcAddr, ToRegister(out)); break;
       case Scalar::Int16:   masm.movswl(srcAddr, ToRegister(out)); break;
       case Scalar::Uint16:  masm.movzwl(srcAddr, ToRegister(out)); break;
       case Scalar::Int32:
       case Scalar::Uint32:  masm.movl(srcAddr, ToRegister(out)); break;
       case Scalar::Float32: masm.loadFloat32(srcAddr, ToFloatRegister(out)); break;
       case Scalar::Float64: masm.loadDouble(srcAddr, ToFloatRegister(out)); break;
-      default: MOZ_ASSUME_UNREACHABLE("unexpected array type");
+      default: MOZ_CRASH("unexpected array type");
     }
     uint32_t after = masm.size();
     if (ool)
         masm.bind(ool->rejoin());
     masm.append(AsmJSHeapAccess(before, after, vt, ToAnyRegister(out), maybeCmpOffset));
     return true;
 }
 
@@ -317,29 +317,29 @@ CodeGeneratorX64::visitAsmJSStoreHeap(LA
     if (ins->value()->isConstant()) {
         switch (vt) {
           case Scalar::Int8:
           case Scalar::Uint8:   masm.movb(Imm32(ToInt32(ins->value())), dstAddr); break;
           case Scalar::Int16:
           case Scalar::Uint16:  masm.movw(Imm32(ToInt32(ins->value())), dstAddr); break;
           case Scalar::Int32:
           case Scalar::Uint32:  masm.movl(Imm32(ToInt32(ins->value())), dstAddr); break;
-          default: MOZ_ASSUME_UNREACHABLE("unexpected array type");
+          default: MOZ_CRASH("unexpected array type");
         }
     } else {
         switch (vt) {
           case Scalar::Int8:
           case Scalar::Uint8:   masm.movb(ToRegister(ins->value()), dstAddr); break;
           case Scalar::Int16:
           case Scalar::Uint16:  masm.movw(ToRegister(ins->value()), dstAddr); break;
           case Scalar::Int32:
           case Scalar::Uint32:  masm.movl(ToRegister(ins->value()), dstAddr); break;
           case Scalar::Float32: masm.storeFloat32(ToFloatRegister(ins->value()), dstAddr); break;
           case Scalar::Float64: masm.storeDouble(ToFloatRegister(ins->value()), dstAddr); break;
-          default: MOZ_ASSUME_UNREACHABLE("unexpected array type");
+          default: MOZ_CRASH("unexpected array type");
         }
     }
     uint32_t after = masm.size();
     if (rejoin.used())
         masm.bind(&rejoin);
     masm.append(AsmJSHeapAccess(before, after, maybeCmpOffset));
     return true;
 }
--- a/js/src/jit/x64/Lowering-x64.cpp
+++ b/js/src/jit/x64/Lowering-x64.cpp
@@ -172,25 +172,25 @@ LIRGeneratorX64::visitAsmJSStoreHeap(MAs
       case Scalar::Uint32:
         lir = new(alloc()) LAsmJSStoreHeap(ptrAlloc, useRegisterOrConstantAtStart(ins->value()));
         break;
       case Scalar::Float32:
       case Scalar::Float64:
         lir = new(alloc()) LAsmJSStoreHeap(ptrAlloc, useRegisterAtStart(ins->value()));
         break;
       default:
-        MOZ_ASSUME_UNREACHABLE("unexpected array type");
+        MOZ_CRASH("unexpected array type");
     }
 
     return add(lir, ins);
 }
 
 bool
 LIRGeneratorX64::visitAsmJSLoadFuncPtr(MAsmJSLoadFuncPtr *ins)
 {
     return define(new(alloc()) LAsmJSLoadFuncPtr(useRegister(ins->index()), temp()), ins);
 }
 
 bool
 LIRGeneratorX64::visitStoreTypedArrayElementStatic(MStoreTypedArrayElementStatic *ins)
 {
-    MOZ_ASSUME_UNREACHABLE("NYI");
+    MOZ_CRASH("NYI");
 }
--- a/js/src/jit/x64/MacroAssembler-x64.cpp
+++ b/js/src/jit/x64/MacroAssembler-x64.cpp
@@ -162,17 +162,17 @@ MacroAssemblerX64::finish()
     if (!simds_.empty())
         masm.align(SimdStackAlignment);
     for (size_t i = 0; i < simds_.length(); i++) {
         SimdData &v = simds_[i];
         bind(&v.uses);
         switch(v.type()) {
           case SimdConstant::Int32x4:   masm.int32x4Constant(v.value.asInt32x4());     break;
           case SimdConstant::Float32x4: masm.float32x4Constant(v.value.asFloat32x4()); break;
-          default: MOZ_ASSUME_UNREACHABLE("unexpected SimdConstant type");
+          default: MOZ_CRASH("unexpected SimdConstant type");
         }
     }
 
     MacroAssemblerX86Shared::finish();
 }
 
 void
 MacroAssemblerX64::setupABICall(uint32_t args)
@@ -218,17 +218,17 @@ MacroAssemblerX64::passABIArg(const Move
                 return;
             }
             to = MoveOperand(dest);
         } else {
             to = MoveOperand(StackPointer, stackForCall_);
             switch (type) {
               case MoveOp::FLOAT32: stackForCall_ += sizeof(float);  break;
               case MoveOp::DOUBLE:  stackForCall_ += sizeof(double); break;
-              default: MOZ_ASSUME_UNREACHABLE("Unexpected float register class argument type");
+              default: MOZ_CRASH("Unexpected float register class argument type");
             }
         }
         break;
       }
       case MoveOp::GENERAL: {
         Register dest;
         if (GetIntArgReg(passedIntArgs_++, passedFloatArgs_, &dest)) {
             if (from.isGeneralReg() && from.reg() == dest) {
@@ -238,17 +238,17 @@ MacroAssemblerX64::passABIArg(const Move
             to = MoveOperand(dest);
         } else {
             to = MoveOperand(StackPointer, stackForCall_);
             stackForCall_ += sizeof(int64_t);
         }
         break;
       }
       default:
-        MOZ_ASSUME_UNREACHABLE("Unexpected argument type");
+        MOZ_CRASH("Unexpected argument type");
     }
 
     enoughMemory_ = moveResolver_.addMove(from, to, type);
 }
 
 void
 MacroAssemblerX64::passABIArg(Register reg)
 {
--- a/js/src/jit/x64/MacroAssembler-x64.h
+++ b/js/src/jit/x64/MacroAssembler-x64.h
@@ -119,17 +119,17 @@ class MacroAssemblerX64 : public MacroAs
           case Operand::MEM_REG_DISP:
             return Operand(Register::FromCode(base.base()), base.disp() + 4);
 
           case Operand::MEM_SCALE:
             return Operand(Register::FromCode(base.base()), Register::FromCode(base.index()),
                            base.scale(), base.disp() + 4);
 
           default:
-            MOZ_ASSUME_UNREACHABLE("unexpected operand kind");
+            MOZ_CRASH("unexpected operand kind");
         }
     }
     static inline Operand ToUpper32(const Address &address) {
         return Operand(address.base, address.offset + 4);
     }
     static inline Operand ToUpper32(const BaseIndex &address) {
         return Operand(address.base, address.index, address.scale, address.offset + 4);
     }
--- a/js/src/jit/x64/Trampoline-x64.cpp
+++ b/js/src/jit/x64/Trampoline-x64.cpp
@@ -514,33 +514,33 @@ GenerateParallelBailoutThunk(MacroAssemb
     masm.moveValue(MagicValue(JS_ION_ERROR), JSReturnOperand);
     masm.loadPtr(Address(rsp, 0), rsp);
     masm.ret();
 }
 
 JitCode *
 JitRuntime::generateBailoutTable(JSContext *cx, uint32_t frameClass)
 {
-    MOZ_ASSUME_UNREACHABLE("x64 does not use bailout tables");
+    MOZ_CRASH("x64 does not use bailout tables");
 }
 
 JitCode *
 JitRuntime::generateBailoutHandler(JSContext *cx, ExecutionMode mode)
 {
     MacroAssembler masm;
 
     switch (mode) {
       case SequentialExecution:
         GenerateBailoutThunk(cx, masm, NO_FRAME_SIZE_CLASS_ID);
         break;
       case ParallelExecution:
         GenerateParallelBailoutThunk(masm);
         break;
       default:
-        MOZ_ASSUME_UNREACHABLE("No such execution mode");
+        MOZ_CRASH("No such execution mode");
     }
 
     Linker linker(masm);
     JitCode *code = linker.newCode<NoGC>(cx, OTHER_CODE);
 
 #ifdef JS_ION_PERF
     writePerfSpewerJitCodeProfile(code, "BailoutHandler");
 #endif
@@ -646,17 +646,17 @@ JitRuntime::generateVMWrapper(JSContext 
             break;
           case VMFunction::WordByRef:
             masm.passABIArg(MoveOperand(argsBase, argDisp, MoveOperand::EFFECTIVE_ADDRESS),
                             MoveOp::GENERAL);
             argDisp += sizeof(void *);
             break;
           case VMFunction::DoubleByValue:
           case VMFunction::DoubleByRef:
-            MOZ_ASSUME_UNREACHABLE("NYI: x64 callVM should not be used with 128bits values.");
+            MOZ_CRASH("NYI: x64 callVM should not be used with 128bits values.");
         }
     }
 
     // Copy the implicit outparam, if any.
     if (outReg != InvalidReg)
         masm.passABIArg(outReg);
 
     masm.callWithABI(f.wrapped);
@@ -666,17 +666,17 @@ JitRuntime::generateVMWrapper(JSContext 
       case Type_Object:
         masm.branchTestPtr(Assembler::Zero, rax, rax, masm.failureLabel(f.executionMode));
         break;
       case Type_Bool:
         masm.testb(rax, rax);
         masm.j(Assembler::Zero, masm.failureLabel(f.executionMode));
         break;
       default:
-        MOZ_ASSUME_UNREACHABLE("unknown failure kind");
+        MOZ_CRASH("unknown failure kind");
     }
 
     // Load the outparam and free any allocated stack.
     switch (f.outParam) {
       case Type_Handle:
         masm.popRooted(f.outParamRootType, ReturnReg, JSReturnOperand);
         break;
 
--- a/js/src/jit/x86/MacroAssembler-x86.cpp
+++ b/js/src/jit/x86/MacroAssembler-x86.cpp
@@ -189,17 +189,17 @@ MacroAssemblerX86::finish()
     if (!simds_.empty())
         masm.align(SimdStackAlignment);
     for (size_t i = 0; i < simds_.length(); i++) {
         CodeLabel cl(simds_[i].uses);
         SimdData &v = simds_[i];
         switch (v.type()) {
           case SimdConstant::Int32x4:   writeInt32x4Constant(v.value, cl.src());   break;
           case SimdConstant::Float32x4: writeFloat32x4Constant(v.value, cl.src()); break;
-          default: MOZ_ASSUME_UNREACHABLE("unexpected SimdConstant type");
+          default: MOZ_CRASH("unexpected SimdConstant type");
         }
         enoughMemory_ &= addCodeLabel(cl);
         if (!enoughMemory_)
             return;
     }
 }
 
 void