Bug 1287351 - OdinMonkey: MIPS: Implement many simple operations in the MacroAssembler. r=lth
authorHeiher <r@hev.cc>
Tue, 19 Jul 2016 23:43:40 +0800
changeset 389636 d19427e7135c3c5798a235d0da8f84bab3aba190
parent 389635 6ac147f1004e4a99497f6e498fd402054ebacda9
child 389637 786569c41cd1b791bfc17c39cf65357c577eebc3
push id23471
push userbmo:tchiovoloni@mozilla.com
push dateTue, 19 Jul 2016 18:52:45 +0000
reviewerslth
bugs1287351
milestone50.0a1
Bug 1287351 - OdinMonkey: MIPS: Implement many simple operations in the MacroAssembler. r=lth --- js/src/jit/MacroAssembler.h | 56 +++---- .../mips-shared/MacroAssembler-mips-shared-inl.h | 177 +++++++++++++++++++++ .../jit/mips-shared/MacroAssembler-mips-shared.cpp | 7 + 3 files changed, 212 insertions(+), 28 deletions(-)
js/src/jit/MacroAssembler.h
js/src/jit/mips-shared/MacroAssembler-mips-shared-inl.h
js/src/jit/mips-shared/MacroAssembler-mips-shared.cpp
--- a/js/src/jit/MacroAssembler.h
+++ b/js/src/jit/MacroAssembler.h
@@ -438,17 +438,17 @@ class MacroAssembler : public MacroAssem
     void Push(JSValueType type, Register reg);
     void PushValue(const Address& addr);
     void PushEmptyRooted(VMFunction::RootType rootType);
     inline CodeOffset PushWithPatch(ImmWord word);
     inline CodeOffset PushWithPatch(ImmPtr imm);
 
     void Pop(const Operand op) DEFINED_ON(x86_shared);
     void Pop(Register reg) PER_SHARED_ARCH;
-    void Pop(FloatRegister t) DEFINED_ON(x86_shared, arm, arm64);
+    void Pop(FloatRegister t) PER_SHARED_ARCH;
     void Pop(const ValueOperand& val) PER_SHARED_ARCH;
     void popRooted(VMFunction::RootType rootType, Register cellReg, const ValueOperand& valueReg);
 
     // Move the stack pointer based on the requested amount.
     void adjustStack(int amount);
     void reserveStack(uint32_t amount) PER_ARCH;
     void freeStack(uint32_t amount);
 
@@ -686,18 +686,18 @@ class MacroAssembler : public MacroAssem
 
   public:
     // ===============================================================
     // Move instructions
 
     inline void move64(Imm64 imm, Register64 dest) PER_ARCH;
     inline void move64(Register64 src, Register64 dest) PER_ARCH;
 
-    inline void moveFloat32ToGPR(FloatRegister src, Register dest) DEFINED_ON(arm, arm64, x86_shared);
-    inline void moveGPRToFloat32(Register src, FloatRegister dest) DEFINED_ON(arm, arm64, x86_shared);
+    inline void moveFloat32ToGPR(FloatRegister src, Register dest) PER_SHARED_ARCH;
+    inline void moveGPRToFloat32(Register src, FloatRegister dest) PER_SHARED_ARCH;
 
     // ===============================================================
     // Logical instructions
 
     inline void not32(Register reg) PER_SHARED_ARCH;
 
     inline void and32(Register src, Register dest) PER_SHARED_ARCH;
     inline void and32(Imm32 imm, Register dest) PER_SHARED_ARCH;
@@ -717,17 +717,17 @@ class MacroAssembler : public MacroAssem
     inline void or32(Imm32 imm, const Address& dest) PER_SHARED_ARCH;
 
     inline void orPtr(Register src, Register dest) PER_ARCH;
     inline void orPtr(Imm32 imm, Register dest) PER_ARCH;
 
     inline void or64(Register64 src, Register64 dest) PER_ARCH;
     inline void xor64(Register64 src, Register64 dest) PER_ARCH;
 
-    inline void xor32(Register src, Register dest) DEFINED_ON(x86_shared, arm, arm64);
+    inline void xor32(Register src, Register dest) PER_SHARED_ARCH;
     inline void xor32(Imm32 imm, Register dest) PER_SHARED_ARCH;
 
     inline void xorPtr(Register src, Register dest) PER_ARCH;
     inline void xorPtr(Imm32 imm, Register dest) PER_ARCH;
 
     // ===============================================================
     // Arithmetic functions
 
@@ -744,91 +744,91 @@ class MacroAssembler : public MacroAssem
     inline void addPtr(ImmPtr imm, Register dest);
     inline void addPtr(Imm32 imm, const Address& dest) DEFINED_ON(mips_shared, arm, arm64, x86, x64);
     inline void addPtr(Imm32 imm, const AbsoluteAddress& dest) DEFINED_ON(x86, x64);
     inline void addPtr(const Address& src, Register dest) DEFINED_ON(mips_shared, arm, arm64, x86, x64);
 
     inline void add64(Register64 src, Register64 dest) PER_ARCH;
     inline void add64(Imm32 imm, Register64 dest) PER_ARCH;
 
-    inline void addFloat32(FloatRegister src, FloatRegister dest) DEFINED_ON(x86_shared, arm, arm64);
+    inline void addFloat32(FloatRegister src, FloatRegister dest) PER_SHARED_ARCH;
 
     inline void addDouble(FloatRegister src, FloatRegister dest) PER_SHARED_ARCH;
     inline void addConstantDouble(double d, FloatRegister dest) DEFINED_ON(x86);
 
     inline void sub32(const Address& src, Register dest) PER_SHARED_ARCH;
     inline void sub32(Register src, Register dest) PER_SHARED_ARCH;
     inline void sub32(Imm32 imm, Register dest) PER_SHARED_ARCH;
 
     inline void subPtr(Register src, Register dest) PER_ARCH;
     inline void subPtr(Register src, const Address& dest) DEFINED_ON(mips_shared, arm, arm64, x86, x64);
     inline void subPtr(Imm32 imm, Register dest) PER_ARCH;
     inline void subPtr(ImmWord imm, Register dest) DEFINED_ON(x64);
     inline void subPtr(const Address& addr, Register dest) DEFINED_ON(mips_shared, arm, arm64, x86, x64);
 
-    inline void subFloat32(FloatRegister src, FloatRegister dest) DEFINED_ON(x86_shared, arm, arm64);
+    inline void subFloat32(FloatRegister src, FloatRegister dest) PER_SHARED_ARCH;
 
     inline void subDouble(FloatRegister src, FloatRegister dest) PER_SHARED_ARCH;
 
     // On x86-shared, srcDest must be eax and edx will be clobbered.
-    inline void mul32(Register rhs, Register srcDest) DEFINED_ON(arm, arm64, x86_shared);
+    inline void mul32(Register rhs, Register srcDest) PER_SHARED_ARCH;
 
     inline void mul32(Register src1, Register src2, Register dest, Label* onOver, Label* onZero) DEFINED_ON(arm64);
 
     inline void mul64(Imm64 imm, const Register64& dest) PER_ARCH;
 
     inline void mulBy3(Register src, Register dest) PER_ARCH;
 
-    inline void mulFloat32(FloatRegister src, FloatRegister dest) DEFINED_ON(x86_shared, arm, arm64);
+    inline void mulFloat32(FloatRegister src, FloatRegister dest) PER_SHARED_ARCH;
     inline void mulDouble(FloatRegister src, FloatRegister dest) PER_SHARED_ARCH;
 
     inline void mulDoublePtr(ImmPtr imm, Register temp, FloatRegister dest) DEFINED_ON(mips_shared, arm, arm64, x86, x64);
 
     // Perform an integer division, returning the integer part rounded toward zero.
     // rhs must not be zero, and the division must not overflow.
     //
     // On x86_shared, srcDest must be eax and edx will be clobbered.
     // On ARM, the chip must have hardware division instructions.
-    inline void quotient32(Register rhs, Register srcDest, bool isUnsigned) DEFINED_ON(x86_shared, arm, arm64);
+    inline void quotient32(Register rhs, Register srcDest, bool isUnsigned) PER_SHARED_ARCH;
 
     // Perform an integer division, returning the remainder part.
     // rhs must not be zero, and the division must not overflow.
     //
     // On x86_shared, srcDest must be eax and edx will be clobbered.
     // On ARM, the chip must have hardware division instructions.
-    inline void remainder32(Register rhs, Register srcDest, bool isUnsigned) DEFINED_ON(x86_shared, arm, arm64);
+    inline void remainder32(Register rhs, Register srcDest, bool isUnsigned) PER_SHARED_ARCH;
 
-    inline void divFloat32(FloatRegister src, FloatRegister dest) DEFINED_ON(x86_shared, arm, arm64);
+    inline void divFloat32(FloatRegister src, FloatRegister dest) PER_SHARED_ARCH;
     inline void divDouble(FloatRegister src, FloatRegister dest) PER_SHARED_ARCH;
 
     inline void inc32(RegisterOrInt32Constant* key);
     inline void inc64(AbsoluteAddress dest) PER_ARCH;
 
     inline void dec32(RegisterOrInt32Constant* key);
 
     inline void neg32(Register reg) PER_SHARED_ARCH;
 
-    inline void negateFloat(FloatRegister reg) DEFINED_ON(arm, arm64, x86_shared);
+    inline void negateFloat(FloatRegister reg) PER_SHARED_ARCH;
 
     inline void negateDouble(FloatRegister reg) PER_SHARED_ARCH;
 
-    inline void absFloat32(FloatRegister src, FloatRegister dest) DEFINED_ON(arm, arm64, x86_shared);
-    inline void absDouble(FloatRegister src, FloatRegister dest) DEFINED_ON(arm, arm64, x86_shared);
+    inline void absFloat32(FloatRegister src, FloatRegister dest) PER_SHARED_ARCH;
+    inline void absDouble(FloatRegister src, FloatRegister dest) PER_SHARED_ARCH;
 
-    inline void sqrtFloat32(FloatRegister src, FloatRegister dest) DEFINED_ON(arm, arm64, x86_shared);
-    inline void sqrtDouble(FloatRegister src, FloatRegister dest) DEFINED_ON(arm, arm64, x86_shared);
+    inline void sqrtFloat32(FloatRegister src, FloatRegister dest) PER_SHARED_ARCH;
+    inline void sqrtDouble(FloatRegister src, FloatRegister dest) PER_SHARED_ARCH;
 
     // srcDest = {min,max}{Float32,Double}(srcDest, other)
     // For min and max, handle NaN specially if handleNaN is true.
 
-    inline void minFloat32(FloatRegister other, FloatRegister srcDest, bool handleNaN) DEFINED_ON(arm, arm64, x86_shared);
-    inline void minDouble(FloatRegister other, FloatRegister srcDest, bool handleNaN) DEFINED_ON(arm, arm64, x86_shared);
+    inline void minFloat32(FloatRegister other, FloatRegister srcDest, bool handleNaN) PER_SHARED_ARCH;
+    inline void minDouble(FloatRegister other, FloatRegister srcDest, bool handleNaN) PER_SHARED_ARCH;
 
-    inline void maxFloat32(FloatRegister other, FloatRegister srcDest, bool handleNaN) DEFINED_ON(arm, arm64, x86_shared);
-    inline void maxDouble(FloatRegister other, FloatRegister srcDest, bool handleNaN) DEFINED_ON(arm, arm64, x86_shared);
+    inline void maxFloat32(FloatRegister other, FloatRegister srcDest, bool handleNaN) PER_SHARED_ARCH;
+    inline void maxDouble(FloatRegister other, FloatRegister srcDest, bool handleNaN) PER_SHARED_ARCH;
 
     // ===============================================================
     // Shift functions
 
     // For shift-by-register there may be platform-specific
     // variations, for example, x86 will perform the shift mod 32 but
     // ARM will perform the shift mod 256.
     //
@@ -843,37 +843,37 @@ class MacroAssembler : public MacroAssem
     inline void rshiftPtr(Imm32 imm, Register dest) PER_ARCH;
     inline void rshiftPtr(Imm32 imm, Register src, Register dest) DEFINED_ON(arm64);
 
     inline void rshiftPtrArithmetic(Imm32 imm, Register dest) PER_ARCH;
 
     inline void rshift64(Imm32 imm, Register64 dest) PER_ARCH;
 
     // On x86_shared these have the constraint that shift must be in CL.
-    inline void lshift32(Register shift, Register srcDest) DEFINED_ON(x86_shared, arm, arm64);
-    inline void rshift32(Register shift, Register srcDest) DEFINED_ON(x86_shared, arm, arm64);
-    inline void rshift32Arithmetic(Register shift, Register srcDest) DEFINED_ON(x86_shared, arm, arm64);
+    inline void lshift32(Register shift, Register srcDest) PER_SHARED_ARCH;
+    inline void rshift32(Register shift, Register srcDest) PER_SHARED_ARCH;
+    inline void rshift32Arithmetic(Register shift, Register srcDest) PER_SHARED_ARCH;
 
-    inline void lshift32(Imm32 shift, Register srcDest) DEFINED_ON(x86_shared, arm, arm64);
-    inline void rshift32(Imm32 shift, Register srcDest) DEFINED_ON(x86_shared, arm, arm64);
-    inline void rshift32Arithmetic(Imm32 shift, Register srcDest) DEFINED_ON(x86_shared, arm, arm64);
+    inline void lshift32(Imm32 shift, Register srcDest) PER_SHARED_ARCH;
+    inline void rshift32(Imm32 shift, Register srcDest) PER_SHARED_ARCH;
+    inline void rshift32Arithmetic(Imm32 shift, Register srcDest) PER_SHARED_ARCH;
 
     // ===============================================================
     // Rotation functions
     inline void rotateLeft(Imm32 count, Register input, Register dest) PER_SHARED_ARCH;
     inline void rotateLeft(Register count, Register input, Register dest) PER_SHARED_ARCH;
     inline void rotateRight(Imm32 count, Register input, Register dest) PER_SHARED_ARCH;
     inline void rotateRight(Register count, Register input, Register dest) PER_SHARED_ARCH;
 
     // ===============================================================
     // Bit counting functions
 
     // knownNotZero may be true only if the src is known not to be zero.
-    inline void clz32(Register src, Register dest, bool knownNotZero) DEFINED_ON(x86_shared, arm, arm64);
-    inline void ctz32(Register src, Register dest, bool knownNotZero) DEFINED_ON(x86_shared, arm, arm64);
+    inline void clz32(Register src, Register dest, bool knownNotZero) PER_SHARED_ARCH;
+    inline void ctz32(Register src, Register dest, bool knownNotZero) PER_SHARED_ARCH;
 
     inline void clz64(Register64 src, Register64 dest) DEFINED_ON(x64);
     inline void ctz64(Register64 src, Register64 dest) DEFINED_ON(x64);
 
     // On x86_shared, temp may be Invalid only if the chip has the POPCNT instruction.
     // On ARM, temp may never be Invalid.
     inline void popcnt32(Register src, Register dest, Register temp) DEFINED_ON(arm, x86_shared);
 
--- a/js/src/jit/mips-shared/MacroAssembler-mips-shared-inl.h
+++ b/js/src/jit/mips-shared/MacroAssembler-mips-shared-inl.h
@@ -8,16 +8,29 @@
 #define jit_mips_shared_MacroAssembler_mips_shared_inl_h
 
 #include "jit/mips-shared/MacroAssembler-mips-shared.h"
 
 namespace js {
 namespace jit {
 
 //{{{ check_macroassembler_style
+
+void
+MacroAssembler::moveFloat32ToGPR(FloatRegister src, Register dest)
+{
+    moveFromFloat32(src, dest);
+}
+
+void
+MacroAssembler::moveGPRToFloat32(Register src, FloatRegister dest)
+{
+    moveToFloat32(src, dest);
+}
+
 // ===============================================================
 // Logical instructions
 
 void
 MacroAssembler::not32(Register reg)
 {
     ma_not(reg, reg);
 }
@@ -65,16 +78,22 @@ void
 MacroAssembler::or32(Imm32 imm, const Address& dest)
 {
     load32(dest, SecondScratchReg);
     ma_or(SecondScratchReg, imm);
     store32(SecondScratchReg, dest);
 }
 
 void
+MacroAssembler::xor32(Register src, Register dest)
+{
+    ma_xor(dest, src);
+}
+
+void
 MacroAssembler::xor32(Imm32 imm, Register dest)
 {
     ma_xor(dest, imm);
 }
 
 // ===============================================================
 // Arithmetic instructions
 
@@ -115,16 +134,22 @@ MacroAssembler::addPtr(const Address& sr
 
 void
 MacroAssembler::addDouble(FloatRegister src, FloatRegister dest)
 {
     as_addd(dest, dest, src);
 }
 
 void
+MacroAssembler::addFloat32(FloatRegister src, FloatRegister dest)
+{
+    as_adds(dest, dest, src);
+}
+
+void
 MacroAssembler::sub32(Register src, Register dest)
 {
     as_subu(dest, dest, src);
 }
 
 void
 MacroAssembler::sub32(Imm32 imm, Register dest)
 {
@@ -155,30 +180,74 @@ MacroAssembler::subPtr(const Address& ad
 
 void
 MacroAssembler::subDouble(FloatRegister src, FloatRegister dest)
 {
     as_subd(dest, dest, src);
 }
 
 void
+MacroAssembler::subFloat32(FloatRegister src, FloatRegister dest)
+{
+    as_subs(dest, dest, src);
+}
+
+void
+MacroAssembler::mul32(Register rhs, Register srcDest)
+{
+    as_mul(srcDest, srcDest, rhs);
+}
+
+void
+MacroAssembler::mulFloat32(FloatRegister src, FloatRegister dest)
+{
+    as_muls(dest, dest, src);
+}
+
+void
 MacroAssembler::mulDouble(FloatRegister src, FloatRegister dest)
 {
     as_muld(dest, dest, src);
 }
 
 void
 MacroAssembler::mulDoublePtr(ImmPtr imm, Register temp, FloatRegister dest)
 {
     movePtr(imm, ScratchRegister);
     loadDouble(Address(ScratchRegister, 0), ScratchDoubleReg);
     mulDouble(ScratchDoubleReg, dest);
 }
 
 void
+MacroAssembler::quotient32(Register rhs, Register srcDest, bool isUnsigned)
+{
+    if (isUnsigned)
+        as_divu(srcDest, rhs);
+    else
+        as_div(srcDest, rhs);
+    as_mflo(srcDest);
+}
+
+void
+MacroAssembler::remainder32(Register rhs, Register srcDest, bool isUnsigned)
+{
+    if (isUnsigned)
+        as_divu(srcDest, rhs);
+    else
+        as_div(srcDest, rhs);
+    as_mfhi(srcDest);
+}
+
+void
+MacroAssembler::divFloat32(FloatRegister src, FloatRegister dest)
+{
+    as_divs(dest, dest, src);
+}
+
+void
 MacroAssembler::divDouble(FloatRegister src, FloatRegister dest)
 {
     as_divd(dest, dest, src);
 }
 
 void
 MacroAssembler::neg32(Register reg)
 {
@@ -186,16 +255,109 @@ MacroAssembler::neg32(Register reg)
 }
 
 void
 MacroAssembler::negateDouble(FloatRegister reg)
 {
     as_negd(reg, reg);
 }
 
+void
+MacroAssembler::negateFloat(FloatRegister reg)
+{
+    as_negs(reg, reg);
+}
+
+void
+MacroAssembler::absFloat32(FloatRegister src, FloatRegister dest)
+{
+    as_abss(dest, src);
+}
+
+void
+MacroAssembler::absDouble(FloatRegister src, FloatRegister dest)
+{
+    as_absd(dest, src);
+}
+
+void
+MacroAssembler::sqrtFloat32(FloatRegister src, FloatRegister dest)
+{
+    as_sqrts(dest, src);
+}
+
+void
+MacroAssembler::sqrtDouble(FloatRegister src, FloatRegister dest)
+{
+    as_sqrtd(dest, src);
+}
+
+void
+MacroAssembler::minFloat32(FloatRegister other, FloatRegister srcDest, bool handleNaN)
+{
+    minMaxFloat32(srcDest, other, handleNaN, false);
+}
+
+void
+MacroAssembler::minDouble(FloatRegister other, FloatRegister srcDest, bool handleNaN)
+{
+    minMaxDouble(srcDest, other, handleNaN, false);
+}
+
+void
+MacroAssembler::maxFloat32(FloatRegister other, FloatRegister srcDest, bool handleNaN)
+{
+    minMaxFloat32(srcDest, other, handleNaN, true);
+}
+
+void
+MacroAssembler::maxDouble(FloatRegister other, FloatRegister srcDest, bool handleNaN)
+{
+    minMaxDouble(srcDest, other, handleNaN, true);
+}
+
+// ===============================================================
+// Shift functions
+
+void
+MacroAssembler::lshift32(Register src, Register dest)
+{
+    ma_sll(dest, dest, src);
+}
+
+void
+MacroAssembler::lshift32(Imm32 imm, Register dest)
+{
+    ma_sll(dest, dest, imm);
+}
+
+void
+MacroAssembler::rshift32(Register src, Register dest)
+{
+    ma_srl(dest, dest, src);
+}
+
+void
+MacroAssembler::rshift32(Imm32 imm, Register dest)
+{
+    ma_srl(dest, dest, imm);
+}
+
+void
+MacroAssembler::rshift32Arithmetic(Register src, Register dest)
+{
+    ma_sra(dest, dest, src);
+}
+
+void
+MacroAssembler::rshift32Arithmetic(Imm32 imm, Register dest)
+{
+    ma_sra(dest, dest, imm);
+}
+
 // ===============================================================
 // Rotation functions
 void
 MacroAssembler::rotateLeft(Imm32 count, Register input, Register dest)
 {
     if (count.value)
         ma_rol(dest, input, count);
     else
@@ -216,16 +378,31 @@ MacroAssembler::rotateRight(Imm32 count,
 }
 void
 MacroAssembler::rotateRight(Register count, Register input, Register dest)
 {
     ma_ror(dest, input, count);
 }
 
 // ===============================================================
+// Bit counting functions
+
+void
+MacroAssembler::clz32(Register src, Register dest, bool knownNotZero)
+{
+    as_clz(dest, src);
+}
+
+void
+MacroAssembler::ctz32(Register src, Register dest, bool knownNotZero)
+{
+    ma_ctz(dest, src);
+}
+
+// ===============================================================
 // Branch functions
 
 void
 MacroAssembler::branch32(Condition cond, Register lhs, Register rhs, Label* label)
 {
     ma_b(lhs, rhs, label, cond);
 }
 
--- a/js/src/jit/mips-shared/MacroAssembler-mips-shared.cpp
+++ b/js/src/jit/mips-shared/MacroAssembler-mips-shared.cpp
@@ -1256,16 +1256,23 @@ MacroAssembler::Push(FloatRegister f)
 void
 MacroAssembler::Pop(Register reg)
 {
     ma_pop(reg);
     adjustFrame(-sizeof(intptr_t));
 }
 
 void
+MacroAssembler::Pop(FloatRegister f)
+{
+    ma_pop(f);
+    adjustFrame(-sizeof(double));
+}
+
+void
 MacroAssembler::Pop(const ValueOperand& val)
 {
     popValue(val);
     framePushed_ -= sizeof(Value);
 }
 
 
 // ===============================================================