Bug 1421244: Remove more ARMv6 dead code; r=lth
authorBenjamin Bouvier <benj@benj.me>
Thu, 30 Nov 2017 12:55:06 +0100
changeset 706645 48d573a890201a591bda202ba5db37eb8559e26f
parent 706644 0c2a8520c1d265889f9955b32d00fd2875a4c6b7
child 706646 ab3f9d3f775a6298b4a99b36cd53f67e69f8049e
push id91866
push userbmo:jbeich@FreeBSD.org
push dateSun, 03 Dec 2017 00:05:43 +0000
reviewerslth
bugs1421244
milestone59.0a1
Bug 1421244: Remove more ARMv6 dead code; r=lth MozReview-Commit-ID: FkeXdjIcffl
js/src/jit/arm/MacroAssembler-arm.cpp
js/src/jit/arm/MacroAssembler-arm.h
--- a/js/src/jit/arm/MacroAssembler-arm.cpp
+++ b/js/src/jit/arm/MacroAssembler-arm.cpp
@@ -4188,32 +4188,16 @@ MacroAssemblerARMCompat::computePointer<
         return src.base;
     ma_add(src.base, Imm32(src.offset), r, scratch);
     return r;
 }
 
 } // namespace jit
 } // namespace js
 
-template<typename T>
-void
-MacroAssemblerARMCompat::compareExchange(int nbytes, bool signExtend, const T& mem,
-                                         Register oldval, Register newval, Register output)
-{
-    // If LDREXB/H and STREXB/H are not available we use the
-    // word-width operations with read-modify-add.  That does not
-    // abstract well, so fork.
-    //
-    // Bug 1077321: We may further optimize for ARMv8 (AArch32) here.
-    if (nbytes < 4 && !HasLDSTREXBHD())
-        compareExchangeARMv6(nbytes, signExtend, mem, oldval, newval, output);
-    else
-        compareExchangeARMv7(nbytes, signExtend, mem, oldval, newval, output);
-}
-
 // General algorithm:
 //
 //     ...    ptr, <addr>         ; compute address of item
 //     dmb
 // L0  ldrex* output, [ptr]
 //     sxt*   output, output, 0   ; sign-extend if applicable
 //     *xt*   tmp, oldval, 0      ; sign-extend or zero-extend if applicable
 //     cmp    output, tmp
@@ -4227,18 +4211,18 @@ MacroAssemblerARMCompat::compareExchange
 // However note that that discussion uses 'isb' as the trailing fence.
 // I've not quite figured out why, and I've gone with dmb here which
 // is safe.  Also see the LLVM source, which uses 'dmb ish' generally.
 // (Apple's Swift CPU apparently handles ish in a non-default, faster
 // way.)
 
 template<typename T>
 void
-MacroAssemblerARMCompat::compareExchangeARMv7(int nbytes, bool signExtend, const T& mem,
-                                              Register oldval, Register newval, Register output)
+MacroAssemblerARMCompat::compareExchange(int nbytes, bool signExtend, const T& mem,
+                                         Register oldval, Register newval, Register output)
 {
     Label again;
     Label done;
 
     asMasm().memoryBarrier(MembarFull);
 
     SecondScratchRegisterScope scratch2(asMasm());
     Register ptr = computePointer(mem, scratch2);
@@ -4288,56 +4272,31 @@ MacroAssemblerARMCompat::compareExchange
     }
     as_cmp(scratch, Imm8(1));
     as_b(&again, Equal);
     bind(&done);
 
     asMasm().memoryBarrier(MembarFull);
 }
 
-template<typename T>
-void
-MacroAssemblerARMCompat::compareExchangeARMv6(int nbytes, bool signExtend, const T& mem,
-                                              Register oldval, Register newval, Register output)
-{
-    // Bug 1077318: Must use read-modify-write with LDREX / STREX.
-    MOZ_ASSERT(nbytes == 1 || nbytes == 2);
-    MOZ_CRASH("NYI");
-}
-
 template void
 js::jit::MacroAssemblerARMCompat::compareExchange(int nbytes, bool signExtend,
                                                   const Address& address, Register oldval,
                                                   Register newval, Register output);
 template void
 js::jit::MacroAssemblerARMCompat::compareExchange(int nbytes, bool signExtend,
                                                   const BaseIndex& address, Register oldval,
                                                   Register newval, Register output);
 
 template<typename T>
 void
 MacroAssemblerARMCompat::atomicExchange(int nbytes, bool signExtend, const T& mem,
                                         Register value, Register output)
 {
-    // If LDREXB/H and STREXB/H are not available we use the
-    // word-width operations with read-modify-add.  That does not
-    // abstract well, so fork.
-    //
     // Bug 1077321: We may further optimize for ARMv8 (AArch32) here.
-    if (nbytes < 4 && !HasLDSTREXBHD())
-        atomicExchangeARMv6(nbytes, signExtend, mem, value, output);
-    else
-        atomicExchangeARMv7(nbytes, signExtend, mem, value, output);
-}
-
-template<typename T>
-void
-MacroAssemblerARMCompat::atomicExchangeARMv7(int nbytes, bool signExtend, const T& mem,
-                                             Register value, Register output)
-{
     Label again;
     Label done;
 
     asMasm().memoryBarrier(MembarFull);
 
     SecondScratchRegisterScope scratch2(asMasm());
     Register ptr = computePointer(mem, scratch2);
 
@@ -4367,26 +4326,16 @@ MacroAssemblerARMCompat::atomicExchangeA
     }
     as_cmp(scratch, Imm8(1));
     as_b(&again, Equal);
     bind(&done);
 
     asMasm().memoryBarrier(MembarFull);
 }
 
-template<typename T>
-void
-MacroAssemblerARMCompat::atomicExchangeARMv6(int nbytes, bool signExtend, const T& mem,
-                                             Register value, Register output)
-{
-    // Bug 1077318: Must use read-modify-write with LDREX / STREX.
-    MOZ_ASSERT(nbytes == 1 || nbytes == 2);
-    MOZ_CRASH("NYI");
-}
-
 template void
 js::jit::MacroAssemblerARMCompat::atomicExchange(int nbytes, bool signExtend,
                                                  const Address& address, Register value,
                                                  Register output);
 template void
 js::jit::MacroAssemblerARMCompat::atomicExchange(int nbytes, bool signExtend,
                                                  const BaseIndex& address, Register value,
                                                  Register output);
@@ -4424,31 +4373,16 @@ MacroAssemblerARMCompat::atomicFetchOp(i
 // output nor the bits stored are affected by OP.
 
 template<typename T>
 void
 MacroAssemblerARMCompat::atomicFetchOp(int nbytes, bool signExtend, AtomicOp op,
                                        const Register& value, const T& mem, Register flagTemp,
                                        Register output)
 {
-    // Fork for non-word operations on ARMv6.
-    //
-    // Bug 1077321: We may further optimize for ARMv8 (AArch32) here.
-    if (nbytes < 4 && !HasLDSTREXBHD())
-        atomicFetchOpARMv6(nbytes, signExtend, op, value, mem, flagTemp, output);
-    else
-        atomicFetchOpARMv7(nbytes, signExtend, op, value, mem, flagTemp, output);
-}
-
-template<typename T>
-void
-MacroAssemblerARMCompat::atomicFetchOpARMv7(int nbytes, bool signExtend, AtomicOp op,
-                                            const Register& value, const T& mem, Register flagTemp,
-                                            Register output)
-{
     MOZ_ASSERT(flagTemp != InvalidReg);
     MOZ_ASSERT(output != value);
 
     Label again;
 
     SecondScratchRegisterScope scratch2(asMasm());
     Register ptr = computePointer(mem, scratch2);
 
@@ -4503,69 +4437,32 @@ MacroAssemblerARMCompat::atomicFetchOpAR
         break;
     }
     as_cmp(flagTemp, Imm8(1));
     as_b(&again, Equal);
 
     asMasm().memoryBarrier(MembarFull);
 }
 
-template<typename T>
-void
-MacroAssemblerARMCompat::atomicFetchOpARMv6(int nbytes, bool signExtend, AtomicOp op,
-                                            const Register& value, const T& mem, Register flagTemp,
-                                            Register output)
-{
-    // Bug 1077318: Must use read-modify-write with LDREX / STREX.
-    MOZ_ASSERT(nbytes == 1 || nbytes == 2);
-    MOZ_CRASH("NYI");
-}
-template<typename T>
-void
-MacroAssemblerARMCompat::atomicEffectOp(int nbytes, AtomicOp op, const Register& value,
-                                        const T& mem, Register flagTemp)
-{
-    // Fork for non-word operations on ARMv6.
-    //
-    // Bug 1077321: We may further optimize for ARMv8 (AArch32) here.
-    if (nbytes < 4 && !HasLDSTREXBHD())
-        atomicEffectOpARMv6(nbytes, op, value, mem, flagTemp);
-    else
-        atomicEffectOpARMv7(nbytes, op, value, mem, flagTemp);
-}
-
-template<typename T>
-void
-MacroAssemblerARMCompat::atomicEffectOp(int nbytes, AtomicOp op, const Imm32& value,
-                                        const T& mem, Register flagTemp)
-{
-    // The Imm32 case is not needed yet because lowering always forces
-    // the value into a register at present (bug 1077317).
-    //
-    // This would be useful for immediates small enough to fit into
-    // add/sub/and/or/xor.
-    MOZ_CRASH("NYI");
-}
-
 // Uses both scratch registers, one for the address and one for a temp,
 // but needs two temps for strex:
 //
 //     ...    ptr, <addr>         ; compute address of item
 //     dmb
 // L0  ldrex* temp, [ptr]
 //     OP     temp, temp, value   ; compute value to store
 //     strex* temp2, temp, [ptr]
 //     cmp    temp2, 1
 //     beq    L0                  ; failed - location is dirty, retry
 //     dmb                        ; ordering barrier required
 
 template<typename T>
 void
-MacroAssemblerARMCompat::atomicEffectOpARMv7(int nbytes, AtomicOp op, const Register& value,
-                                             const T& mem, Register flagTemp)
+MacroAssemblerARMCompat::atomicEffectOp(int nbytes, AtomicOp op, const Register& value,
+                                        const T& mem, Register flagTemp)
 {
     MOZ_ASSERT(flagTemp != InvalidReg);
 
     Label again;
 
     SecondScratchRegisterScope scratch2(asMasm());
     Register ptr = computePointer(mem, scratch2);
 
@@ -4617,21 +4514,24 @@ MacroAssemblerARMCompat::atomicEffectOpA
     as_cmp(flagTemp, Imm8(1));
     as_b(&again, Equal);
 
     asMasm().memoryBarrier(MembarFull);
 }
 
 template<typename T>
 void
-MacroAssemblerARMCompat::atomicEffectOpARMv6(int nbytes, AtomicOp op, const Register& value,
-                                             const T& mem, Register flagTemp)
-{
-    // Bug 1077318: Must use read-modify-write with LDREX / STREX.
-    MOZ_ASSERT(nbytes == 1 || nbytes == 2);
+MacroAssemblerARMCompat::atomicEffectOp(int nbytes, AtomicOp op, const Imm32& value,
+                                        const T& mem, Register flagTemp)
+{
+    // The Imm32 case is not needed yet because lowering always forces
+    // the value into a register at present (bug 1077317).
+    //
+    // This would be useful for immediates small enough to fit into
+    // add/sub/and/or/xor.
     MOZ_CRASH("NYI");
 }
 
 template void
 js::jit::MacroAssemblerARMCompat::atomicFetchOp(int nbytes, bool signExtend, AtomicOp op,
                                                 const Imm32& value, const Address& mem,
                                                 Register flagTemp, Register output);
 template void
--- a/js/src/jit/arm/MacroAssembler-arm.h
+++ b/js/src/jit/arm/MacroAssembler-arm.h
@@ -1107,64 +1107,32 @@ class MacroAssemblerARMCompat : public M
         ma_vmov(src, dest, cc);
     }
 
   private:
     template<typename T>
     Register computePointer(const T& src, Register r);
 
     template<typename T>
-    void compareExchangeARMv6(int nbytes, bool signExtend, const T& mem, Register oldval,
-                              Register newval, Register output);
-
-    template<typename T>
-    void compareExchangeARMv7(int nbytes, bool signExtend, const T& mem, Register oldval,
-                              Register newval, Register output);
-
-    template<typename T>
     void compareExchange(int nbytes, bool signExtend, const T& address, Register oldval,
                          Register newval, Register output);
 
     template<typename T>
-    void atomicExchangeARMv6(int nbytes, bool signExtend, const T& mem, Register value,
-                             Register output);
-
-    template<typename T>
-    void atomicExchangeARMv7(int nbytes, bool signExtend, const T& mem, Register value,
-                             Register output);
-
-    template<typename T>
     void atomicExchange(int nbytes, bool signExtend, const T& address, Register value,
                         Register output);
 
     template<typename T>
-    void atomicFetchOpARMv6(int nbytes, bool signExtend, AtomicOp op, const Register& value,
-                            const T& mem, Register flagTemp, Register output);
-
-    template<typename T>
-    void atomicFetchOpARMv7(int nbytes, bool signExtend, AtomicOp op, const Register& value,
-                            const T& mem, Register flagTemp, Register output);
-
-    template<typename T>
     void atomicFetchOp(int nbytes, bool signExtend, AtomicOp op, const Imm32& value,
                        const T& address, Register flagTemp, Register output);
 
     template<typename T>
     void atomicFetchOp(int nbytes, bool signExtend, AtomicOp op, const Register& value,
                        const T& address, Register flagTemp, Register output);
 
     template<typename T>
-    void atomicEffectOpARMv6(int nbytes, AtomicOp op, const Register& value, const T& address,
-                             Register flagTemp);
-
-    template<typename T>
-    void atomicEffectOpARMv7(int nbytes, AtomicOp op, const Register& value, const T& address,
-                             Register flagTemp);
-
-    template<typename T>
     void atomicEffectOp(int nbytes, AtomicOp op, const Imm32& value, const T& address,
                              Register flagTemp);
 
     template<typename T>
     void atomicEffectOp(int nbytes, AtomicOp op, const Register& value, const T& address,
                              Register flagTemp);
 
     template<typename T>