--- a/js/src/nanojit/NativeSparc.cpp
+++ b/js/src/nanojit/NativeSparc.cpp
@@ -267,25 +267,25 @@ namespace nanojit
Reservation *resv = getresv(ins);
Register rr = resv->reg;
if (rr != UnknownReg && (rmask(rr) & FpRegs))
evict(rr);
if (hi->isconst()) {
STW32(L0, d+4, FP);
- SET32(hi->constval(), L0);
+ SET32(hi->imm32(), L0);
} else {
Register rh = findRegFor(hi, GpRegs);
STW32(rh, d+4, FP);
}
if (lo->isconst()) {
STW32(L0, d, FP);
- SET32(lo->constval(), L0);
+ SET32(lo->imm32(), L0);
} else {
// okay if r gets recycled.
Register rl = findRegFor(lo, GpRegs);
STW32(rl, d, FP);
}
freeRsrcOf(ins, false); // if we had a reg in use, emit a ST to flush it to mem
}
@@ -300,17 +300,17 @@ namespace nanojit
verbose_only(if (_verbose) {
outputf(" remat %s size %d", _thisfrag->lirbuf->names->formatRef(i), i->size());
})
}
else if (i->isconst()) {
if (!resv->arIndex) {
reserveFree(i);
}
- int v = i->constval();
+ int v = i->imm32();
SET32(v, r);
} else {
int d = findMemFor(i);
if (rmask(r) & FpRegs) {
LDDF32(FP, d, r);
} else {
LDSW32(FP, d, r);
}
@@ -321,32 +321,32 @@ namespace nanojit
}
void Assembler::asm_store32(LIns *value, int dr, LIns *base)
{
underrunProtect(20);
if (value->isconst())
{
Register rb = getBaseReg(base, dr, GpRegs);
- int c = value->constval();
+ int c = value->imm32();
STW32(L0, dr, rb);
SET32(c, L0);
}
else
{
// make sure what is in a register
Reservation *rA, *rB;
Register ra, rb;
if (base->isop(LIR_alloc)) {
rb = FP;
dr += findMemFor(base);
ra = findRegFor(value, GpRegs);
} else if (base->isconst()) {
// absolute address
- dr += base->constval();
+ dr += base->imm32();
ra = findRegFor(value, GpRegs);
rb = G0;
} else {
findRegFor2(GpRegs, value, rA, base, rB);
ra = rA->reg;
rb = rB->reg;
}
STW32(ra, dr, rb);
@@ -365,17 +365,17 @@ namespace nanojit
}
}
}
void Assembler::asm_load64(LInsp ins)
{
underrunProtect(72);
LIns* base = ins->oprnd1();
- int db = ins->oprnd2()->constval();
+ int db = ins->oprnd2()->imm32();
Reservation *resv = getresv(ins);
Register rr = resv->reg;
int dr = disp(resv);
Register rb;
if (base->isop(LIR_alloc)) {
rb = FP;
db += findMemFor(base);
@@ -403,19 +403,19 @@ namespace nanojit
underrunProtect(48);
if (value->isconstq())
{
// if a constant 64-bit value just store it now rather than
// generating a pointless store/load/store sequence
Register rb = findRegFor(base, GpRegs);
const int32_t* p = (const int32_t*) (value-2);
STW32(L0, dr+4, rb);
- SET32(p[0], L0);
+ SET32(value->imm64_0(), L0);
STW32(L0, dr, rb);
- SET32(p[1], L0);
+ SET32(value->imm64_1(), L0);
return;
}
if (value->isop(LIR_ldq) || value->isop(LIR_ldqc) || value->isop(LIR_qjoin))
{
// value is 64bit struct or int64_t, or maybe a double.
// it may be live in an FPU reg. Either way, don't
// put it in an FPU reg just to load & store it.
@@ -569,17 +569,17 @@ namespace nanojit
NanoAssert((!lhs->isQuad() && !rhs->isQuad()) || (lhs->isQuad() && rhs->isQuad()));
NanoAssert(!lhs->isQuad() && !rhs->isQuad());
// ready to issue the compare
if (rhs->isconst())
{
- int c = rhs->constval();
+ int c = rhs->imm32();
if (c == 0 && cond->isop(LIR_eq)) {
Register r = findRegFor(lhs, GpRegs);
ANDCC(r, r, G0);
}
else if (!rhs->isQuad()) {
Register r = getBaseReg(lhs, c, GpRegs);
SUBCC(r, L0, G0);
SET32(c, L0);
@@ -665,17 +665,17 @@ namespace nanojit
if ((rb = asm_binop_rhs_reg(ins)) == UnknownReg) {
rb = findRegFor(rhs, allow);
}
allow &= ~rmask(rb);
}
else if ((op == LIR_add||op == LIR_addp) && lhs->isop(LIR_alloc) && rhs->isconst()) {
// add alloc+const, use lea
Register rr = prepResultReg(ins, allow);
- int d = findMemFor(lhs) + rhs->constval();
+ int d = findMemFor(lhs) + rhs->imm32();
ADD(FP, L0, rr);
SET32(d, L0);
}
Register rr = prepResultReg(ins, allow);
Reservation* rA = getresv(lhs);
Register ra;
// if this is last use of lhs in reg, we can re-use result reg
@@ -706,17 +706,17 @@ namespace nanojit
SRA(rr, rb, rr);
else if (op == LIR_ush)
SRL(rr, rb, rr);
else
NanoAssertMsg(0, "Unsupported");
}
else
{
- int c = rhs->constval();
+ int c = rhs->imm32();
if (op == LIR_add || op == LIR_addp) {
ADDCC(rr, L0, rr);
} else if (op == LIR_sub) {
SUBCC(rr, L0, rr);
} else if (op == LIR_and)
AND(rr, L0, rr);
else if (op == LIR_or)
OR(rr, L0, rr);
@@ -762,17 +762,17 @@ namespace nanojit
void Assembler::asm_ld(LInsp ins)
{
underrunProtect(12);
LOpcode op = ins->opcode();
LIns* base = ins->oprnd1();
LIns* disp = ins->oprnd2();
Register rr = prepResultReg(ins, GpRegs);
- int d = disp->constval();
+ int d = disp->imm32();
Register ra = getBaseReg(base, d, GpRegs);
if (op == LIR_ldcb) {
LDUB32(ra, d, rr);
} else if (op == LIR_ldcs) {
LDUH32(ra, d, rr);
} else {
LDSW32(ra, d, rr);
}
@@ -837,27 +837,16 @@ namespace nanojit
// prepResultReg(ins, rmask(argRegs[a]));
if (kind == 0) {
prepResultReg(ins, rmask(argRegs[a]));
} else {
prepResultReg(ins, rmask(savedRegs[a]));
}
}
- void Assembler::asm_short(LInsp ins)
- {
- underrunProtect(8);
- Register rr = prepResultReg(ins, GpRegs);
- int32_t val = ins->imm16();
- if (val == 0)
- XOR(rr, rr, rr);
- else
- SET32(val, rr);
- }
-
void Assembler::asm_int(LInsp ins)
{
underrunProtect(8);
Register rr = prepResultReg(ins, GpRegs);
int32_t val = ins->imm32();
if (val == 0)
XOR(rr, rr, rr);
else
@@ -884,19 +873,19 @@ namespace nanojit
int d = disp(rR);
freeRsrcOf(ins, false);
if (d)
{
Register r = registerAlloc(GpRegs);
_allocator.addFree(r);
const int32_t* p = (const int32_t*) (ins-2);
STW32(r, d+4, FP);
- SET32(p[0], r);
+ SET32(ins->imm64_0(), r);
STW32(r, d, FP);
- SET32(p[1], r);
+ SET32(ins->imm64_1(), r);
}
}
void Assembler::asm_qlo(LInsp ins)
{
}
void Assembler::asm_fneg(LInsp ins)