[arm] b=481761; fix up asm_cmov; assert on non-qcmov; r=graydon
authorVladimir Vukicevic <vladimir@pobox.com>
Fri, 20 Mar 2009 15:53:14 -0700
changeset 26539 cda79cc9399ed9a9ce2adb0b4c2915fed4ca34e9
parent 26538 77f4c1affaa22182690760f258403b5ecdceee76
child 26540 c1abb77d680baf7999ce3e524dc5566ba500ec07
push id6115
push userrsayre@mozilla.com
push dateTue, 24 Mar 2009 17:50:03 +0000
treeherdermozilla-central@4a34c6235bb7 [default view] [failures only]
perfherder[talos] [build metrics] [platform microbench] (compared to previous push)
reviewersgraydon
bugs481761
milestone1.9.2a1pre
[arm] b=481761; fix up asm_cmov; assert on non-qcmov; r=graydon
js/src/nanojit/NativeARM.cpp
--- a/js/src/nanojit/NativeARM.cpp
+++ b/js/src/nanojit/NativeARM.cpp
@@ -1473,51 +1473,47 @@ Assembler::asm_ld(LInsp ins)
     }
 
     NanoAssertMsg(0, "Unsupported instruction in asm_ld");
 }
 
 void
 Assembler::asm_cmov(LInsp ins)
 {
-    LOpcode op = ins->opcode();
+    NanoAssert(ins->opcode() == LIR_cmov);
     LIns* condval = ins->oprnd1();
     NanoAssert(condval->isCmp());
 
     LIns* values = ins->oprnd2();
 
     NanoAssert(values->opcode() == LIR_2);
     LIns* iftrue = values->oprnd1();
     LIns* iffalse = values->oprnd2();
 
-    NanoAssert(op == LIR_qcmov || (!iftrue->isQuad() && !iffalse->isQuad()));
+    NanoAssert(!iftrue->isQuad() && !iffalse->isQuad());
 
     const Register rr = prepResultReg(ins, GpRegs);
 
     // this code assumes that neither LD nor MR nor MRcc set any of the condition flags.
     // (This is true on Intel, is it true on all architectures?)
     const Register iffalsereg = findRegFor(iffalse, GpRegs & ~rmask(rr));
-    if (op == LIR_cmov) {
-        switch (condval->opcode()) {
-            // note that these are all opposites...
-            case LIR_eq:    MOVNE(rr, iffalsereg);   break;
-            case LIR_ov:    MOVNO(rr, iffalsereg);   break;
-            case LIR_cs:    MOVNC(rr, iffalsereg);   break;
-            case LIR_lt:    MOVGE(rr, iffalsereg);   break;
-            case LIR_le:    MOVG(rr, iffalsereg);    break;
-            case LIR_gt:    MOVLE(rr, iffalsereg);   break;
-            case LIR_ge:    MOVL(rr, iffalsereg);    break;
-            case LIR_ult:   MOVAE(rr, iffalsereg);   break;
-            case LIR_ule:   MOVA(rr, iffalsereg);    break;
-            case LIR_ugt:   MOVBE(rr, iffalsereg);   break;
-            case LIR_uge:   MOVB(rr, iffalsereg);    break;
-            default: debug_only( NanoAssert(0) );   break;
-        }
-    } else if (op == LIR_qcmov) {
-        NanoAssert(0);
+    switch (condval->opcode()) {
+        // note that these are all opposites...
+        case LIR_eq:    MOVNE(rr, iffalsereg);   break;
+        case LIR_ov:    MOVNO(rr, iffalsereg);   break;
+        case LIR_cs:    MOVNC(rr, iffalsereg);   break;
+        case LIR_lt:    MOVGE(rr, iffalsereg);   break;
+        case LIR_le:    MOVG(rr, iffalsereg);    break;
+        case LIR_gt:    MOVLE(rr, iffalsereg);   break;
+        case LIR_ge:    MOVL(rr, iffalsereg);    break;
+        case LIR_ult:   MOVAE(rr, iffalsereg);   break;
+        case LIR_ule:   MOVA(rr, iffalsereg);    break;
+        case LIR_ugt:   MOVBE(rr, iffalsereg);   break;
+        case LIR_uge:   MOVB(rr, iffalsereg);    break;
+        default: debug_only( NanoAssert(0) );   break;
     }
     /*const Register iftruereg =*/ findSpecificRegFor(iftrue, rr);
     asm_cmp(condval);
 }
 
 void
 Assembler::asm_qhi(LInsp ins)
 {