Bug 1077346 - implement coprocessor traps for DSB, DMB, ISB. r=dtc-moz
authorLars T Hansen <lhansen@mozilla.com>
Wed, 15 Oct 2014 09:24:49 +0200
changeset 210503 c07de0783e2791c824b026df4b5a978fb773d4cc
parent 210502 d5c1c2837d530539ee8edc2835c61f48009fca0b
child 210504 8d0aca89e1b264e607f151fd1f23f6b15ccf3e0d
push id27654
push userryanvm@gmail.com
push dateWed, 15 Oct 2014 18:31:27 +0000
treeherdermozilla-central@a280a03c9f3c [default view] [failures only]
perfherder[talos] [build metrics] [platform microbench] (compared to previous push)
reviewersdtc-moz
bugs1077346
milestone36.0a1
first release with
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nightly linux64
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nightly win32
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Bug 1077346 - implement coprocessor traps for DSB, DMB, ISB. r=dtc-moz
js/src/jit/arm/Simulator-arm.cpp
js/src/jit/arm/Simulator-arm.h
--- a/js/src/jit/arm/Simulator-arm.cpp
+++ b/js/src/jit/arm/Simulator-arm.cpp
@@ -3236,21 +3236,53 @@ Simulator::decodeType6(SimInstruction *i
     decodeType6CoprocessorIns(instr);
 }
 
 void
 Simulator::decodeType7(SimInstruction *instr)
 {
     if (instr->bit(24) == 1)
         softwareInterrupt(instr);
+    else if (instr->bit(4) == 1 && instr->bits(11,9) != 5)
+        decodeType7CoprocessorIns(instr);
     else
         decodeTypeVFP(instr);
 }
 
 void
+Simulator::decodeType7CoprocessorIns(SimInstruction *instr)
+{
+    if (instr->bit(20) == 0) {
+        // MCR, MCR2
+        if (instr->coprocessorValue() == 15) {
+            int opc1 = instr->bits(23,21);
+            int opc2 = instr->bits(7,5);
+            int CRn = instr->bits(19,16);
+            int CRm = instr->bits(3,0);
+            if (opc1 == 0 && opc2 == 4 && CRn == 7 && CRm == 10) {
+                // ARMv6 DSB instruction - do nothing now, see comments above
+            } else if (opc1 == 0 && opc2 == 5 && CRn == 7 && CRm == 10) {
+                // ARMv6 DMB instruction - do nothing now, see comments above
+            }
+            else if (opc1 == 0 && opc2 == 4 && CRn == 7 && CRm == 5) {
+                // ARMv6 ISB instruction - do nothing now, see comments above
+            }
+            else {
+                MOZ_CRASH();
+            }
+        } else {
+            MOZ_CRASH();
+        }
+    } else {
+        // MRC, MRC2
+        MOZ_CRASH();
+    }
+}
+
+void
 Simulator::decodeTypeVFP(SimInstruction *instr)
 {
     MOZ_ASSERT(instr->typeValue() == 7 && instr->bit(24) == 0);
     MOZ_ASSERT(instr->bits(11, 9) == 0x5);
 
     // Obtain double precision register codes.
     VFPRegPrecision precision = (instr->szValue() == 1) ? kDoublePrecision : kSinglePrecision;
     int vm = instr->VFPMRegValue(precision);
@@ -4072,16 +4104,25 @@ Simulator::decodeSpecialCondition(SimIns
         break;
       case 0xB:
         if (instr->bits(22, 20) == 5 && instr->bits(15, 12) == 0xf) {
             // pld: ignore instruction.
         } else {
             MOZ_CRASH();
         }
         break;
+      case 0x1C:
+      case 0x1D:
+        if (instr->bit(4) == 1 && instr->bits(11,9) != 5) {
+            // MCR, MCR2, MRC, MRC2 with cond == 15
+            decodeType7CoprocessorIns(instr);
+        } else {
+            MOZ_CRASH();
+        }
+        break;
       default:
         MOZ_CRASH();
     }
 }
 
 // Executes the current instruction.
 void
 Simulator::instructionDecode(SimInstruction *instr)
--- a/js/src/jit/arm/Simulator-arm.h
+++ b/js/src/jit/arm/Simulator-arm.h
@@ -259,16 +259,19 @@ class Simulator
     void decodeSpecialCondition(SimInstruction *instr);
 
     void decodeVMOVBetweenCoreAndSinglePrecisionRegisters(SimInstruction *instr);
     void decodeVCMP(SimInstruction *instr);
     void decodeVCVTBetweenDoubleAndSingle(SimInstruction *instr);
     void decodeVCVTBetweenFloatingPointAndInteger(SimInstruction *instr);
     void decodeVCVTBetweenFloatingPointAndIntegerFrac(SimInstruction *instr);
 
+    // Support for some system functions.
+    void decodeType7CoprocessorIns(SimInstruction *instr);
+
     // Executes one instruction.
     void instructionDecode(SimInstruction *instr);
 
   public:
     static bool ICacheCheckingEnabled;
     static void FlushICache(void *start, size_t size);
 
     static int64_t StopSimAt;