Bug 1609319 - [MIPS] Rename jit::Opcode to jit::OpcodeField to avoid conflicts with wasm::Opcode. r=lth
authorZhao Jiazhong <zhaojiazhong-hf@loongson.cn>
Thu, 16 Jan 2020 06:23:45 +0000
changeset 510441 76d2813008374a2e1cfc4443de4b3c12d9ef2c3f
parent 510440 4a3321b64a58ff2725e01470099c97cd90cda0f2
child 510442 22135e7e31430e6cc90872111a0d7a6b5100bef1
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Bug 1609319 - [MIPS] Rename jit::Opcode to jit::OpcodeField to avoid conflicts with wasm::Opcode. r=lth Differential Revision: https://phabricator.services.mozilla.com/D59979
js/src/jit/mips-shared/Assembler-mips-shared.cpp
js/src/jit/mips-shared/Assembler-mips-shared.h
js/src/jit/mips32/Simulator-mips32.cpp
js/src/jit/mips64/Simulator-mips64.cpp
--- a/js/src/jit/mips-shared/Assembler-mips-shared.cpp
+++ b/js/src/jit/mips-shared/Assembler-mips-shared.cpp
@@ -1938,17 +1938,17 @@ uint8_t* AssemblerMIPSShared::NextInstru
 }
 
 // Since there are no pools in MIPS implementation, this should be simple.
 Instruction* Instruction::next() { return this + 1; }
 
 InstImm AssemblerMIPSShared::invertBranch(InstImm branch,
                                           BOffImm16 skipOffset) {
   uint32_t rt = 0;
-  Opcode op = (Opcode)(branch.extractOpcode() << OpcodeShift);
+  OpcodeField op = (OpcodeField)(branch.extractOpcode() << OpcodeShift);
   switch (op) {
     case op_beq:
       branch.setBOffImm16(skipOffset);
       branch.setOpcode(op_bne);
       return branch;
     case op_bne:
       branch.setBOffImm16(skipOffset);
       branch.setOpcode(op_beq);
@@ -2015,17 +2015,17 @@ void AssemblerMIPSShared::UpdateLuiOriVa
   MOZ_ASSERT(inst1->extractOpcode() == ((uint32_t)op_ori >> OpcodeShift));
 
   ((InstImm*)inst0)->setImm16(Imm16::Upper(Imm32(value)));
   ((InstImm*)inst1)->setImm16(Imm16::Lower(Imm32(value)));
 }
 
 #ifdef JS_JITSPEW
 void AssemblerMIPSShared::decodeBranchInstAndSpew(InstImm branch) {
-  Opcode op = (Opcode)(branch.extractOpcode() << OpcodeShift);
+  OpcodeField op = (OpcodeField)(branch.extractOpcode() << OpcodeShift);
   uint32_t rt_id;
   uint32_t rs_id;
   uint32_t immi = branch.extractImm16Value();
   uint32_t fcc;
   switch (op) {
     case op_beq:
       rt_id = branch.extractRT();
       rs_id = branch.extractRS();
--- a/js/src/jit/mips-shared/Assembler-mips-shared.h
+++ b/js/src/jit/mips-shared/Assembler-mips-shared.h
@@ -216,17 +216,17 @@ uint32_t SA(FloatRegister r);
 uint32_t FS(uint32_t value);
 
 Register toRS(Instruction& i);
 Register toRT(Instruction& i);
 Register toRD(Instruction& i);
 Register toR(Instruction& i);
 
 // MIPS enums for instruction fields
-enum Opcode {
+enum OpcodeField {
   op_special = 0 << OpcodeShift,
   op_regimm = 1 << OpcodeShift,
 
   op_j = 2 << OpcodeShift,
   op_jal = 3 << OpcodeShift,
   op_beq = 4 << OpcodeShift,
   op_bne = 5 << OpcodeShift,
   op_blez = 6 << OpcodeShift,
@@ -1320,18 +1320,18 @@ class Instruction {
     return (encode() >> lo) & ((2 << (hi - lo)) - 1);
   }
   // Since all MIPS instructions have opcode, the opcode
   // extractor resides in the base class.
   uint32_t extractOpcode() {
     return extractBitField(OpcodeShift + OpcodeBits - 1, OpcodeShift);
   }
   // Return the fields at their original place in the instruction encoding.
-  Opcode OpcodeFieldRaw() const {
-    return static_cast<Opcode>(encode() & OpcodeMask);
+  OpcodeField OpcodeFieldRaw() const {
+    return static_cast<OpcodeField>(encode() & OpcodeMask);
   }
 
   // Get the next instruction in the instruction stream.
   // This does neat things like ignoreconstant pools and their guards.
   Instruction* next();
 
   // Sometimes, an api wants a uint32_t (or a pointer to it) rather than
   // an instruction.  raw() just coerces this into a pointer to a uint32_t
@@ -1346,51 +1346,52 @@ static_assert(sizeof(Instruction) == 4,
 class InstNOP : public Instruction {
  public:
   InstNOP() : Instruction(NopInst) {}
 };
 
 // Class for register type instructions.
 class InstReg : public Instruction {
  public:
-  InstReg(Opcode op, Register rd, FunctionField ff)
+  InstReg(OpcodeField op, Register rd, FunctionField ff)
       : Instruction(op | RD(rd) | ff) {}
-  InstReg(Opcode op, Register rs, Register rt, FunctionField ff)
+  InstReg(OpcodeField op, Register rs, Register rt, FunctionField ff)
       : Instruction(op | RS(rs) | RT(rt) | ff) {}
-  InstReg(Opcode op, Register rs, Register rt, Register rd, FunctionField ff)
+  InstReg(OpcodeField op, Register rs, Register rt, Register rd,
+          FunctionField ff)
       : Instruction(op | RS(rs) | RT(rt) | RD(rd) | ff) {}
-  InstReg(Opcode op, Register rs, Register rt, Register rd, uint32_t sa,
+  InstReg(OpcodeField op, Register rs, Register rt, Register rd, uint32_t sa,
           FunctionField ff)
       : Instruction(op | RS(rs) | RT(rt) | RD(rd) | SA(sa) | ff) {}
-  InstReg(Opcode op, RSField rs, Register rt, Register rd, uint32_t sa,
+  InstReg(OpcodeField op, RSField rs, Register rt, Register rd, uint32_t sa,
           FunctionField ff)
       : Instruction(op | rs | RT(rt) | RD(rd) | SA(sa) | ff) {}
-  InstReg(Opcode op, Register rs, RTField rt, Register rd, uint32_t sa,
+  InstReg(OpcodeField op, Register rs, RTField rt, Register rd, uint32_t sa,
           FunctionField ff)
       : Instruction(op | RS(rs) | rt | RD(rd) | SA(sa) | ff) {}
-  InstReg(Opcode op, Register rs, uint32_t cc, Register rd, uint32_t sa,
+  InstReg(OpcodeField op, Register rs, uint32_t cc, Register rd, uint32_t sa,
           FunctionField ff)
       : Instruction(op | RS(rs) | cc | RD(rd) | SA(sa) | ff) {}
-  InstReg(Opcode op, uint32_t code, FunctionField ff)
+  InstReg(OpcodeField op, uint32_t code, FunctionField ff)
       : Instruction(op | code | ff) {}
   // for float point
-  InstReg(Opcode op, RSField rs, Register rt, uint32_t fs)
+  InstReg(OpcodeField op, RSField rs, Register rt, uint32_t fs)
       : Instruction(op | rs | RT(rt) | FS(fs)) {}
-  InstReg(Opcode op, RSField rs, Register rt, FloatRegister rd)
+  InstReg(OpcodeField op, RSField rs, Register rt, FloatRegister rd)
       : Instruction(op | rs | RT(rt) | RD(rd)) {}
-  InstReg(Opcode op, RSField rs, Register rt, FloatRegister rd, uint32_t sa,
-          FunctionField ff)
+  InstReg(OpcodeField op, RSField rs, Register rt, FloatRegister rd,
+          uint32_t sa, FunctionField ff)
       : Instruction(op | rs | RT(rt) | RD(rd) | SA(sa) | ff) {}
-  InstReg(Opcode op, RSField rs, Register rt, FloatRegister fs,
+  InstReg(OpcodeField op, RSField rs, Register rt, FloatRegister fs,
           FloatRegister fd, FunctionField ff)
       : Instruction(op | rs | RT(rt) | RD(fs) | SA(fd) | ff) {}
-  InstReg(Opcode op, RSField rs, FloatRegister ft, FloatRegister fs,
+  InstReg(OpcodeField op, RSField rs, FloatRegister ft, FloatRegister fs,
           FloatRegister fd, FunctionField ff)
       : Instruction(op | rs | RT(ft) | RD(fs) | SA(fd) | ff) {}
-  InstReg(Opcode op, RSField rs, FloatRegister ft, FloatRegister fd,
+  InstReg(OpcodeField op, RSField rs, FloatRegister ft, FloatRegister fd,
           uint32_t sa, FunctionField ff)
       : Instruction(op | rs | RT(ft) | RD(fd) | SA(sa) | ff) {}
 
   uint32_t extractRS() {
     return extractBitField(RSShift + RSBits - 1, RSShift);
   }
   uint32_t extractRT() {
     return extractBitField(RTShift + RTBits - 1, RTShift);
@@ -1406,33 +1407,33 @@ class InstReg : public Instruction {
   }
 };
 
 // Class for branch, load and store instructions with immediate offset.
 class InstImm : public Instruction {
  public:
   void extractImm16(BOffImm16* dest);
 
-  InstImm(Opcode op, Register rs, Register rt, BOffImm16 off)
+  InstImm(OpcodeField op, Register rs, Register rt, BOffImm16 off)
       : Instruction(op | RS(rs) | RT(rt) | off.encode()) {}
-  InstImm(Opcode op, Register rs, RTField rt, BOffImm16 off)
+  InstImm(OpcodeField op, Register rs, RTField rt, BOffImm16 off)
       : Instruction(op | RS(rs) | rt | off.encode()) {}
-  InstImm(Opcode op, RSField rs, uint32_t cc, BOffImm16 off)
+  InstImm(OpcodeField op, RSField rs, uint32_t cc, BOffImm16 off)
       : Instruction(op | rs | cc | off.encode()) {}
-  InstImm(Opcode op, Register rs, Register rt, Imm16 off)
+  InstImm(OpcodeField op, Register rs, Register rt, Imm16 off)
       : Instruction(op | RS(rs) | RT(rt) | off.encode()) {}
   InstImm(uint32_t raw) : Instruction(raw) {}
   // For floating-point loads and stores.
-  InstImm(Opcode op, Register rs, FloatRegister rt, Imm16 off)
+  InstImm(OpcodeField op, Register rs, FloatRegister rt, Imm16 off)
       : Instruction(op | RS(rs) | RT(rt) | off.encode()) {}
 
   uint32_t extractOpcode() {
     return extractBitField(OpcodeShift + OpcodeBits - 1, OpcodeShift);
   }
-  void setOpcode(Opcode op) { data = (data & ~OpcodeMask) | op; }
+  void setOpcode(OpcodeField op) { data = (data & ~OpcodeMask) | op; }
   uint32_t extractRS() {
     return extractBitField(RSShift + RSBits - 1, RSShift);
   }
   uint32_t extractRT() {
     return extractBitField(RTShift + RTBits - 1, RTShift);
   }
   void setRT(RTField rt) { data = (data & ~RTMask) | rt; }
   uint32_t extractImm16Value() {
@@ -1446,43 +1447,44 @@ class InstImm : public Instruction {
     // Reset immediate field and replace it
     data = (data & ~Imm16Mask) | off.encode();
   }
 };
 
 // Class for Jump type instructions.
 class InstJump : public Instruction {
  public:
-  InstJump(Opcode op, JOffImm26 off) : Instruction(op | off.encode()) {}
+  InstJump(OpcodeField op, JOffImm26 off) : Instruction(op | off.encode()) {}
 
   uint32_t extractImm26Value() {
     return extractBitField(Imm26Shift + Imm26Bits - 1, Imm26Shift);
   }
 };
 
 // Class for Loongson-specific instructions
 class InstGS : public Instruction {
  public:
   // For indexed loads and stores.
-  InstGS(Opcode op, Register rs, Register rt, Register rd, Imm8 off,
+  InstGS(OpcodeField op, Register rs, Register rt, Register rd, Imm8 off,
          FunctionField ff)
       : Instruction(op | RS(rs) | RT(rt) | RD(rd) | off.encode(3) | ff) {}
-  InstGS(Opcode op, Register rs, FloatRegister rt, Register rd, Imm8 off,
+  InstGS(OpcodeField op, Register rs, FloatRegister rt, Register rd, Imm8 off,
          FunctionField ff)
       : Instruction(op | RS(rs) | RT(rt) | RD(rd) | off.encode(3) | ff) {}
   // For quad-word loads and stores.
-  InstGS(Opcode op, Register rs, Register rt, Register rz, GSImm13 off,
+  InstGS(OpcodeField op, Register rs, Register rt, Register rz, GSImm13 off,
          FunctionField ff)
       : Instruction(op | RS(rs) | RT(rt) | RZ(rz) | off.encode(6) | ff) {}
-  InstGS(Opcode op, Register rs, FloatRegister rt, FloatRegister rz,
+  InstGS(OpcodeField op, Register rs, FloatRegister rt, FloatRegister rz,
          GSImm13 off, FunctionField ff)
       : Instruction(op | RS(rs) | RT(rt) | RZ(rz) | off.encode(6) | ff) {}
   InstGS(uint32_t raw) : Instruction(raw) {}
   // For floating-point unaligned loads and stores.
-  InstGS(Opcode op, Register rs, FloatRegister rt, Imm8 off, FunctionField ff)
+  InstGS(OpcodeField op, Register rs, FloatRegister rt, Imm8 off,
+         FunctionField ff)
       : Instruction(op | RS(rs) | RT(rt) | off.encode(6) | ff) {}
 };
 
 inline bool IsUnaligned(const wasm::MemoryAccessDesc& access) {
   if (!access.align()) {
     return false;
   }
 
--- a/js/src/jit/mips32/Simulator-mips32.cpp
+++ b/js/src/jit/mips32/Simulator-mips32.cpp
@@ -101,18 +101,19 @@ class SimInstruction {
 
   // Instruction type.
   enum Type { kRegisterType, kImmediateType, kJumpType, kUnsupported = -1 };
 
   // Get the encoding type of the instruction.
   Type instructionType() const;
 
   // Accessors for the different named fields used in the MIPS encoding.
-  inline Opcode opcodeValue() const {
-    return static_cast<Opcode>(bits(OpcodeShift + OpcodeBits - 1, OpcodeShift));
+  inline OpcodeField opcodeValue() const {
+    return static_cast<OpcodeField>(
+        bits(OpcodeShift + OpcodeBits - 1, OpcodeShift));
   }
 
   inline int rsValue() const {
     MOZ_ASSERT(instructionType() == kRegisterType ||
                instructionType() == kImmediateType);
     return bits(RSShift + RSBits - 1, RSShift);
   }
 
@@ -157,18 +158,18 @@ class SimInstruction {
   }
 
   // Float Branch true/false instruction bit.
   inline int fbtrueValue() const {
     return bits(FBtrueShift + FBtrueBits - 1, FBtrueShift);
   }
 
   // Return the fields at their original place in the instruction encoding.
-  inline Opcode opcodeFieldRaw() const {
-    return static_cast<Opcode>(instructionBits() & OpcodeMask);
+  inline OpcodeField opcodeFieldRaw() const {
+    return static_cast<OpcodeField>(instructionBits() & OpcodeMask);
   }
 
   inline int rsFieldRaw() const {
     MOZ_ASSERT(instructionType() == kRegisterType ||
                instructionType() == kImmediateType);
     return instructionBits() & RSMask;
   }
 
@@ -192,17 +193,17 @@ class SimInstruction {
   }
 
   inline int functionFieldRaw() const {
     return instructionBits() & FunctionMask;
   }
 
   // Get the secondary field according to the opcode.
   inline int secondaryValue() const {
-    Opcode op = opcodeFieldRaw();
+    OpcodeField op = opcodeFieldRaw();
     switch (op) {
       case op_special:
       case op_special2:
         return functionValue();
       case op_cop1:
         return rsValue();
       case op_regimm:
         return rtValue();
@@ -2231,17 +2232,17 @@ void Simulator::configureTypeRegister(Si
                                       int32_t& next_pc,
                                       int32_t& return_addr_reg,
                                       bool& do_interrupt) {
   // Every local variable declared here needs to be const.
   // This is to make sure that changed values are sent back to
   // decodeTypeRegister correctly.
 
   // Instruction fields.
-  const Opcode op = instr->opcodeFieldRaw();
+  const OpcodeField op = instr->opcodeFieldRaw();
   const int32_t rs_reg = instr->rsValue();
   const int32_t rs = getRegister(rs_reg);
   const uint32_t rs_u = static_cast<uint32_t>(rs);
   const int32_t rt_reg = instr->rtValue();
   const int32_t rt = getRegister(rt_reg);
   const uint32_t rt_u = static_cast<uint32_t>(rt);
   const int32_t rd_reg = instr->rdValue();
   const uint32_t sa = instr->saValue();
@@ -2481,17 +2482,17 @@ void Simulator::configureTypeRegister(Si
       break;
     default:
       MOZ_CRASH();
   }
 }
 
 void Simulator::decodeTypeRegister(SimInstruction* instr) {
   // Instruction fields.
-  const Opcode op = instr->opcodeFieldRaw();
+  const OpcodeField op = instr->opcodeFieldRaw();
   const int32_t rs_reg = instr->rsValue();
   const int32_t rs = getRegister(rs_reg);
   const uint32_t rs_u = static_cast<uint32_t>(rs);
   const int32_t rt_reg = instr->rtValue();
   const int32_t rt = getRegister(rt_reg);
   const uint32_t rt_u = static_cast<uint32_t>(rt);
   const int32_t rd_reg = instr->rdValue();
 
@@ -3041,17 +3042,17 @@ void Simulator::decodeTypeRegister(SimIn
     default:
       setRegister(rd_reg, alu_out);
   }
 }
 
 // Type 2: instructions using a 16 bytes immediate. (e.g. addi, beq).
 void Simulator::decodeTypeImmediate(SimInstruction* instr) {
   // Instruction fields.
-  Opcode op = instr->opcodeFieldRaw();
+  OpcodeField op = instr->opcodeFieldRaw();
   int32_t rs = getRegister(instr->rsValue());
   uint32_t rs_u = static_cast<uint32_t>(rs);
   int32_t rt_reg = instr->rtValue();  // Destination register.
   int32_t rt = getRegister(rt_reg);
   int16_t imm16 = instr->imm16Value();
 
   int32_t ft_reg = instr->ftValue();  // Destination register.
 
--- a/js/src/jit/mips64/Simulator-mips64.cpp
+++ b/js/src/jit/mips64/Simulator-mips64.cpp
@@ -109,18 +109,19 @@ class SimInstruction {
 
   // Instruction type.
   enum Type { kRegisterType, kImmediateType, kJumpType, kUnsupported = -1 };
 
   // Get the encoding type of the instruction.
   Type instructionType() const;
 
   // Accessors for the different named fields used in the MIPS encoding.
-  inline Opcode opcodeValue() const {
-    return static_cast<Opcode>(bits(OpcodeShift + OpcodeBits - 1, OpcodeShift));
+  inline OpcodeField opcodeValue() const {
+    return static_cast<OpcodeField>(
+        bits(OpcodeShift + OpcodeBits - 1, OpcodeShift));
   }
 
   inline int rsValue() const {
     MOZ_ASSERT(instructionType() == kRegisterType ||
                instructionType() == kImmediateType);
     return bits(RSShift + RSBits - 1, RSShift);
   }
 
@@ -165,18 +166,18 @@ class SimInstruction {
   }
 
   // Float Branch true/false instruction bit.
   inline int fbtrueValue() const {
     return bits(FBtrueShift + FBtrueBits - 1, FBtrueShift);
   }
 
   // Return the fields at their original place in the instruction encoding.
-  inline Opcode opcodeFieldRaw() const {
-    return static_cast<Opcode>(instructionBits() & OpcodeMask);
+  inline OpcodeField opcodeFieldRaw() const {
+    return static_cast<OpcodeField>(instructionBits() & OpcodeMask);
   }
 
   inline int rsFieldRaw() const {
     MOZ_ASSERT(instructionType() == kRegisterType ||
                instructionType() == kImmediateType);
     return instructionBits() & RSMask;
   }
 
@@ -200,17 +201,17 @@ class SimInstruction {
   }
 
   inline int functionFieldRaw() const {
     return instructionBits() & FunctionMask;
   }
 
   // Get the secondary field according to the opcode.
   inline int secondaryValue() const {
-    Opcode op = opcodeFieldRaw();
+    OpcodeField op = opcodeFieldRaw();
     switch (op) {
       case op_special:
       case op_special2:
         return functionValue();
       case op_cop1:
         return rsValue();
       case op_regimm:
         return rtValue();
@@ -2341,17 +2342,17 @@ void Simulator::configureTypeRegister(Si
                                       int64_t& next_pc,
                                       int32_t& return_addr_reg,
                                       bool& do_interrupt) {
   // Every local variable declared here needs to be const.
   // This is to make sure that changed values are sent back to
   // decodeTypeRegister correctly.
 
   // Instruction fields.
-  const Opcode op = instr->opcodeFieldRaw();
+  const OpcodeField op = instr->opcodeFieldRaw();
   const int32_t rs_reg = instr->rsValue();
   const int64_t rs = getRegister(rs_reg);
   const int32_t rt_reg = instr->rtValue();
   const int64_t rt = getRegister(rt_reg);
   const int32_t rd_reg = instr->rdValue();
   const uint32_t sa = instr->saValue();
 
   const int32_t fs_reg = instr->fsValue();
@@ -2775,17 +2776,17 @@ void Simulator::configureTypeRegister(Si
     default:
       MOZ_CRASH();
   };
 }
 
 // Handle execution based on instruction types.
 void Simulator::decodeTypeRegister(SimInstruction* instr) {
   // Instruction fields.
-  const Opcode op = instr->opcodeFieldRaw();
+  const OpcodeField op = instr->opcodeFieldRaw();
   const int32_t rs_reg = instr->rsValue();
   const int64_t rs = getRegister(rs_reg);
   const int32_t rt_reg = instr->rtValue();
   const int64_t rt = getRegister(rt_reg);
   const int32_t rd_reg = instr->rdValue();
 
   const int32_t fr_reg = instr->frValue();
   const int32_t fs_reg = instr->fsValue();
@@ -3404,17 +3405,17 @@ void Simulator::decodeTypeRegister(SimIn
     default:
       setRegister(rd_reg, alu_out);
   };
 }
 
 // Type 2: instructions using a 16 bits immediate. (e.g. addi, beq).
 void Simulator::decodeTypeImmediate(SimInstruction* instr) {
   // Instruction fields.
-  Opcode op = instr->opcodeFieldRaw();
+  OpcodeField op = instr->opcodeFieldRaw();
   int64_t rs = getRegister(instr->rsValue());
   int32_t rt_reg = instr->rtValue();  // Destination register.
   int64_t rt = getRegister(rt_reg);
   int16_t imm16 = instr->imm16Value();
 
   int32_t ft_reg = instr->ftValue();  // Destination register.
 
   // Zero extended immediate.