[arm] b=462430, implement LIR_ldcs, re-enable regexp jit for ARM
authorVladimir Vukicevic <vladimir@pobox.com>
Sun, 09 Nov 2008 17:36:30 -0800
changeset 21551 703a0fdffe3868fd730e42db595933558692f5d0
parent 21548 9d4c8de84579657075eff652b694e188d4b6d5dd
child 21552 d8718260ba23d98f4608e7c0755b3e9e45d81886
push id3572
push uservladimir@mozilla.com
push dateMon, 10 Nov 2008 07:28:32 +0000
treeherdermozilla-central@60733588d123 [default view] [failures only]
perfherder[talos] [build metrics] [platform microbench] (compared to previous push)
bugs462430
milestone1.9.1b2pre
[arm] b=462430, implement LIR_ldcs, re-enable regexp jit for ARM
js/src/jsregexp.cpp
js/src/nanojit/NativeARM.cpp
js/src/nanojit/NativeARM.h
--- a/js/src/jsregexp.cpp
+++ b/js/src/jsregexp.cpp
@@ -61,22 +61,16 @@
 #include "jsnum.h"
 #include "jsobj.h"
 #include "jsopcode.h"
 #include "jsregexp.h"
 #include "jsscan.h"
 #include "jsscope.h"
 #include "jsstr.h"
 
-#ifdef NANOJIT_ARM
-// Something's broken with regexp tracing on ARM;
-// disable to get everything else limping along.
-#undef JS_TRACER
-#endif
-
 #ifdef JS_TRACER
 #include "jstracer.h"
 using namespace avmplus;
 using namespace nanojit;
 
 /* 
  * FIXME  Duplicated with jstracer.cpp, doing it this way for now
  *        to keep it private to files that need it. 
--- a/js/src/nanojit/NativeARM.cpp
+++ b/js/src/nanojit/NativeARM.cpp
@@ -1390,20 +1390,24 @@ void
 Assembler::asm_ld(LInsp ins)
 {
     LOpcode op = ins->opcode();
     LIns* base = ins->oprnd1();
     LIns* disp = ins->oprnd2();
     Register rr = prepResultReg(ins, GpRegs);
     int d = disp->constval();
     Register ra = getBaseReg(base, d, GpRegs);
-    if (op == LIR_ldcb)
-        LD8Z(rr, d, ra);
+    if (op == LIR_ld || op == LIR_ldc)
+        LD(rr, d, ra);
+    else if (op == LIR_ldcb)
+        LDRB(rr, d, ra);
+    else if (op == LIR_ldcs)
+        LDRH(rr, d, ra);
     else
-        LD(rr, d, ra);
+        NanoAssertMsg(0, "Unsupported instruction in asm_ld");
 }
 
 void
 Assembler::asm_cmov(LInsp ins)
 {
     LOpcode op = ins->opcode();
     LIns* condval = ins->oprnd1();
     NanoAssert(condval->isCmp());
--- a/js/src/nanojit/NativeARM.h
+++ b/js/src/nanojit/NativeARM.h
@@ -528,27 +528,35 @@ typedef enum {
         } else {                                                        \
             underrunProtect(LD32_size);                                 \
             LD32_nochk(_d, (_imm));                                     \
             asm_output2("ld  %s,0x%x",gpn((_d)),(_imm));                \
         }                                                               \
     } while(0)
 
 
-// load 8-bit, zero extend (aka LDRB)
-// note, only 5-bit offsets (!) are supported for this, but that's all we need at the moment
-// (LDRB actually allows 12-bit offset in ARM mode but constraining to 5-bit gives us advantage for Thumb)
-// @todo, untested!
-#define LD8Z(_d,_off,_b) do {                                           \
-        NanoAssert((d)>=0&&(d)<=31);                                    \
+// load 8-bit, zero extend (aka LDRB) note, only 5-bit offsets (!) are
+// supported for this, but that's all we need at the moment.
+// (LDRB/LDRH actually allow a 12-bit offset in ARM mode but
+// constraining to 5-bit gives us advantage for Thumb)
+#define LDRB(_d,_off,_b) do {                                           \
+        NanoAssert((_off)>=0&&(_off)<=31);                              \
         underrunProtect(4);                                             \
-        *(--_nIns) = (NIns)( COND_AL | (0x5D<<20) | ((_b)<<16) | ((_d)<<12) |  ((_off)&0xfff)  ); \
+        *(--_nIns) = (NIns)( COND_AL | (0x5D<<20) | ((_b)<<16) | ((_d)<<12) | ((_off)&0xfff)  ); \
         asm_output3("ldrb %s,%d(%s)", gpn(_d),(_off),gpn(_b));          \
     } while(0)
 
+// P and U
+#define LDRH(_d,_off,_b) do {                  \
+        NanoAssert((_off)>=0&&(_off)<=31);      \
+        underrunProtect(4);                     \
+        *(--_nIns) = (NIns)( COND_AL | (0x1D<<20) | ((_b)<<16) | ((_d)<<12) | ((0xB)<<4) | (((_off)&0xf0)<<4) | ((_off)&0xf) ); \
+        asm_output3("ldrsh %s,%d(%s)", gpn(_d),(_off),gpn(_b));         \
+    } while(0)
+
 #define STR(_d,_n,_off) do {                                            \
         NanoAssert(!IsFpReg(_d) && isS12(_off));                        \
         underrunProtect(4);                                             \
         if ((_off)<0)   *(--_nIns) = (NIns)( COND_AL | (0x50<<20) | ((_n)<<16) | ((_d)<<12) | ((-(_off))&0xFFF) ); \
         else            *(--_nIns) = (NIns)( COND_AL | (0x58<<20) | ((_n)<<16) | ((_d)<<12) | ((_off)&0xFFF) ); \
         asm_output3("str %s, [%s, #%d]", gpn(_d), gpn(_n), (_off)); \
     } while(0)