Bug 1393723 - Fix incorrect lowering of wasm i64 load/stores on mips. r=lth
authorDragan Mladjenovic <dragan.mladjenovic@rt-rk.com>
Fri, 25 Aug 2017 02:48:00 -0400
changeset 377603 540cd433f474a086491951ea61954320d6fae928
parent 377602 27ce9e7b7648a110e0e23c21f74487d97a5ec070
child 377604 166c94ca628c67ec704a4056984985218d669b0b
push id32411
push userkwierso@gmail.com
push dateTue, 29 Aug 2017 23:14:35 +0000
treeherdermozilla-central@db7f19e26e57 [default view] [failures only]
perfherder[talos] [build metrics] [platform microbench] (compared to previous push)
reviewerslth
bugs1393723
milestone57.0a1
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Bug 1393723 - Fix incorrect lowering of wasm i64 load/stores on mips. r=lth
js/src/jit/mips-shared/Lowering-mips-shared.cpp
js/src/jit/mips32/CodeGenerator-mips32.cpp
--- a/js/src/jit/mips-shared/Lowering-mips-shared.cpp
+++ b/js/src/jit/mips-shared/Lowering-mips-shared.cpp
@@ -332,17 +332,23 @@ LIRGeneratorMIPSShared::visitWasmNeg(MWa
 }
 
 void
 LIRGeneratorMIPSShared::visitWasmLoad(MWasmLoad* ins)
 {
     MDefinition* base = ins->base();
     MOZ_ASSERT(base->type() == MIRType::Int32);
 
-    LAllocation ptr = useRegisterAtStart(base);
+    LAllocation ptr;
+#ifdef JS_CODEGEN_MIPS32
+    if (ins->type() == MIRType::Int64)
+        ptr = useRegister(base);
+    else
+#endif
+        ptr = useRegisterAtStart(base);
 
     if (IsUnaligned(ins->access())) {
         if (ins->type() == MIRType::Int64) {
             auto* lir = new(alloc()) LWasmUnalignedLoadI64(ptr, temp());
             if (ins->access().offset())
                 lir->setTemp(0, tempCopy(base, 0));
 
             defineInt64(lir, ins);
@@ -378,17 +384,17 @@ LIRGeneratorMIPSShared::visitWasmStore(M
 {
     MDefinition* base = ins->base();
     MOZ_ASSERT(base->type() == MIRType::Int32);
 
     MDefinition* value = ins->value();
     LAllocation baseAlloc = useRegisterAtStart(base);
 
     if (IsUnaligned(ins->access())) {
-        if (ins->type() == MIRType::Int64) {
+        if (ins->access().type() == Scalar::Int64) {
             LInt64Allocation valueAlloc = useInt64RegisterAtStart(value);
             auto* lir = new(alloc()) LWasmUnalignedStoreI64(baseAlloc, valueAlloc, temp());
             if (ins->access().offset())
                 lir->setTemp(0, tempCopy(base, 0));
 
             add(lir, ins);
             return;
         }
@@ -397,17 +403,17 @@ LIRGeneratorMIPSShared::visitWasmStore(M
         auto* lir = new(alloc()) LWasmUnalignedStore(baseAlloc, valueAlloc, temp());
         if (ins->access().offset())
             lir->setTemp(0, tempCopy(base, 0));
 
         add(lir, ins);
         return;
     }
 
-    if (ins->type() == MIRType::Int64) {
+    if (ins->access().type() == Scalar::Int64) {
         LInt64Allocation valueAlloc = useInt64RegisterAtStart(value);
         auto* lir = new(alloc()) LWasmStoreI64(baseAlloc, valueAlloc);
         if (ins->access().offset())
             lir->setTemp(0, tempCopy(base, 0));
 
         add(lir, ins);
         return;
     }
--- a/js/src/jit/mips32/CodeGenerator-mips32.cpp
+++ b/js/src/jit/mips32/CodeGenerator-mips32.cpp
@@ -492,16 +492,17 @@ CodeGeneratorMIPS::emitWasmLoadI64(T* li
                                    temp, static_cast<LoadStoreSize>(8 * byteSize),
                                    isSigned ? SignExtend : ZeroExtend);
             if (!isSigned)
                 masm.move32(Imm32(0), output.high);
             else
                 masm.ma_sra(output.high, output.low, Imm32(31));
         } else {
             ScratchRegisterScope scratch(masm);
+            MOZ_ASSERT(output.low != ptr);
             masm.ma_load_unaligned(output.low, BaseIndex(HeapReg, ptr, TimesOne),
                                    temp, SizeWord, isSigned ? SignExtend : ZeroExtend);
             masm.ma_addu(scratch, ptr, Imm32(INT64HIGH_OFFSET));
             masm.ma_load_unaligned(output.high, BaseIndex(HeapReg, scratch, TimesOne),
                                    temp, SizeWord, isSigned ? SignExtend : ZeroExtend);
         }
         return;
     }
@@ -510,16 +511,17 @@ CodeGeneratorMIPS::emitWasmLoadI64(T* li
         masm.ma_load(output.low, BaseIndex(HeapReg, ptr, TimesOne),
                      static_cast<LoadStoreSize>(8 * byteSize), isSigned ? SignExtend : ZeroExtend);
         if (!isSigned)
             masm.move32(Imm32(0), output.high);
         else
             masm.ma_sra(output.high, output.low, Imm32(31));
     } else {
         ScratchRegisterScope scratch(masm);
+        MOZ_ASSERT(output.low != ptr);
         masm.ma_load(output.low, BaseIndex(HeapReg, ptr, TimesOne), SizeWord);
         masm.ma_addu(scratch, ptr, Imm32(INT64HIGH_OFFSET));
         masm.ma_load(output.high, BaseIndex(HeapReg, scratch, TimesOne), SizeWord);
     }
 
     masm.memoryBarrier(mir->access().barrierAfter());
 }