Bug 1096707 - SpiderMonkey: Use consistent operand order for round[sp][sd] and cmpps
authorDan Gohman <sunfish@mozilla.com>
Tue, 02 Dec 2014 08:26:26 -0800
changeset 218256 2e1da9ea1c9fd11839b180103a2a340f3abf5c2e
parent 218255 80b2348e3ab6b7a8c91733597eff20711436e4c5
child 218257 2fbdfbae0a6e23e255fabb70e65d8e593ae057b4
push id27925
push usercbook@mozilla.com
push dateWed, 03 Dec 2014 12:32:33 +0000
treeherdermozilla-central@59b7bf5d119d [default view] [failures only]
perfherder[talos] [build metrics] [platform microbench] (compared to previous push)
bugs1096707
milestone37.0a1
first release with
nightly linux32
nightly linux64
nightly mac
nightly win32
nightly win64
last release without
nightly linux32
nightly linux64
nightly mac
nightly win32
nightly win64
Bug 1096707 - SpiderMonkey: Use consistent operand order for round[sp][sd] and cmpps
js/src/jit/shared/Assembler-x86-shared.h
js/src/jit/shared/BaseAssembler-x86-shared.h
js/src/jit/shared/CodeGenerator-x86-shared.cpp
--- a/js/src/jit/shared/Assembler-x86-shared.h
+++ b/js/src/jit/shared/Assembler-x86-shared.h
@@ -1670,46 +1670,46 @@ class AssemblerX86Shared : public Assemb
             break;
           case Operand::MEM_ADDRESS32:
             masm.pcmpgtd_mr(src.address(), dest.code());
             break;
           default:
             MOZ_CRASH("unexpected operand kind");
         }
     }
-    void cmpps(const Operand &src, FloatRegister dest, uint8_t order) {
+    void cmpps(uint8_t order, const Operand &src, FloatRegister dest) {
         MOZ_ASSERT(HasSSE2());
         switch (src.kind()) {
           case Operand::FPREG:
-            masm.cmpps_rr(src.fpu(), dest.code(), order);
+            masm.cmpps_rr(order, src.fpu(), dest.code());
             break;
           case Operand::MEM_REG_DISP:
-            masm.cmpps_mr(src.disp(), src.base(), dest.code(), order);
+            masm.cmpps_mr(order, src.disp(), src.base(), dest.code());
             break;
           case Operand::MEM_ADDRESS32:
-            masm.cmpps_mr(src.address(), dest.code(), order);
+            masm.cmpps_mr(order, src.address(), dest.code());
             break;
           default:
             MOZ_CRASH("unexpected operand kind");
         }
     }
     void cmpeqps(const Operand &src, FloatRegister dest) {
-        cmpps(src, dest, X86Assembler::ConditionCmp_EQ);
+        cmpps(X86Assembler::ConditionCmp_EQ, src, dest);
     }
     void cmpltps(const Operand &src, FloatRegister dest) {
-        cmpps(src, dest, X86Assembler::ConditionCmp_LT);
+        cmpps(X86Assembler::ConditionCmp_LT, src, dest);
     }
     void cmpleps(const Operand &src, FloatRegister dest) {
-        cmpps(src, dest, X86Assembler::ConditionCmp_LE);
+        cmpps(X86Assembler::ConditionCmp_LE, src, dest);
     }
     void cmpunordps(const Operand &src, FloatRegister dest) {
-        cmpps(src, dest, X86Assembler::ConditionCmp_UNORD);
+        cmpps(X86Assembler::ConditionCmp_UNORD, src, dest);
     }
     void cmpneqps(const Operand &src, FloatRegister dest) {
-        cmpps(src, dest, X86Assembler::ConditionCmp_NEQ);
+        cmpps(X86Assembler::ConditionCmp_NEQ, src, dest);
     }
     void rcpps(const Operand &src, FloatRegister dest) {
         MOZ_ASSERT(HasSSE2());
         switch (src.kind()) {
           case Operand::FPREG:
             masm.rcpps_rr(src.fpu(), dest.code());
             break;
           case Operand::MEM_REG_DISP:
@@ -2168,23 +2168,23 @@ class AssemblerX86Shared : public Assemb
     void sqrtsd(FloatRegister src, FloatRegister dest) {
         MOZ_ASSERT(HasSSE2());
         masm.sqrtsd_rr(src.code(), dest.code());
     }
     void sqrtss(FloatRegister src, FloatRegister dest) {
         MOZ_ASSERT(HasSSE2());
         masm.sqrtss_rr(src.code(), dest.code());
     }
-    void roundsd(FloatRegister src, FloatRegister dest, X86Assembler::RoundingMode mode) {
+    void roundsd(X86Assembler::RoundingMode mode, FloatRegister src, FloatRegister dest) {
         MOZ_ASSERT(HasSSE41());
-        masm.roundsd_rr(src.code(), dest.code(), mode);
+        masm.roundsd_rr(mode, src.code(), dest.code());
     }
-    void roundss(FloatRegister src, FloatRegister dest, X86Assembler::RoundingMode mode) {
+    void roundss(X86Assembler::RoundingMode mode, FloatRegister src, FloatRegister dest) {
         MOZ_ASSERT(HasSSE41());
-        masm.roundss_rr(src.code(), dest.code(), mode);
+        masm.roundss_rr(mode, src.code(), dest.code());
     }
     unsigned insertpsMask(SimdLane sourceLane, SimdLane destLane, unsigned zeroMask = 0)
     {
         // Note that the sourceLane bits are ignored in the case of a source
         // memory operand, and the source is the given 32-bits memory location.
         MOZ_ASSERT(zeroMask < 16);
         unsigned ret = zeroMask ;
         ret |= unsigned(destLane) << 4;
--- a/js/src/jit/shared/BaseAssembler-x86-shared.h
+++ b/js/src/jit/shared/BaseAssembler-x86-shared.h
@@ -685,29 +685,29 @@ public:
         } else {
             m_formatter.oneByteOp64(OP_GROUP1_EvIz, GROUP1_OP_ADD, base, offset);
             m_formatter.immediate32(imm);
         }
     }
 
     void addq_im(int imm, const void* addr)
     {
-        spew("addq       %d, %p", imm, addr);
+        spew("addq       $%d, %p", imm, addr);
         if (CAN_SIGN_EXTEND_8_32(imm)) {
             m_formatter.oneByteOp64(OP_GROUP1_EvIb, GROUP1_OP_ADD, addr);
             m_formatter.immediate8(imm);
         } else {
             m_formatter.oneByteOp64(OP_GROUP1_EvIz, GROUP1_OP_ADD, addr);
             m_formatter.immediate32(imm);
         }
     }
 #endif
     void addl_im(int imm, const void* addr)
     {
-        spew("addl       %d, %p", imm, addr);
+        spew("addl       $%d, %p", imm, addr);
         if (CAN_SIGN_EXTEND_8_32(imm)) {
             m_formatter.oneByteOp(OP_GROUP1_EvIb, GROUP1_OP_ADD, addr);
             m_formatter.immediate8(imm);
         } else {
             m_formatter.oneByteOp(OP_GROUP1_EvIz, GROUP1_OP_ADD, addr);
             m_formatter.immediate32(imm);
         }
     }
@@ -2035,33 +2035,33 @@ public:
         spew("movb       $0x%x, %d(%s,%s,%d)",
              imm, offset, nameIReg(base), nameIReg(index), 1<<scale);
         m_formatter.oneByteOp(OP_GROUP11_EvIb, GROUP11_MOV, base, index, scale, offset);
         m_formatter.immediate8(imm);
     }
 
     void movb_i8m(int imm, const void* addr)
     {
-        spew("movb       %d, %p", imm, addr);
+        spew("movb       $%d, %p", imm, addr);
         m_formatter.oneByteOp_disp32(OP_GROUP11_EvIb, GROUP11_MOV, addr);
         m_formatter.immediate8(imm);
     }
 
     void movw_i16m(int imm, int offset, RegisterID base)
     {
         spew("movw       $0x%x, %s0x%x(%s)",
              imm, PRETTY_PRINT_OFFSET(offset), nameIReg(base));
         m_formatter.prefix(PRE_OPERAND_SIZE);
         m_formatter.oneByteOp(OP_GROUP11_EvIz, GROUP11_MOV, base, offset);
         m_formatter.immediate16(imm);
     }
 
     void movw_i16m(int imm, const void* addr)
     {
-        spew("movw       %d, %p", imm, addr);
+        spew("movw       $%d, %p", imm, addr);
         m_formatter.prefix(PRE_OPERAND_SIZE);
         m_formatter.oneByteOp_disp32(OP_GROUP11_EvIz, GROUP11_MOV, addr);
         m_formatter.immediate16(imm);
     }
 
     void movl_i32m(int imm, int offset, RegisterID base)
     {
         spew("movl       $0x%x, %s0x%x(%s)",
@@ -2200,17 +2200,17 @@ public:
     {
         spew("movq       $%d, %s0x%x(%s)",
              imm, PRETTY_PRINT_OFFSET(offset), nameIReg(base));
         m_formatter.oneByteOp64(OP_GROUP11_EvIz, GROUP11_MOV, base, index, scale, offset);
         m_formatter.immediate32(imm);
     }
     void movq_i32m(int imm, const void* addr)
     {
-        spew("movq       %d, %p", imm, addr);
+        spew("movq       $%d, %p", imm, addr);
         m_formatter.oneByteOp64(OP_GROUP11_EvIz, GROUP11_MOV, addr);
         m_formatter.immediate32(imm);
     }
 
     // Note that this instruction sign-extends its 32-bit immediate field to 64
     // bits and loads the 64-bit value into a 64-bit register.
     //
     // Note also that this is similar to the movl_i32r instruction, except that
@@ -2264,17 +2264,17 @@ public:
         }
 
         spew("movl       %s, %p", nameIReg(4, src), addr);
         m_formatter.oneByteOp(OP_MOV_EvGv, src, addr);
     }
 
     void movl_i32m(int imm, const void* addr)
     {
-        spew("movl       %d, %p", imm, addr);
+        spew("movl       $%d, %p", imm, addr);
         m_formatter.oneByteOp(OP_GROUP11_EvIz, GROUP11_MOV, addr);
         m_formatter.immediate32(imm);
     }
 
     void movb_rm(RegisterID src, int offset, RegisterID base)
     {
         spew("movb       %s, %s0x%x(%s)",
              nameIReg(1, src), PRETTY_PRINT_OFFSET(offset), nameIReg(base));
@@ -2686,34 +2686,34 @@ public:
 
     void pcmpgtd_mr(const void* address, XMMRegisterID dst)
     {
         spew("pcmpgtd    %p, %s",  address, nameFPReg(dst));
         m_formatter.prefix(PRE_SSE_66);
         m_formatter.twoByteOp(OP2_PCMPGTD_VdqWdq, (RegisterID)dst, address);
     }
 
-    void cmpps_rr(XMMRegisterID src, XMMRegisterID dst, uint8_t order)
-    {
-        spew("cmpps      %s, %s, %u", nameFPReg(src), nameFPReg(dst), order);
+    void cmpps_rr(uint8_t order, XMMRegisterID src, XMMRegisterID dst)
+    {
+        spew("cmpps      $%u, %s, %s", order, nameFPReg(src), nameFPReg(dst));
         m_formatter.twoByteOp(OP2_CMPPS_VpsWps, (RegisterID)dst, (RegisterID)src);
         m_formatter.immediate8(order);
     }
 
-    void cmpps_mr(int offset, RegisterID base, XMMRegisterID dst, uint8_t order)
-    {
-        spew("cmpps      %s0x%x(%s), %s, %u",
-             PRETTY_PRINT_OFFSET(offset), nameIReg(base), nameFPReg(dst), order);
+    void cmpps_mr(uint8_t order, int offset, RegisterID base, XMMRegisterID dst)
+    {
+        spew("cmpps      $%u, %s0x%x(%s), %s",
+             order, PRETTY_PRINT_OFFSET(offset), nameIReg(base), nameFPReg(dst));
         m_formatter.twoByteOp(OP2_CMPPS_VpsWps, (RegisterID)dst, base, offset);
         m_formatter.immediate8(order);
     }
 
-    void cmpps_mr(const void* address, XMMRegisterID dst, uint8_t order)
-    {
-        spew("cmpps      %p, %s, %u", address, nameFPReg(dst), order);
+    void cmpps_mr(uint8_t order, const void* address, XMMRegisterID dst)
+    {
+        spew("cmpps      $%u, %p, %s", order, address, nameFPReg(dst));
         m_formatter.twoByteOp(OP2_CMPPS_VpsWps, (RegisterID)dst, address);
         m_formatter.immediate8(order);
     }
 
     void rcpps_rr(XMMRegisterID src, XMMRegisterID dst){
         spew("rcpps      %s, %s", nameFPReg(src), nameFPReg(dst));
         m_formatter.twoByteOp(OP2_RCPPS_VpsWps, (RegisterID)dst, (RegisterID)src);
     }
@@ -3752,27 +3752,27 @@ public:
 
     void sqrtss_rr(XMMRegisterID src, XMMRegisterID dst)
     {
         spew("sqrtss     %s, %s", nameFPReg(src), nameFPReg(dst));
         m_formatter.prefix(PRE_SSE_F3);
         m_formatter.twoByteOp(OP2_SQRTSS_VssWss, (RegisterID)dst, (RegisterID)src);
     }
 
-    void roundsd_rr(XMMRegisterID src, XMMRegisterID dst, RoundingMode mode)
-    {
-        spew("roundsd    %s, %s, %d", nameFPReg(src), nameFPReg(dst), (int)mode);
+    void roundsd_rr(RoundingMode mode, XMMRegisterID src, XMMRegisterID dst)
+    {
+        spew("roundsd    $%d, %s, %s", (int)mode, nameFPReg(src), nameFPReg(dst));
         m_formatter.prefix(PRE_SSE_66);
         m_formatter.threeByteOp(OP3_ROUNDSD_VsdWsd, ESCAPE_ROUNDSD, (RegisterID)dst, (RegisterID)src);
         m_formatter.immediate8(mode);
     }
 
-    void roundss_rr(XMMRegisterID src, XMMRegisterID dst, RoundingMode mode)
-    {
-        spew("roundss    %s, %s, %d", nameFPReg(src), nameFPReg(dst), (int)mode);
+    void roundss_rr(RoundingMode mode, XMMRegisterID src, XMMRegisterID dst)
+    {
+        spew("roundss    $%d, %s, %s", (int)mode, nameFPReg(src), nameFPReg(dst));
         m_formatter.prefix(PRE_SSE_66);
         m_formatter.threeByteOp(OP3_ROUNDSS_VsdWsd, ESCAPE_ROUNDSD, (RegisterID)dst, (RegisterID)src);
         m_formatter.immediate8(mode); // modes are the same for roundsd and roundss
     }
 
     void insertps_irr(unsigned mask, XMMRegisterID src, XMMRegisterID dst)
     {
         MOZ_ASSERT(mask < 256);
--- a/js/src/jit/shared/CodeGenerator-x86-shared.cpp
+++ b/js/src/jit/shared/CodeGenerator-x86-shared.cpp
@@ -1683,17 +1683,17 @@ CodeGeneratorX86Shared::visitFloor(LFloo
 
     if (AssemblerX86Shared::HasSSE41()) {
         // Bail on negative-zero.
         masm.branchNegativeZero(input, output, &bailout);
         if (!bailoutFrom(&bailout, lir->snapshot()))
             return false;
 
         // Round toward -Infinity.
-        masm.roundsd(input, scratch, X86Assembler::RoundDown);
+        masm.roundsd(X86Assembler::RoundDown, input, scratch);
 
         if (!bailoutCvttsd2si(scratch, output, lir->snapshot()))
             return false;
     } else {
         Label negative, end;
 
         // Branch to a slow path for negative inputs. Doesn't catch NaN or -0.
         masm.xorpd(scratch, scratch);
@@ -1746,17 +1746,17 @@ CodeGeneratorX86Shared::visitFloorF(LFlo
 
     if (AssemblerX86Shared::HasSSE41()) {
         // Bail on negative-zero.
         masm.branchNegativeZeroFloat32(input, output, &bailout);
         if (!bailoutFrom(&bailout, lir->snapshot()))
             return false;
 
         // Round toward -Infinity.
-        masm.roundss(input, scratch, X86Assembler::RoundDown);
+        masm.roundss(X86Assembler::RoundDown, input, scratch);
 
         if (!bailoutCvttss2si(scratch, output, lir->snapshot()))
             return false;
     } else {
         Label negative, end;
 
         // Branch to a slow path for negative inputs. Doesn't catch NaN or -0.
         masm.xorps(scratch, scratch);
@@ -1817,17 +1817,17 @@ CodeGeneratorX86Shared::visitCeil(LCeil 
     masm.branchTest32(Assembler::NonZero, output, Imm32(1), &bailout);
     if (!bailoutFrom(&bailout, lir->snapshot()))
         return false;
 
     if (AssemblerX86Shared::HasSSE41()) {
         // x <= -1 or x > -0
         masm.bind(&lessThanMinusOne);
         // Round toward +Infinity.
-        masm.roundsd(input, scratch, X86Assembler::RoundUp);
+        masm.roundsd(X86Assembler::RoundUp, input, scratch);
         return bailoutCvttsd2si(scratch, output, lir->snapshot());
     }
 
     // No SSE4.1
     Label end;
 
     // x >= 0 and x is not -0.0, we can truncate (resp. truncate and add 1) for
     // integer (resp. non-integer) values.
@@ -1873,17 +1873,17 @@ CodeGeneratorX86Shared::visitCeilF(LCeil
     masm.branchTest32(Assembler::NonZero, output, Imm32(1), &bailout);
     if (!bailoutFrom(&bailout, lir->snapshot()))
         return false;
 
     if (AssemblerX86Shared::HasSSE41()) {
         // x <= -1 or x > -0
         masm.bind(&lessThanMinusOne);
         // Round toward +Infinity.
-        masm.roundss(input, scratch, X86Assembler::RoundUp);
+        masm.roundss(X86Assembler::RoundUp, input, scratch);
         return bailoutCvttss2si(scratch, output, lir->snapshot());
     }
 
     // No SSE4.1
     Label end;
 
     // x >= 0 and x is not -0.0, we can truncate (resp. truncate and add 1) for
     // integer (resp. non-integer) values.
@@ -1953,17 +1953,17 @@ CodeGeneratorX86Shared::visitRound(LRoun
     // Input is negative.
     masm.bind(&negative);
     masm.loadConstantDouble(0.5, temp);
 
     if (AssemblerX86Shared::HasSSE41()) {
         // Add 0.5 and round toward -Infinity. The result is stored in the temp
         // register (currently contains 0.5).
         masm.addsd(input, temp);
-        masm.roundsd(temp, scratch, X86Assembler::RoundDown);
+        masm.roundsd(X86Assembler::RoundDown, temp, scratch);
 
         // Truncate.
         if (!bailoutCvttsd2si(scratch, output, lir->snapshot()))
             return false;
 
         // If the result is positive zero, then the actual result is -0. Bail.
         // Otherwise, the truncation will have produced the correct negative integer.
         masm.testl(output, output);
@@ -2044,17 +2044,17 @@ CodeGeneratorX86Shared::visitRoundF(LRou
     // Input is negative.
     masm.bind(&negative);
     masm.loadConstantFloat32(0.5f, temp);
 
     if (AssemblerX86Shared::HasSSE41()) {
         // Add 0.5 and round toward -Infinity. The result is stored in the temp
         // register (currently contains 0.5).
         masm.addss(input, temp);
-        masm.roundss(temp, scratch, X86Assembler::RoundDown);
+        masm.roundss(X86Assembler::RoundDown, temp, scratch);
 
         // Truncate.
         if (!bailoutCvttss2si(scratch, output, lir->snapshot()))
             return false;
 
         // If the result is positive zero, then the actual result is -0. Bail.
         // Otherwise, the truncation will have produced the correct negative integer.
         masm.testl(output, output);