Bug 547232 - solaris nanojit compiler error LIR_qcmov is not defined. r=stejohns
authorLeon Sha<leon.sha@sun.com>
Tue, 02 Mar 2010 12:24:17 +0800
changeset 40242 065bbe536a935e14674fbc043066ad28fcc5ccf9
parent 40241 4885f541537e728e2134b28dc9cb5c8ddf2e65d2
child 40243 74757beda82fabbfd7e1bafa9d47451b08c08642
push id12610
push userrsayre@mozilla.com
push dateMon, 05 Apr 2010 17:26:41 +0000
treeherdermozilla-central@1942c0b4e101 [default view] [failures only]
perfherder[talos] [build metrics] [platform microbench] (compared to previous push)
reviewersstejohns
bugs547232
milestone1.9.3a2pre
Bug 547232 - solaris nanojit compiler error LIR_qcmov is not defined. r=stejohns
js/src/nanojit/NativeSparc.cpp
--- a/js/src/nanojit/NativeSparc.cpp
+++ b/js/src/nanojit/NativeSparc.cpp
@@ -673,21 +673,21 @@ namespace nanojit
                 else if (op == LIR_ush)
                     SRL(rr, rb, rr);
                 else
                     NanoAssertMsg(0, "Unsupported");
             }
         else
             {
                 int c = rhs->imm32();
-                if (op == LIR_add || op == LIR_iaddp || op == LIR_addxov) {
+                if (op == LIR_add || op == LIR_iaddp || op == LIR_addxov)
                     ADDCC(rr, L2, rr);
-                } else if (op == LIR_sub || op == LIR_subxov)
+                else if (op == LIR_sub || op == LIR_subxov)
                     SUBCC(rr, L2, rr);
-                } else if (op == LIR_and)
+                else if (op == LIR_and)
                     AND(rr, L2, rr);
                 else if (op == LIR_or)
                     OR(rr, L2, rr);
                 else if (op == LIR_xor)
                     XOR(rr, L2, rr);
                 else if (op == LIR_lsh)
                     SLL(rr, L2, rr);
                 else if (op == LIR_rsh)
@@ -778,18 +778,16 @@ namespace nanojit
             case LIR_gt:  MOVLE (iffalsereg, 1, 0, 0, rr); break;
             case LIR_ge:  MOVL  (iffalsereg, 1, 0, 0, rr); break;
             case LIR_ult: MOVCC (iffalsereg, 1, 0, 0, rr); break;
             case LIR_ule: MOVGU (iffalsereg, 1, 0, 0, rr); break;
             case LIR_ugt: MOVLEU(iffalsereg, 1, 0, 0, rr); break;
             case LIR_uge: MOVCS (iffalsereg, 1, 0, 0, rr); break;
                 debug_only( default: NanoAssert(0); break; )
                     }
-        } else if (op == LIR_qcmov) {
-            NanoAssert(0);
         }
         /*const Register iftruereg =*/ findSpecificRegFor(iftrue, rr);
         asm_cmp(condval);
     }
 
     void Assembler::asm_param(LInsp ins)
     {
         uint32_t a = ins->paramArg();