third_party/rust/cranelift-codegen-meta/src/isa/arm64/mod.rs
author Benjamin Bouvier <benj@benj.me>
Tue, 30 Apr 2019 14:22:41 +0200
changeset 474110 bc152a886c75ad2b0be20c3c380834fb1447f281
parent 472291 00ca72fd66c249afe66d16ade5d3c6597f939a95
child 476790 ccb4138ed2ff4f4a497492edc96b3f47c9646c5e
permissions -rw-r--r--
Bug 1547682: Bump Cranelift to cc216b46b35a797d03c0f3e8b16a2096f1c6db61; r=lth Differential Revision: https://phabricator.services.mozilla.com/D29343

use crate::cdsl::cpu_modes::CpuMode;
use crate::cdsl::inst::InstructionGroup;
use crate::cdsl::isa::TargetIsa;
use crate::cdsl::regs::{IsaRegs, IsaRegsBuilder, RegBankBuilder, RegClassBuilder};
use crate::cdsl::settings::{SettingGroup, SettingGroupBuilder};

use crate::shared::Definitions as SharedDefinitions;

fn define_settings(_shared: &SettingGroup) -> SettingGroup {
    let setting = SettingGroupBuilder::new("arm64");
    setting.finish()
}

fn define_registers() -> IsaRegs {
    let mut regs = IsaRegsBuilder::new();

    // The `x31` regunit serves as the stack pointer / zero register depending on context. We
    // reserve it and don't model the difference.
    let builder = RegBankBuilder::new("IntRegs", "x")
        .units(32)
        .track_pressure(true);
    let int_regs = regs.add_bank(builder);

    let builder = RegBankBuilder::new("FloatRegs", "v")
        .units(32)
        .track_pressure(true);
    let float_regs = regs.add_bank(builder);

    let builder = RegBankBuilder::new("FlagRegs", "")
        .units(1)
        .names(vec!["nzcv"])
        .track_pressure(false);
    let flag_reg = regs.add_bank(builder);

    let builder = RegClassBuilder::new_toplevel("GPR", int_regs);
    regs.add_class(builder);

    let builder = RegClassBuilder::new_toplevel("FPR", float_regs);
    regs.add_class(builder);

    let builder = RegClassBuilder::new_toplevel("FLAG", flag_reg);
    regs.add_class(builder);

    regs.finish()
}

pub fn define(shared_defs: &mut SharedDefinitions) -> TargetIsa {
    let settings = define_settings(&shared_defs.settings);
    let regs = define_registers();

    let inst_group = InstructionGroup::new("arm64", "arm64 specific instruction set");

    let mut a64 = CpuMode::new("A64");

    // TODO refine these.
    let narrow = shared_defs.transform_groups.by_name("narrow");
    a64.legalize_default(narrow);

    let cpu_modes = vec![a64];

    TargetIsa::new("arm64", inst_group, settings, regs, cpu_modes)
}