Bug 994716 - IonMonkey MIPS: Style fixes, JS_ASSERT to MOZ_ASSERT. r=nbp
authorBranislav Rankov <branislav.rankov@imgtec.com>
Fri, 11 Apr 2014 12:01:39 +0200
changeset 182146 fbfff6e640638d5d65a0c00cc7b6c67436b84245
parent 182145 5fce8c9d9c0ffb82fb7ebd9452ab71cd2f395f91
child 182147 3fe658d898581a7d124e8bf6565abfd66b242d91
push id43220
push userryanvm@gmail.com
push dateThu, 08 May 2014 14:01:22 +0000
treeherdermozilla-inbound@cf209153f20e [default view] [failures only]
perfherder[talos] [build metrics] [platform microbench] (compared to previous push)
reviewersnbp
bugs994716
milestone32.0a1
first release with
nightly linux32
nightly linux64
nightly mac
nightly win32
nightly win64
last release without
nightly linux32
nightly linux64
nightly mac
nightly win32
nightly win64
Bug 994716 - IonMonkey MIPS: Style fixes, JS_ASSERT to MOZ_ASSERT. r=nbp
js/src/jit/mips/Architecture-mips.cpp
js/src/jit/mips/Architecture-mips.h
js/src/jit/mips/Assembler-mips.cpp
js/src/jit/mips/Assembler-mips.h
js/src/jit/mips/MacroAssembler-mips.cpp
--- a/js/src/jit/mips/Architecture-mips.cpp
+++ b/js/src/jit/mips/Architecture-mips.cpp
@@ -25,17 +25,17 @@ uint32_t GetMIPSFlags()
         return flags;
 #if WTF_OS_LINUX
     FILE *fp = fopen("/proc/cpuinfo", "r");
     if (!fp)
         return false;
 
     char buf[1024];
     memset(buf, 0, sizeof(buf));
-    fread(buf, sizeof(char), sizeof(buf)-1, fp);
+    fread(buf, sizeof(char), sizeof(buf) - 1, fp);
     fclose(fp);
     if (strstr(buf, "FPU"))
         flags |= HWCAP_FPU;
 
     isSet = true;
     return flags;
 #endif
 
--- a/js/src/jit/mips/Architecture-mips.h
+++ b/js/src/jit/mips/Architecture-mips.h
@@ -108,17 +108,17 @@ class Registers
     static const char *GetName(Code code) {
         static const char * const Names[] = { "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
                                               "t0",   "t1", "t2", "t3", "t4", "t5", "t6", "t7",
                                               "s0",   "s1", "s2", "s3", "s4", "s5", "s6", "s7",
                                               "t8",   "t9", "k0", "k1", "gp", "sp", "fp", "ra"};
         return Names[code];
     }
     static const char *GetName(uint32_t i) {
-        JS_ASSERT(i < Total);
+        MOZ_ASSERT(i < Total);
         return GetName(Code(i));
     }
 
     static Code FromName(const char *name);
 
     static const Code StackPointer = sp;
     static const Code Invalid = invalid_reg;
 
@@ -194,17 +194,17 @@ typedef uint32_t PackedRegisterMask;
 // MIPS32 can have two types of floating-point coprocessors:
 // - 32 bit floating-point coprocessor - In this case, there are 32 single
 // precision registers and pairs of even and odd float registers are used as
 // double precision registers. Example: f0 (double) is composed of
 // f0 and f1 (single).
 // - 64 bit floating-point coprocessor - In this case, there are 32 double
 // precision register which can also be used as single precision registers.
 
-// When using O32 ABI, floating-point coprocessor is 32 bit
+// When using O32 ABI, floating-point coprocessor is 32 bit.
 // When using N32 ABI, floating-point coprocessor is 64 bit.
 class FloatRegisters
 {
   public:
     enum FPRegisterID {
         f0 = 0,
         f1,
         f2,
@@ -245,17 +245,17 @@ class FloatRegisters
         static const char * const Names[] = { "f0", "f1", "f2", "f3",  "f4", "f5",  "f6", "f7",
                                               "f8", "f9",  "f10", "f11", "f12", "f13",
                                               "f14", "f15", "f16", "f17", "f18", "f19",
                                               "f20", "f21", "f22", "f23", "f24", "f25",
                                               "f26", "f27", "f28", "f29", "f30", "f31"};
         return Names[code];
     }
     static const char *GetName(uint32_t i) {
-        JS_ASSERT(i < Total);
+        MOZ_ASSERT(i < Total);
         return GetName(Code(i));
     }
 
     static Code FromName(const char *name);
 
     static const Code Invalid = invalid_freg;
 
     static const uint32_t Total = 32;
--- a/js/src/jit/mips/Assembler-mips.cpp
+++ b/js/src/jit/mips/Assembler-mips.cpp
@@ -36,59 +36,59 @@ ABIArgGenerator::next(MIRType type)
 const Register ABIArgGenerator::NonArgReturnVolatileReg0 = t0;
 const Register ABIArgGenerator::NonArgReturnVolatileReg1 = t1;
 
 // Encode a standard register when it is being used as rd, the rs, and
 // an extra register(rt). These should never be called with an InvalidReg.
 uint32_t
 js::jit::RS(Register r)
 {
-    JS_ASSERT((r.code() & ~RegMask) == 0);
+    MOZ_ASSERT((r.code() & ~RegMask) == 0);
     return r.code() << RSShift;
 }
 
 uint32_t
 js::jit::RT(Register r)
 {
-    JS_ASSERT((r.code() & ~RegMask) == 0);
+    MOZ_ASSERT((r.code() & ~RegMask) == 0);
     return r.code() << RTShift;
 }
 
 uint32_t
 js::jit::RT(FloatRegister r)
 {
-    JS_ASSERT(r.code() < FloatRegisters::Total);
+    MOZ_ASSERT(r.code() < FloatRegisters::Total);
     return r.code() << RTShift;
 }
 
 uint32_t
 js::jit::RD(Register r)
 {
-    JS_ASSERT((r.code() & ~RegMask) == 0);
+    MOZ_ASSERT((r.code() & ~RegMask) == 0);
     return r.code() << RDShift;
 }
 
 uint32_t
 js::jit::RD(FloatRegister r)
 {
-    JS_ASSERT(r.code() < FloatRegisters::Total);
+    MOZ_ASSERT(r.code() < FloatRegisters::Total);
     return r.code() << RDShift;
 }
 
 uint32_t
 js::jit::SA(uint32_t value)
 {
-    JS_ASSERT(value < 32);
+    MOZ_ASSERT(value < 32);
     return value << SAShift;
 }
 
 uint32_t
 js::jit::SA(FloatRegister r)
 {
-    JS_ASSERT(r.code() < FloatRegisters::Total);
+    MOZ_ASSERT(r.code() < FloatRegisters::Total);
     return r.code() << SAShift;
 }
 
 Register
 js::jit::toRS(Instruction &i)
 {
     return Register::FromCode((i.encode() & RSMask ) >> RSShift);
 }
@@ -127,24 +127,24 @@ jit::PatchJump(CodeLocationJump &jump_, 
     Assembler::updateLuiOriValue(inst1, inst2, (uint32_t)label.raw());
 
     AutoFlushCache::updateTop(uintptr_t(inst1), 8);
 }
 
 void
 Assembler::finish()
 {
-    JS_ASSERT(!isFinished);
+    MOZ_ASSERT(!isFinished);
     isFinished = true;
 }
 
 void
 Assembler::executableCopy(uint8_t *buffer)
 {
-    JS_ASSERT(isFinished);
+    MOZ_ASSERT(isFinished);
     m_buffer.executableCopy(buffer);
 
     // Patch all long jumps during code copy.
     for (size_t i = 0; i < longJumps_.length(); i++) {
         Instruction *inst1 = (Instruction *) ((uint32_t)buffer + longJumps_[i]);
 
         uint32_t value = extractLuiOriValue(inst1, inst1->next());
         updateLuiOriValue(inst1, inst1->next(), (uint32_t)buffer + value);
@@ -275,17 +275,17 @@ Assembler::copyPreBarrierTable(uint8_t *
 void
 Assembler::trace(JSTracer *trc)
 {
     for (size_t i = 0; i < jumps_.length(); i++) {
         RelativePatch &rp = jumps_[i];
         if (rp.kind == Relocation::JITCODE) {
             JitCode *code = JitCode::FromExecutable((uint8_t *)rp.target);
             MarkJitCodeUnbarriered(trc, &code, "masmrel32");
-            JS_ASSERT(code == JitCode::FromExecutable((uint8_t *)rp.target));
+            MOZ_ASSERT(code == JitCode::FromExecutable((uint8_t *)rp.target));
         }
     }
     if (dataRelocations_.length()) {
         CompactBufferReader reader(dataRelocations_);
         ::TraceDataRelocations(trc, &m_buffer, reader);
     }
 }
 
@@ -455,33 +455,33 @@ Assembler::writeInst(uint32_t x, uint32_
 
     writeInstStatic(x, dest);
     return BufferOffset();
 }
 
 void
 Assembler::writeInstStatic(uint32_t x, uint32_t *dest)
 {
-    JS_ASSERT(dest != nullptr);
+    MOZ_ASSERT(dest != nullptr);
     *dest = x;
 }
 
 BufferOffset
 Assembler::align(int alignment)
 {
     BufferOffset ret;
-    JS_ASSERT(m_buffer.isAligned(4));
+    MOZ_ASSERT(m_buffer.isAligned(4));
     if (alignment == 8) {
         if (!m_buffer.isAligned(alignment)) {
             BufferOffset tmp = as_nop();
             if (!ret.assigned())
                 ret = tmp;
         }
     } else {
-        JS_ASSERT((alignment & (alignment - 1)) == 0);
+        MOZ_ASSERT((alignment & (alignment - 1)) == 0);
         while (size() & (alignment - 1)) {
             BufferOffset tmp = as_nop();
             if (!ret.assigned())
                 ret = tmp;
         }
     }
     return ret;
 }
@@ -515,31 +515,31 @@ BufferOffset
 Assembler::as_nor(Register rd, Register rs, Register rt)
 {
     return writeInst(InstReg(op_special, rs, rt, rd, ff_nor).encode());
 }
 
 BufferOffset
 Assembler::as_andi(Register rd, Register rs, int32_t j)
 {
-    JS_ASSERT(Imm16::isInUnsignedRange(j));
+    MOZ_ASSERT(Imm16::isInUnsignedRange(j));
     return writeInst(InstImm(op_andi, rs, rd, Imm16(j)).encode());
 }
 
 BufferOffset
 Assembler::as_ori(Register rd, Register rs, int32_t j)
 {
-    JS_ASSERT(Imm16::isInUnsignedRange(j));
+    MOZ_ASSERT(Imm16::isInUnsignedRange(j));
     return writeInst(InstImm(op_ori, rs, rd, Imm16(j)).encode());
 }
 
 BufferOffset
 Assembler::as_xori(Register rd, Register rs, int32_t j)
 {
-    JS_ASSERT(Imm16::isInUnsignedRange(j));
+    MOZ_ASSERT(Imm16::isInUnsignedRange(j));
     return writeInst(InstImm(op_xori, rs, rd, Imm16(j)).encode());
 }
 
 // Branch and jump instructions
 BufferOffset
 Assembler::as_bal(BOffImm16 off)
 {
     BufferOffset bo = writeInst(InstImm(op_regimm, zero, rt_bgezal, off).encode());
@@ -553,17 +553,17 @@ Assembler::getBranchCode(JumpOrCall jump
         return InstImm(op_regimm, zero, rt_bgezal, BOffImm16(0));
 
     return InstImm(op_beq, zero, zero, BOffImm16(0));
 }
 
 InstImm
 Assembler::getBranchCode(Register s, Register t, Condition c)
 {
-    JS_ASSERT(c == Assembler::Equal || c == Assembler::NotEqual);
+    MOZ_ASSERT(c == Assembler::Equal || c == Assembler::NotEqual);
     return InstImm(c == Assembler::Equal ? op_beq : op_bne, s, t, BOffImm16(0));
 }
 
 InstImm
 Assembler::getBranchCode(Register s, Condition c)
 {
     switch (c) {
       case Assembler::Equal:
@@ -587,17 +587,17 @@ Assembler::getBranchCode(Register s, Con
       default:
         MOZ_ASSUME_UNREACHABLE("Condition not supported.");
     }
 }
 
 InstImm
 Assembler::getBranchCode(FloatTestKind testKind, FPConditionBit fcc)
 {
-    JS_ASSERT(!(fcc && FccMask));
+    MOZ_ASSERT(!(fcc && FccMask));
     uint32_t rtField = ((testKind == TestForTrue ? 1 : 0) | (fcc << FccShift)) << RTShift;
 
     return InstImm(op_cop1, rs_bc1, rtField, BOffImm16(0));
 }
 
 BufferOffset
 Assembler::as_j(JOffImm26 off)
 {
@@ -630,17 +630,17 @@ BufferOffset
 Assembler::as_addu(Register rd, Register rs, Register rt)
 {
     return writeInst(InstReg(op_special, rs, rt, rd, ff_addu).encode());
 }
 
 BufferOffset
 Assembler::as_addiu(Register rd, Register rs, int32_t j)
 {
-    JS_ASSERT(Imm16::isInSignedRange(j));
+    MOZ_ASSERT(Imm16::isInSignedRange(j));
     return writeInst(InstImm(op_addiu, rs, rd, Imm16(j)).encode());
 }
 
 BufferOffset
 Assembler::as_subu(Register rd, Register rs, Register rt)
 {
     return writeInst(InstReg(op_special, rs, rt, rd, ff_subu).encode());
 }
@@ -673,64 +673,64 @@ BufferOffset
 Assembler::as_mul(Register rd, Register rs, Register rt)
 {
     return writeInst(InstReg(op_special2, rs, rt, rd, ff_mul).encode());
 }
 
 BufferOffset
 Assembler::as_lui(Register rd, int32_t j)
 {
-    JS_ASSERT(Imm16::isInUnsignedRange(j));
+    MOZ_ASSERT(Imm16::isInUnsignedRange(j));
     return writeInst(InstImm(op_lui, zero, rd, Imm16(j)).encode());
 }
 
 // Shift instructions
 BufferOffset
 Assembler::as_sll(Register rd, Register rt, uint16_t sa)
 {
-    JS_ASSERT(sa < 32);
+    MOZ_ASSERT(sa < 32);
     return writeInst(InstReg(op_special, rs_zero, rt, rd, sa, ff_sll).encode());
 }
 
 BufferOffset
 Assembler::as_sllv(Register rd, Register rt, Register rs)
 {
     return writeInst(InstReg(op_special, rs, rt, rd, ff_sllv).encode());
 }
 
 BufferOffset
 Assembler::as_srl(Register rd, Register rt, uint16_t sa)
 {
-    JS_ASSERT(sa < 32);
+    MOZ_ASSERT(sa < 32);
     return writeInst(InstReg(op_special, rs_zero, rt, rd, sa, ff_srl).encode());
 }
 
 BufferOffset
 Assembler::as_srlv(Register rd, Register rt, Register rs)
 {
     return writeInst(InstReg(op_special, rs, rt, rd, ff_srlv).encode());
 }
 
 BufferOffset
 Assembler::as_sra(Register rd, Register rt, uint16_t sa)
 {
-    JS_ASSERT(sa < 32);
+    MOZ_ASSERT(sa < 32);
     return writeInst(InstReg(op_special, rs_zero, rt, rd, sa, ff_sra).encode());
 }
 
 BufferOffset
 Assembler::as_srav(Register rd, Register rt, Register rs)
 {
     return writeInst(InstReg(op_special, rs, rt, rd, ff_srav).encode());
 }
 
 BufferOffset
 Assembler::as_rotr(Register rd, Register rt, uint16_t sa)
 {
-    JS_ASSERT(sa < 32);
+    MOZ_ASSERT(sa < 32);
     return writeInst(InstReg(op_special, rs_one, rt, rd, sa, ff_srl).encode());
 }
 
 BufferOffset
 Assembler::as_rotrv(Register rd, Register rt, Register rs)
 {
     return writeInst(InstReg(op_special, rs, rt, rd, 1, ff_srlv).encode());
 }
@@ -832,24 +832,24 @@ BufferOffset
 Assembler::as_sltu(Register rd, Register rs, Register rt)
 {
     return writeInst(InstReg(op_special, rs, rt, rd, ff_sltu).encode());
 }
 
 BufferOffset
 Assembler::as_slti(Register rd, Register rs, int32_t j)
 {
-    JS_ASSERT(Imm16::isInSignedRange(j));
+    MOZ_ASSERT(Imm16::isInSignedRange(j));
     return writeInst(InstImm(op_slti, rs, rd, Imm16(j)).encode());
 }
 
 BufferOffset
 Assembler::as_sltiu(Register rd, Register rs, uint32_t j)
 {
-    JS_ASSERT(Imm16::isInUnsignedRange(j));
+    MOZ_ASSERT(Imm16::isInUnsignedRange(j));
     return writeInst(InstImm(op_sltiu, rs, rd, Imm16(j)).encode());
 }
 
 // Conditional move.
 BufferOffset
 Assembler::as_movz(Register rd, Register rs, Register rt)
 {
     return writeInst(InstReg(op_special, rs, rt, rd, ff_movz).encode());
@@ -882,57 +882,57 @@ BufferOffset
 Assembler::as_clz(Register rd, Register rs, Register rt)
 {
     return writeInst(InstReg(op_special2, rs, rt, rd, ff_clz).encode());
 }
 
 BufferOffset
 Assembler::as_ins(Register rt, Register rs, uint16_t pos, uint16_t size)
 {
-    JS_ASSERT(pos < 32 && size != 0 && size <= 32 && pos + size != 0 && pos + size >= 32);
+    MOZ_ASSERT(pos < 32 && size != 0 && size <= 32 && pos + size != 0 && pos + size >= 32);
     Register rd;
     rd = Register::FromCode(pos + size - 1);
     return writeInst(InstReg(op_special3, rs, rt, rd, pos, ff_ins).encode());
 }
 
 BufferOffset
 Assembler::as_ext(Register rt, Register rs, uint16_t pos, uint16_t size)
 {
-    JS_ASSERT(pos < 32 && size != 0 && size <= 32 && pos + size != 0 && pos + size >= 32);
+    MOZ_ASSERT(pos < 32 && size != 0 && size <= 32 && pos + size != 0 && pos + size >= 32);
     Register rd;
     rd = Register::FromCode(size - 1);
     return writeInst(InstReg(op_special3, rs, rt, rd, pos, ff_ext).encode());
 }
 
 // FP instructions
 BufferOffset
 Assembler::as_ld(FloatRegister fd, Register base, int32_t off)
 {
-    JS_ASSERT(Imm16::isInSignedRange(off));
+    MOZ_ASSERT(Imm16::isInSignedRange(off));
     return writeInst(InstImm(op_ldc1, base, fd, Imm16(off)).encode());
 }
 
 BufferOffset
 Assembler::as_sd(FloatRegister fd, Register base, int32_t off)
 {
-    JS_ASSERT(Imm16::isInSignedRange(off));
+    MOZ_ASSERT(Imm16::isInSignedRange(off));
     return writeInst(InstImm(op_sdc1, base, fd, Imm16(off)).encode());
 }
 
 BufferOffset
 Assembler::as_ls(FloatRegister fd, Register base, int32_t off)
 {
-    JS_ASSERT(Imm16::isInSignedRange(off));
+    MOZ_ASSERT(Imm16::isInSignedRange(off));
     return writeInst(InstImm(op_lwc1, base, fd, Imm16(off)).encode());
 }
 
 BufferOffset
 Assembler::as_ss(FloatRegister fd, Register base, int32_t off)
 {
-    JS_ASSERT(Imm16::isInSignedRange(off));
+    MOZ_ASSERT(Imm16::isInSignedRange(off));
     return writeInst(InstImm(op_swc1, base, fd, Imm16(off)).encode());
 }
 
 BufferOffset
 Assembler::as_movs(FloatRegister fd, FloatRegister fs)
 {
     return writeInst(InstReg(op_cop1, rs_s, zero, fs, fd, ff_mov_fmt).encode());
 }
@@ -1205,17 +1205,17 @@ void
 Assembler::bind(InstImm *inst, uint32_t branch, uint32_t target)
 {
     int32_t offset = target - branch;
     InstImm inst_bgezal = InstImm(op_regimm, zero, rt_bgezal, BOffImm16(0));
     InstImm inst_beq = InstImm(op_beq, zero, zero, BOffImm16(0));
 
     // If encoded offset is 4, then the jump must be short
     if (BOffImm16(inst[0]).decode() == 4) {
-        JS_ASSERT(BOffImm16::isInRange(offset));
+        MOZ_ASSERT(BOffImm16::isInRange(offset));
         inst[0].setBOffImm16(BOffImm16(offset));
         inst[1].makeNop();
         return;
     }
     if (BOffImm16::isInRange(offset)) {
         bool conditional = (inst[0].encode() != inst_bgezal.encode() &&
                             inst[0].encode() != inst_beq.encode());
 
@@ -1294,28 +1294,28 @@ Assembler::retarget(Label *label, Label 
             // target's use chain, prepending the entire use chain of target.
             Instruction *inst = editSrc(labelBranchOffset);
             int32_t prev = target->use(label->offset());
             inst[1].setData(prev);
         } else {
             // The target is unbound and unused.  We can just take the head of
             // the list hanging off of label, and dump that into target.
             DebugOnly<uint32_t> prev = target->use(label->offset());
-            JS_ASSERT((int32_t)prev == Label::INVALID_OFFSET);
+            MOZ_ASSERT((int32_t)prev == Label::INVALID_OFFSET);
         }
     }
     label->reset();
 }
 
 void dbg_break() {}
 static int stopBKPT = -1;
 void
 Assembler::as_break(uint32_t code)
 {
-    JS_ASSERT(code <= MAX_BREAK_CODE);
+    MOZ_ASSERT(code <= MAX_BREAK_CODE);
     writeInst(op_special | code << RTShift | ff_break);
 }
 
 uint32_t
 Assembler::patchWrite_NearCallSize()
 {
     return 4 * sizeof(uint32_t);
 }
@@ -1339,29 +1339,29 @@ Assembler::patchWrite_NearCall(CodeLocat
     AutoFlushCache::updateTop(uintptr_t(inst), patchWrite_NearCallSize());
 }
 
 uint32_t
 Assembler::extractLuiOriValue(Instruction *inst0, Instruction *inst1)
 {
     InstImm *i0 = (InstImm *) inst0;
     InstImm *i1 = (InstImm *) inst1;
-    JS_ASSERT(i0->extractOpcode() == ((uint32_t)op_lui >> OpcodeShift));
-    JS_ASSERT(i1->extractOpcode() == ((uint32_t)op_ori >> OpcodeShift));
+    MOZ_ASSERT(i0->extractOpcode() == ((uint32_t)op_lui >> OpcodeShift));
+    MOZ_ASSERT(i1->extractOpcode() == ((uint32_t)op_ori >> OpcodeShift));
 
     uint32_t value = i0->extractImm16Value() << 16;
     value = value | i1->extractImm16Value();
     return value;
 }
 
 void
 Assembler::updateLuiOriValue(Instruction *inst0, Instruction *inst1, uint32_t value)
 {
-    JS_ASSERT(inst0->extractOpcode() == ((uint32_t)op_lui >> OpcodeShift));
-    JS_ASSERT(inst1->extractOpcode() == ((uint32_t)op_ori >> OpcodeShift));
+    MOZ_ASSERT(inst0->extractOpcode() == ((uint32_t)op_lui >> OpcodeShift));
+    MOZ_ASSERT(inst1->extractOpcode() == ((uint32_t)op_ori >> OpcodeShift));
 
     ((InstImm *) inst0)->setImm16(Imm16::upper(Imm32(value)));
     ((InstImm *) inst1)->setImm16(Imm16::lower(Imm32(value)));
 }
 
 void
 Assembler::writeLuiOriInstructions(Instruction *inst0, Instruction *inst1,
                                    Register reg, uint32_t value)
@@ -1373,17 +1373,17 @@ Assembler::writeLuiOriInstructions(Instr
 void
 Assembler::patchDataWithValueCheck(CodeLocationLabel label, PatchedImmPtr newValue,
                                    PatchedImmPtr expectedValue)
 {
     Instruction *inst = (Instruction *) label.raw();
 
     // Extract old Value
     DebugOnly<uint32_t> value = Assembler::extractLuiOriValue(&inst[0], &inst[1]);
-    JS_ASSERT(value == uint32_t(expectedValue.value));
+    MOZ_ASSERT(value == uint32_t(expectedValue.value));
 
     // Replace with new value
     Assembler::updateLuiOriValue(inst, inst->next(), uint32_t(newValue.value));
 
     AutoFlushCache::updateTop(uintptr_t(inst), 8);
 }
 
 void
@@ -1456,17 +1456,17 @@ InstImm Assembler::invertBranch(InstImm 
             branch.setRT(rt_bltz);
             return branch;
         }
 
         MOZ_ASSUME_UNREACHABLE("Error creating long branch.");
         return branch;
 
       case op_cop1:
-        JS_ASSERT(branch.extractRS() == rs_bc1 >> RSShift);
+        MOZ_ASSERT(branch.extractRS() == rs_bc1 >> RSShift);
 
         branch.setBOffImm16(skipOffset);
         rt = branch.extractRT();
         if (rt & 0x1)
             branch.setRT((RTField) ((rt & ~0x1) << RTShift));
         else
             branch.setRT((RTField) ((rt | 0x1) << RTShift));
         return branch;
@@ -1476,46 +1476,46 @@ InstImm Assembler::invertBranch(InstImm 
     return branch;
 }
 
 void
 Assembler::ToggleToJmp(CodeLocationLabel inst_)
 {
     InstImm * inst = (InstImm *)inst_.raw();
 
-    JS_ASSERT(inst->extractOpcode() == ((uint32_t)op_andi >> OpcodeShift));
+    MOZ_ASSERT(inst->extractOpcode() == ((uint32_t)op_andi >> OpcodeShift));
     // We converted beq to andi, so now we restore it.
     inst->setOpcode(op_beq);
 
     AutoFlushCache::updateTop((uintptr_t)inst, 4);
 }
 
 void
 Assembler::ToggleToCmp(CodeLocationLabel inst_)
 {
     InstImm * inst = (InstImm *)inst_.raw();
 
     // toggledJump is allways used for short jumps.
-    JS_ASSERT(inst->extractOpcode() == ((uint32_t)op_beq >> OpcodeShift));
+    MOZ_ASSERT(inst->extractOpcode() == ((uint32_t)op_beq >> OpcodeShift));
     // Replace "beq $zero, $zero, offset" with "andi $zero, $zero, offset"
     inst->setOpcode(op_andi);
 
     AutoFlushCache::updateTop((uintptr_t)inst, 4);
 }
 
 void
 Assembler::ToggleCall(CodeLocationLabel inst_, bool enabled)
 {
     Instruction *inst = (Instruction *)inst_.raw();
     InstImm *i0 = (InstImm *) inst;
     InstImm *i1 = (InstImm *) i0->next();
     Instruction *i2 = (Instruction *) i1->next();
 
-    JS_ASSERT(i0->extractOpcode() == ((uint32_t)op_lui >> OpcodeShift));
-    JS_ASSERT(i1->extractOpcode() == ((uint32_t)op_ori >> OpcodeShift));
+    MOZ_ASSERT(i0->extractOpcode() == ((uint32_t)op_lui >> OpcodeShift));
+    MOZ_ASSERT(i1->extractOpcode() == ((uint32_t)op_ori >> OpcodeShift));
 
     if (enabled) {
         InstReg jalr = InstReg(op_special, ScratchRegister, zero, ra, ff_jalr);
         *i2 = jalr;
     } else {
         InstNOP nop;
         *i2 = nop;
     }
--- a/js/src/jit/mips/Assembler-mips.h
+++ b/js/src/jit/mips/Assembler-mips.h
@@ -376,29 +376,29 @@ class Operand;
 
 // A BOffImm16 is a 16 bit immediate that is used for branches.
 class BOffImm16
 {
     uint32_t data;
 
   public:
     uint32_t encode() {
-        JS_ASSERT(!isInvalid());
+        MOZ_ASSERT(!isInvalid());
         return data;
     }
     int32_t decode() {
-        JS_ASSERT(!isInvalid());
+        MOZ_ASSERT(!isInvalid());
         return (int32_t(data << 18) >> 16) + 4;
     }
 
     explicit BOffImm16(int offset)
       : data ((offset - 4) >> 2 & Imm16Mask)
     {
-        JS_ASSERT((offset & 0x3) == 0);
-        JS_ASSERT(isInRange(offset));
+        MOZ_ASSERT((offset & 0x3) == 0);
+        MOZ_ASSERT(isInRange(offset));
     }
     static bool isInRange(int offset) {
         if ((offset - 4) < (INT16_MIN << 2))
             return false;
         if ((offset - 4) > (INT16_MAX << 2))
             return false;
         return true;
     }
@@ -417,29 +417,29 @@ class BOffImm16
 
 // A JOffImm26 is a 26 bit immediate that is used for unconditional jumps.
 class JOffImm26
 {
     uint32_t data;
 
   public:
     uint32_t encode() {
-        JS_ASSERT(!isInvalid());
+        MOZ_ASSERT(!isInvalid());
         return data;
     }
     int32_t decode() {
-        JS_ASSERT(!isInvalid());
+        MOZ_ASSERT(!isInvalid());
         return (int32_t(data << 8) >> 6) + 4;
     }
 
     explicit JOffImm26(int offset)
       : data ((offset - 4) >> 2 & Imm26Mask)
     {
-        JS_ASSERT((offset & 0x3) == 0);
-        JS_ASSERT(isInRange(offset));
+        MOZ_ASSERT((offset & 0x3) == 0);
+        MOZ_ASSERT(isInRange(offset));
     }
     static bool isInRange(int offset) {
         if ((offset - 4) < -536870912)
             return false;
         if ((offset - 4) > 536870908)
             return false;
         return true;
     }
@@ -522,45 +522,45 @@ class Operand
       : tag(MEM), reg(addr.base.code()), offset(addr.offset)
     { }
 
     Tag getTag() const {
         return tag;
     }
 
     Register toReg() const {
-        JS_ASSERT(tag == REG);
+        MOZ_ASSERT(tag == REG);
         return Register::FromCode(reg);
     }
 
     FloatRegister toFReg() const {
-        JS_ASSERT(tag == FREG);
+        MOZ_ASSERT(tag == FREG);
         return FloatRegister::FromCode(reg);
     }
 
     void toAddr(Register *r, Imm32 *dest) const {
-        JS_ASSERT(tag == MEM);
+        MOZ_ASSERT(tag == MEM);
         *r = Register::FromCode(reg);
         *dest = Imm32(offset);
     }
     Address toAddress() const {
-        JS_ASSERT(tag == MEM);
+        MOZ_ASSERT(tag == MEM);
         return Address(Register::FromCode(reg), offset);
     }
     int32_t disp() const {
-        JS_ASSERT(tag == MEM);
+        MOZ_ASSERT(tag == MEM);
         return offset;
     }
 
     int32_t base() const {
-        JS_ASSERT(tag == MEM);
+        MOZ_ASSERT(tag == MEM);
         return reg;
     }
     Register baseReg() const {
-        JS_ASSERT(tag == MEM);
+        MOZ_ASSERT(tag == MEM);
         return Register::FromCode(reg);
     }
 };
 
 void
 PatchJump(CodeLocationJump &jump_, CodeLocationLabel label);
 class Assembler;
 typedef js::jit::AssemblerBuffer<1024, Instruction> MIPSBuffer;
@@ -851,17 +851,17 @@ class Assembler : public AssemblerShared
 
     BufferOffset as_mtc1(Register rt, FloatRegister fs);
     BufferOffset as_mfc1(Register rt, FloatRegister fs);
 
   protected:
     // This is used to access the odd regiter form the pair of single
     // precision registers that make one double register.
     FloatRegister getOddPair(FloatRegister reg) {
-        JS_ASSERT(reg.code() % 2 == 0);
+        MOZ_ASSERT(reg.code() % 2 == 0);
         return FloatRegister::FromCode(reg.code() + 1);
     }
 
   public:
     // FP convert instructions
     BufferOffset as_ceilws(FloatRegister fd, FloatRegister fs);
     BufferOffset as_floorws(FloatRegister fd, FloatRegister fs);
     BufferOffset as_roundws(FloatRegister fd, FloatRegister fs);
@@ -1222,34 +1222,34 @@ GetIntArgReg(uint32_t usedArgSlots, Regi
 // actual argument registers to use we will fall back on using whatever
 // CallTempReg* don't overlap the argument registers, and only fail once those
 // run out too.
 static inline bool
 GetTempRegForIntArg(uint32_t usedIntArgs, uint32_t usedFloatArgs, Register *out)
 {
     // NOTE: We can't properly determine which regs are used if there are
     // float arguments. If this is needed, we will have to guess.
-    JS_ASSERT(usedFloatArgs == 0);
+    MOZ_ASSERT(usedFloatArgs == 0);
 
     if (GetIntArgReg(usedIntArgs, out))
         return true;
     // Unfortunately, we have to assume things about the point at which
     // GetIntArgReg returns false, because we need to know how many registers it
     // can allocate.
     usedIntArgs -= NumIntArgRegs;
     if (usedIntArgs >= NumCallTempNonArgRegs)
         return false;
     *out = CallTempNonArgRegs[usedIntArgs];
     return true;
 }
 
 static inline uint32_t
 GetArgStackDisp(uint32_t usedArgSlots)
 {
-    JS_ASSERT(usedArgSlots >= NumIntArgRegs);
+    MOZ_ASSERT(usedArgSlots >= NumIntArgRegs);
     // Even register arguments have place reserved on stack.
     return usedArgSlots * sizeof(intptr_t);
 }
 
 } // namespace jit
 } // namespace js
 
 #endif /* jit_mips_Assembler_mips_h */
--- a/js/src/jit/mips/MacroAssembler-mips.cpp
+++ b/js/src/jit/mips/MacroAssembler-mips.cpp
@@ -3101,17 +3101,18 @@ MacroAssemblerMIPSCompat::passABIArg(con
 }
 
 void
 MacroAssemblerMIPSCompat::passABIArg(const FloatRegister &freg, MoveOp::Type type)
 {
     passABIArg(MoveOperand(freg), type);
 }
 
-void MacroAssemblerMIPSCompat::checkStackAlignment()
+void
+MacroAssemblerMIPSCompat::checkStackAlignment()
 {
 #ifdef DEBUG
     Label aligned;
     as_andi(ScratchRegister, sp, StackAlignment - 1);
     ma_b(ScratchRegister, zero, &aligned, Equal, ShortJump);
     as_break(MAX_BREAK_CODE);
     bind(&aligned);
 #endif