Bug 1208674 - part 1: Add ToggleCall assertions. r=sstangl
authorJakob Olesen <jolesen@mozilla.com>
Sun, 11 Oct 2015 18:13:09 +0200
changeset 267150 d6d3fcb7c0bc0e331a38c49cd0d541ccf9b83501
parent 267149 7c5db9a3a4b1ab8d809c8e5943f911870b8639b5
child 267151 b541b27061614b59483c29efe0ac763f1275e775
push id66402
push userarchaeopteryx@coole-files.de
push dateSun, 11 Oct 2015 16:15:00 +0000
treeherdermozilla-inbound@ee4cb52e6b15 [default view] [failures only]
perfherder[talos] [build metrics] [platform microbench] (compared to previous push)
reviewerssstangl
bugs1208674
milestone44.0a1
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Bug 1208674 - part 1: Add ToggleCall assertions. r=sstangl Assert that the ToggleCall() function does not overwrite any unexpected instructions.
js/src/jit/arm64/Assembler-arm64.cpp
js/src/jit/arm64/vixl/Instructions-vixl.h
js/src/jit/arm64/vixl/MozInstructions-vixl.cpp
--- a/js/src/jit/arm64/Assembler-arm64.cpp
+++ b/js/src/jit/arm64/Assembler-arm64.cpp
@@ -395,32 +395,35 @@ Assembler::ToggleCall(CodeLocationLabel 
         load = first;
         call = NextInstruction(first);
     }
 
     if (call->IsBLR() == enabled)
         return;
 
     if (call->IsBLR()) {
-        // if the second instruction is blr(), then wehave:
-        // ldr x17, [pc, offset]
-        // blr x17
-        // we want to transform this to:
-        // adr xzr, [pc, offset]
-        // nop
+        // If the second instruction is blr(), then wehave:
+        //   ldr x17, [pc, offset]
+        //   blr x17
+        MOZ_ASSERT(load->IsLDR());
+        // We want to transform this to:
+        //   adr xzr, [pc, offset]
+        //   nop
         int32_t offset = load->ImmLLiteral();
         adr(load, xzr, int32_t(offset));
         nop(call);
     } else {
-        // we have adr xzr, [pc, offset]
-        // nop
-        // transform this to
-        // ldr x17, [pc, offset]
-        // blr x17
-
+        // We have:
+        //   adr xzr, [pc, offset] (or ldr x17, [pc, offset])
+        //   nop
+        MOZ_ASSERT(load->IsADR() || load->IsLDR());
+        MOZ_ASSERT(call->IsNOP());
+        // Transform this to:
+        //   ldr x17, [pc, offset]
+        //   blr x17
         int32_t offset = (int)load->ImmPCRawOffset();
         MOZ_ASSERT(vixl::is_int19(offset));
         ldr(load, ScratchReg2_64, int32_t(offset));
         blr(call, ScratchReg2_64);
     }
 }
 
 class RelocationIterator
--- a/js/src/jit/arm64/vixl/Instructions-vixl.h
+++ b/js/src/jit/arm64/vixl/Instructions-vixl.h
@@ -254,16 +254,17 @@ class Instruction {
   bool IsBL() const;
   bool IsBR() const;
   bool IsBLR() const;
   bool IsTBZ() const;
   bool IsTBNZ() const;
   bool IsCBZ() const;
   bool IsCBNZ() const;
   bool IsLDR() const;
+  bool IsNOP() const;
   bool IsADR() const;
   bool IsADRP() const;
   bool IsBranchLinkImm() const;
   bool IsTargetReachable(Instruction* target) const;
   ptrdiff_t ImmPCRawOffset() const;
   void SetBits32(int msb, int lsb, unsigned value);
 
 #define DEFINE_SETTERS(Name, HighBit, LowBit, Func)  \
--- a/js/src/jit/arm64/vixl/MozInstructions-vixl.cpp
+++ b/js/src/jit/arm64/vixl/MozInstructions-vixl.cpp
@@ -73,16 +73,21 @@ bool Instruction::IsCBNZ() const {
 }
 
 
 bool Instruction::IsLDR() const {
   return Mask(LoadLiteralMask) == LDR_x_lit;
 }
 
 
+bool Instruction::IsNOP() const {
+  return Mask(SystemHintMask) == HINT && ImmHint() == NOP;
+}
+
+
 bool Instruction::IsADR() const {
   return Mask(PCRelAddressingMask) == ADR;
 }
 
 
 bool Instruction::IsADRP() const {
   return Mask(PCRelAddressingMask) == ADRP;
 }