Bug 1329650 - Make MIPS32 simulator build pass. r=bbouvier
authorDragan Mladjenovic <dragan.mladjenovic@rt-rk.com>
Wed, 16 Aug 2017 12:11:00 -0400
changeset 375101 c217dd347b01
parent 375100 bfe9b1d9ad11
child 375102 22c5313e3d65
push id93833
push userryanvm@gmail.com
push dateWed, 16 Aug 2017 22:14:15 +0000
treeherdermozilla-inbound@c217dd347b01 [default view] [failures only]
perfherder[talos] [build metrics] [platform microbench] (compared to previous push)
reviewersbbouvier
bugs1329650
milestone57.0a1
first release with
nightly linux32
nightly linux64
nightly mac
nightly win32
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nightly win64
Bug 1329650 - Make MIPS32 simulator build pass. r=bbouvier
js/src/jit/MacroAssembler.h
js/src/jit/mips-shared/CodeGenerator-mips-shared.cpp
js/src/jit/mips-shared/LIR-mips-shared.h
js/src/jit/mips32/CodeGenerator-mips32.cpp
js/src/jit/mips32/MacroAssembler-mips32.cpp
js/src/jit/mips32/MacroAssembler-mips32.h
js/src/jit/mips32/MoveEmitter-mips32.cpp
js/src/jit/mips32/Simulator-mips32.cpp
js/src/jit/mips32/Simulator-mips32.h
js/src/shell/js.cpp
--- a/js/src/jit/MacroAssembler.h
+++ b/js/src/jit/MacroAssembler.h
@@ -483,17 +483,17 @@ class MacroAssembler : public MacroAssem
 #endif // DEBUG
 
   public:
     // ===============================================================
     // Simple call functions.
 
     CodeOffset call(Register reg) PER_SHARED_ARCH;
     CodeOffset call(Label* label) PER_SHARED_ARCH;
-    void call(const Address& addr) DEFINED_ON(x86_shared, arm, arm64, mips32, mips64);
+    void call(const Address& addr) PER_SHARED_ARCH;
     void call(ImmWord imm) PER_SHARED_ARCH;
     // Call a target native function, which is neither traceable nor movable.
     void call(ImmPtr imm) PER_SHARED_ARCH;
     void call(wasm::SymbolicAddress imm) PER_SHARED_ARCH;
     inline void call(const wasm::CallSiteDesc& desc, wasm::SymbolicAddress imm);
 
     // Call a target JitCode, which must be traceable, and may be movable.
     void call(JitCode* c) PER_SHARED_ARCH;
--- a/js/src/jit/mips-shared/CodeGenerator-mips-shared.cpp
+++ b/js/src/jit/mips-shared/CodeGenerator-mips-shared.cpp
@@ -2085,18 +2085,16 @@ CodeGeneratorMIPSShared::visitAsmJSLoadH
             }
         } else {
             masm.ma_load(ToRegister(out), BaseIndex(HeapReg, ptrReg, TimesOne),
                          static_cast<LoadStoreSize>(size), isSigned ? SignExtend : ZeroExtend);
         }
         return;
     }
 
-    BufferOffset bo = masm.ma_BoundsCheck(ScratchRegister);
-
     Label done, outOfRange;
     masm.ma_b(ptrReg, ScratchRegister, &outOfRange, Assembler::AboveOrEqual, ShortJump);
     // Offset is ok, let's load value.
     if (isFloat) {
         if (size == 32)
             masm.loadFloat32(BaseIndex(HeapReg, ptrReg, TimesOne), ToFloatRegister(out));
         else
             masm.loadDouble(BaseIndex(HeapReg, ptrReg, TimesOne), ToFloatRegister(out));
@@ -2174,18 +2172,16 @@ CodeGeneratorMIPSShared::visitAsmJSStore
                 masm.storeDouble(freg, bi);
         } else {
             masm.ma_store(ToRegister(value), BaseIndex(HeapReg, ptrReg, TimesOne),
                           static_cast<LoadStoreSize>(size), isSigned ? SignExtend : ZeroExtend);
         }
         return;
     }
 
-    BufferOffset bo = masm.ma_BoundsCheck(ScratchRegister);
-
     Label outOfRange;
     masm.ma_b(ptrReg, ScratchRegister, &outOfRange, Assembler::AboveOrEqual, ShortJump);
 
     // Offset is ok, let's store value.
     if (isFloat) {
         if (size == 32) {
             masm.storeFloat32(ToFloatRegister(value), BaseIndex(HeapReg, ptrReg, TimesOne));
         } else
--- a/js/src/jit/mips-shared/LIR-mips-shared.h
+++ b/js/src/jit/mips-shared/LIR-mips-shared.h
@@ -303,17 +303,17 @@ namespace details {
 // Base class for the int64 and non-int64 variants.
 template<size_t NumDefs>
 class LWasmUnalignedLoadBase : public details::LWasmLoadBase<NumDefs, 2>
 {
   public:
     typedef LWasmLoadBase<NumDefs, 2> Base;
 
     explicit LWasmUnalignedLoadBase(const LAllocation& ptr, const LDefinition& valueHelper)
-      : Base(ptr,  LAllocation())
+      : Base(ptr, LAllocation())
     {
         Base::setTemp(0, LDefinition::BogusTemp());
         Base::setTemp(1, valueHelper);
     }
     const LAllocation* ptr() {
         return Base::getOperand(0);
     }
     const LDefinition* ptrCopy() {
--- a/js/src/jit/mips32/CodeGenerator-mips32.cpp
+++ b/js/src/jit/mips32/CodeGenerator-mips32.cpp
@@ -405,19 +405,19 @@ CodeGeneratorMIPS::visitDivOrModI64(LDiv
     masm.setupUnalignedABICall(temp);
     masm.passABIArg(lhs.high);
     masm.passABIArg(lhs.low);
     masm.passABIArg(rhs.high);
     masm.passABIArg(rhs.low);
 
     MOZ_ASSERT(gen->compilingWasm());
     if (lir->mir()->isMod())
-        masm.callWithABI(wasm::SymbolicAddress::ModI64);
+        masm.callWithABI(lir->bytecodeOffset(), wasm::SymbolicAddress::ModI64);
     else
-        masm.callWithABI(wasm::SymbolicAddress::DivI64);
+        masm.callWithABI(lir->bytecodeOffset(), wasm::SymbolicAddress::DivI64);
     MOZ_ASSERT(ReturnReg64 == output);
 
     masm.bind(&done);
 }
 
 void
 CodeGeneratorMIPS::visitUDivOrModI64(LUDivOrModI64* lir)
 {
@@ -444,19 +444,19 @@ CodeGeneratorMIPS::visitUDivOrModI64(LUD
     masm.setupUnalignedABICall(temp);
     masm.passABIArg(lhs.high);
     masm.passABIArg(lhs.low);
     masm.passABIArg(rhs.high);
     masm.passABIArg(rhs.low);
 
     MOZ_ASSERT(gen->compilingWasm());
     if (lir->mir()->isMod())
-        masm.callWithABI(wasm::SymbolicAddress::UModI64);
+        masm.callWithABI(lir->bytecodeOffset(), wasm::SymbolicAddress::UModI64);
     else
-        masm.callWithABI(wasm::SymbolicAddress::UDivI64);
+        masm.callWithABI(lir->bytecodeOffset(), wasm::SymbolicAddress::UDivI64);
 }
 
 template <typename T>
 void
 CodeGeneratorMIPS::emitWasmLoadI64(T* lir)
 {
     const MWasmLoad* mir = lir->mir();
     Register64 output = ToOutRegister64(lir);
@@ -742,19 +742,19 @@ CodeGeneratorMIPS::visitWasmTruncateToIn
         masm.convertFloat32ToDouble(input, scratch);
     } else {
         MOZ_CRASH("unexpected type in visitOutOfLineWasmTruncateCheck");
     }
 
     masm.setupUnalignedABICall(output.high);
     masm.passABIArg(scratch, MoveOp::DOUBLE);
     if (lir->mir()->isUnsigned())
-        masm.callWithABI(wasm::SymbolicAddress::TruncateDoubleToUint64);
+        masm.callWithABI(mir->bytecodeOffset(), wasm::SymbolicAddress::TruncateDoubleToUint64);
     else
-        masm.callWithABI(wasm::SymbolicAddress::TruncateDoubleToInt64);
+        masm.callWithABI(mir->bytecodeOffset(), wasm::SymbolicAddress::TruncateDoubleToInt64);
     masm.ma_b(output.high, Imm32(0x80000000), ool->rejoin(), Assembler::NotEqual);
     masm.ma_b(output.low, Imm32(0x00000000), ool->rejoin(), Assembler::NotEqual);
     masm.ma_b(ool->entry());
 
     masm.bind(ool->rejoin());
 
     MOZ_ASSERT(ReturnReg64 == output);
 }
@@ -773,19 +773,19 @@ CodeGeneratorMIPS::visitInt64ToFloatingP
     regs.take(input.high);
     Register temp = regs.takeAny();
 
     masm.setupUnalignedABICall(temp);
     masm.passABIArg(input.high);
     masm.passABIArg(input.low);
 
     if (lir->mir()->isUnsigned())
-        masm.callWithABI(wasm::SymbolicAddress::Uint64ToFloatingPoint, MoveOp::DOUBLE);
+        masm.callWithABI(mir->bytecodeOffset(), wasm::SymbolicAddress::Uint64ToDouble, MoveOp::DOUBLE);
     else
-        masm.callWithABI(wasm::SymbolicAddress::Int64ToFloatingPoint, MoveOp::DOUBLE);
+        masm.callWithABI(mir->bytecodeOffset(), wasm::SymbolicAddress::Int64ToDouble, MoveOp::DOUBLE);
 
     MOZ_ASSERT_IF(toType == MIRType::Double, output == ReturnDoubleReg);
     if (toType == MIRType::Float32) {
          MOZ_ASSERT(output == ReturnFloat32Reg);
          masm.convertDoubleToFloat32(ReturnDoubleReg, output);
     }
 }
 
--- a/js/src/jit/mips32/MacroAssembler-mips32.cpp
+++ b/js/src/jit/mips32/MacroAssembler-mips32.cpp
@@ -1345,17 +1345,17 @@ MacroAssemblerMIPSCompat::unboxValue(con
 
 void
 MacroAssemblerMIPSCompat::unboxPrivate(const ValueOperand& src, Register dest)
 {
     ma_move(dest, src.payloadReg());
 }
 
 void
-MacroAssemblerMIPS64Compat::boxDouble(FloatRegister src, const ValueOperand& dest, FloatRegister)
+MacroAssemblerMIPSCompat::boxDouble(FloatRegister src, const ValueOperand& dest, FloatRegister)
 {
     moveFromDoubleLo(src, dest.payloadReg());
     moveFromDoubleHi(src, dest.typeReg());
 }
 
 void
 MacroAssemblerMIPSCompat::boxNonDouble(JSValueType type, Register src,
                                        const ValueOperand& dest)
@@ -2248,16 +2248,36 @@ MacroAssembler::callWithABINoProfiler(co
 {
     // Load the callee in t9, as above.
     loadPtr(Address(fun.base, fun.offset), t9);
     uint32_t stackAdjust;
     callWithABIPre(&stackAdjust);
     call(t9);
     callWithABIPost(stackAdjust, result);
 }
+// ===============================================================
+// Move instructions
+
+void
+MacroAssembler::moveValue(const TypedOrValueRegister& src, const ValueOperand& dest)
+{
+    MOZ_CRASH("NIY");
+}
+
+void
+MacroAssembler::moveValue(const ValueOperand& src, const ValueOperand& dest)
+{
+    MOZ_CRASH("NIY");
+}
+
+void
+MacroAssembler::moveValue(const Value& src, const ValueOperand& dest)
+{
+    MOZ_CRASH("NIY");
+}
 
 // ===============================================================
 // Branch functions
 
 void
 MacroAssembler::branchValueIsNurseryObject(Condition cond, const Address& address,
                                            Register temp, Label* label)
 {
--- a/js/src/jit/mips32/MacroAssembler-mips32.h
+++ b/js/src/jit/mips32/MacroAssembler-mips32.h
@@ -47,16 +47,17 @@ class MacroAssemblerMIPS : public MacroA
     using MacroAssemblerMIPSShared::ma_b;
     using MacroAssemblerMIPSShared::ma_li;
     using MacroAssemblerMIPSShared::ma_ss;
     using MacroAssemblerMIPSShared::ma_sd;
     using MacroAssemblerMIPSShared::ma_load;
     using MacroAssemblerMIPSShared::ma_store;
     using MacroAssemblerMIPSShared::ma_cmp_set;
     using MacroAssemblerMIPSShared::ma_subTestOverflow;
+    using MacroAssemblerMIPSShared::ma_liPatchable;
 
     void ma_li(Register dest, CodeOffset* label);
 
     void ma_li(Register dest, ImmWord imm);
     void ma_liPatchable(Register dest, ImmPtr imm);
     void ma_liPatchable(Register dest, ImmWord imm);
 
     // load
--- a/js/src/jit/mips32/MoveEmitter-mips32.cpp
+++ b/js/src/jit/mips32/MoveEmitter-mips32.cpp
@@ -41,16 +41,17 @@ MoveEmitterMIPS::breakCycle(const MoveOp
             masm.loadDouble(getAdjustedAddress(to), temp);
             masm.storeDouble(temp, cycleSlot(slotId, 0));
         } else {
             masm.storeDouble(to.floatReg(), cycleSlot(slotId, 0));
         }
         break;
       case MoveOp::INT32:
         MOZ_ASSERT(sizeof(uintptr_t) == sizeof(int32_t));
+        MOZ_FALLTHROUGH;
       case MoveOp::GENERAL:
         if (to.isMemory()) {
             Register temp = tempReg();
             masm.loadPtr(getAdjustedAddress(to), temp);
             masm.storePtr(temp, cycleSlot(0, 0));
         } else {
             // Second scratch register should not be moved by MoveEmitter.
             MOZ_ASSERT(to.reg() != spilledReg_);
@@ -91,16 +92,17 @@ MoveEmitterMIPS::completeCycle(const Mov
             masm.loadDouble(cycleSlot(slotId, 0), temp);
             masm.storeDouble(temp, getAdjustedAddress(to));
         } else {
             masm.loadDouble(cycleSlot(slotId, 0), to.floatReg());
         }
         break;
       case MoveOp::INT32:
         MOZ_ASSERT(sizeof(uintptr_t) == sizeof(int32_t));
+        MOZ_FALLTHROUGH;
       case MoveOp::GENERAL:
         MOZ_ASSERT(slotId == 0);
         if (to.isMemory()) {
             Register temp = tempReg();
             masm.loadPtr(cycleSlot(0, 0), temp);
             masm.storePtr(temp, getAdjustedAddress(to));
         } else {
             // Second scratch register should not be moved by MoveEmitter.
--- a/js/src/jit/mips32/Simulator-mips32.cpp
+++ b/js/src/jit/mips32/Simulator-mips32.cpp
@@ -32,16 +32,18 @@
 #include "mozilla/FloatingPoint.h"
 #include "mozilla/Likely.h"
 #include "mozilla/MathAlgorithms.h"
 
 #include <float.h>
 
 #include "jit/mips32/Assembler-mips32.h"
 #include "vm/Runtime.h"
+#include "wasm/WasmInstance.h"
+#include "wasm/WasmSignalHandlers.h"
 
 #define I8(v)   static_cast<int8_t>(v)
 #define I16(v)  static_cast<int16_t>(v)
 #define U16(v)  static_cast<uint16_t>(v)
 #define I32(v)  static_cast<int32_t>(v)
 #define U32(v)  static_cast<uint32_t>(v)
 
 namespace js {
@@ -1255,17 +1257,17 @@ Simulator::Simulator()
     // Note, allocation and anything that depends on allocated memory is
     // deferred until init(), in order to handle OOM properly.
 
     stack_ = nullptr;
     stackLimit_ = 0;
     pc_modified_ = false;
     icount_ = 0;
     break_count_ = 0;
-    resume_pc_ = 0;
+    wasm_interrupt_ = false;
     break_pc_ = nullptr;
     break_instr_ = 0;
 
     // Set up architecture state.
     // All registers are initialized to zero to start with.
     for (int i = 0; i < Register::kNumSimuRegisters; i++) {
         registers_[i] = 0;
     }
@@ -1619,16 +1621,28 @@ Simulator::has_bad_pc() const
 
 // Raw access to the PC register without the special adjustment when reading.
 int32_t
 Simulator::get_pc() const
 {
     return registers_[pc];
 }
 
+void
+Simulator::startInterrupt(WasmActivation* activation)
+{
+    MOZ_CRASH("NIY");
+}
+
+void
+Simulator::handleWasmInterrupt()
+{
+    MOZ_CRASH("NIY");
+}
+
 // The MIPS cannot do unaligned reads and writes.  On some MIPS platforms an
 // interrupt is caused.  On others it does a funky rotation thing.  For now we
 // simply disallow unaligned reads, but at some point we may want to move to
 // emulating the rotate behaviour.  Note that simulator runs have the runtime
 // system running directly on the host system and only generated code is
 // executed in the simulator.  Since the host is typically IA32 we will not
 // get the correct MIPS-like behaviour on unaligned accesses.
 
@@ -2588,16 +2602,17 @@ Simulator::decodeTypeRegister(SimInstruc
               case ff_cvt_d_fmt:
                 f = getFpuRegisterFloat(fs_reg);
                 setFpuRegisterDouble(fd_reg, static_cast<double>(f));
                 break;
               case ff_cvt_w_fmt:   // Convert float to word.
                 // Rounding modes are not yet supported.
                 MOZ_ASSERT((FCSR_ & 3) == 0);
                 // In rounding mode 0 it should behave like ROUND.
+                MOZ_FALLTHROUGH;
               case ff_round_w_fmt: { // Round double to word (round half to even).
                 float rounded = std::floor(fs_value + 0.5);
                 int32_t result = static_cast<int32_t>(rounded);
                 if ((result & 1) != 0 && result - fs_value == 0.5) {
                     // If the number is halfway between two integers,
                     // round to the even one.
                     result--;
                 }
@@ -2733,16 +2748,17 @@ Simulator::decodeTypeRegister(SimInstruc
                 dt_value = getFpuRegisterDouble(ft_reg);
                 setFCSRBit(fcsr_cc,
                             (ds_value <= dt_value) || (mozilla::IsNaN(ds_value) || mozilla::IsNaN(dt_value)));
                 break;
               case ff_cvt_w_fmt:   // Convert double to word.
                 // Rounding modes are not yet supported.
                 MOZ_ASSERT((FCSR_ & 3) == 0);
                 // In rounding mode 0 it should behave like ROUND.
+                MOZ_FALLTHROUGH;
               case ff_round_w_fmt: { // Round double to word (round half to even).
                 double rounded = std::floor(ds_value + 0.5);
                 int32_t result = static_cast<int32_t>(rounded);
                 if ((result & 1) != 0 && result - ds_value == 0.5) {
                     // If the number is halfway between two integers,
                     // round to the even one.
                     result--;
                 }
@@ -2984,17 +3000,17 @@ Simulator::decodeTypeRegister(SimInstruc
           case ff_ins:
             // Ins instr leaves result in Rt, rather than Rd.
             setRegister(rt_reg, alu_out);
             break;
           case ff_ext:
             // Ext instr leaves result in Rt, rather than Rd.
             setRegister(rt_reg, alu_out);
             break;
-          case ff_bshfl: 
+          case ff_bshfl:
             setRegister(rd_reg, alu_out);
             break;
           default:
             MOZ_CRASH();
         }
         break;
         // Unimplemented opcodes raised an error in the configuration step before,
         // so we can use the default here to set the destination register in common
@@ -3094,16 +3110,17 @@ Simulator::decodeTypeImmediate(SimInstru
             if (do_branch) {
                 next_pc = current_pc + (imm16 << 2) + SimInstruction::kInstrSize;
                 if (instr->isLinkingInstruction()) {
                     setRegister(31, current_pc + kBranchReturnOffset);
                 }
             } else {
                 next_pc = current_pc + kBranchReturnOffset;
             }
+            break;
           default:
             break;
         }
         break;  // case op_regimm.
         // ------------- Branch instructions.
         // When comparing to zero, the encoding of rt field is always 0, so we don't
         // need to replace rt with zero.
       case op_beq:
@@ -3397,33 +3414,29 @@ Simulator::branchDelayInstructionDecode(
 
 template<bool enableStopSimAt>
 void
 Simulator::execute()
 {
     // Get the PC to simulate. Cannot use the accessor here as we need the
     // raw PC value and not the one used as input to arithmetic instructions.
     int program_counter = get_pc();
-    WasmActivation* activation = TlsContext.get()->wasmActivationStack();
 
     while (program_counter != end_sim_pc) {
         if (enableStopSimAt && (icount_ == Simulator::StopSimAt)) {
             MipsDebugger dbg(this);
             dbg.debug();
         } else {
             SimInstruction* instr = reinterpret_cast<SimInstruction*>(program_counter);
             instructionDecode(instr);
             icount_++;
 
-            int32_t rpc = resume_pc_;
-            if (MOZ_UNLIKELY(rpc != 0)) {
-                // wasm signal handler ran and we have to adjust the pc.
-                activation->setResumePC((void*)get_pc());
-                set_pc(rpc);
-                resume_pc_ = 0;
+            if (MOZ_UNLIKELY(wasm_interrupt_)) {
+                handleWasmInterrupt();
+                wasm_interrupt_ = false;
             }
         }
         program_counter = get_pc();
     }
 }
 
 void
 Simulator::callInternal(uint8_t* entry)
--- a/js/src/jit/mips32/Simulator-mips32.h
+++ b/js/src/jit/mips32/Simulator-mips32.h
@@ -33,16 +33,19 @@
 
 #include "mozilla/Atomics.h"
 
 #include "jit/IonTypes.h"
 #include "threading/Thread.h"
 #include "vm/MutexIDs.h"
 
 namespace js {
+
+class WasmActivation;
+
 namespace jit {
 
 class Simulator;
 class Redirection;
 class CachePage;
 class AutoLockSimulator;
 
 const intptr_t kPointerAlignment = 4;
@@ -183,18 +186,21 @@ class Simulator {
 
     // Special case of set_register and get_register to access the raw PC value.
     void set_pc(int32_t value);
     int32_t get_pc() const;
 
     template <typename T>
     T get_pc_as() const { return reinterpret_cast<T>(get_pc()); }
 
-    void set_resume_pc(void* value) {
-        resume_pc_ = int32_t(value);
+    void trigger_wasm_interrupt() {
+        // This can be called several times if a single interrupt isn't caught
+        // and handled by the simulator, but this is fine; once the current
+        // instruction is done executing, the interrupt will be handled anyhow.
+        wasm_interrupt_ = true;
     }
 
     // Accessor to the internal simulator stack area.
     uintptr_t stackLimit() const;
     bool overRecursed(uintptr_t newsp = 0) const;
     bool overRecursedWithExtra(uint32_t extra) const;
 
     // Executes MIPS instructions until the PC reaches end_sim_pc.
@@ -279,25 +285,26 @@ class Simulator {
     void handleStop(uint32_t code, SimInstruction* instr);
     bool isStopInstruction(SimInstruction* instr);
     bool isEnabledStop(uint32_t code);
     void enableStop(uint32_t code);
     void disableStop(uint32_t code);
     void increaseStopCounter(uint32_t code);
     void printStopInfo(uint32_t code);
 
+    // Handle a wasm interrupt triggered by an async signal handler.
+    void handleWasmInterrupt();
+    void startInterrupt(WasmActivation* act);
 
     // Executes one instruction.
     void instructionDecode(SimInstruction* instr);
     // Execute one instruction placed in a branch delay slot.
     void branchDelayInstructionDecode(SimInstruction* instr);
 
   public:
-    static bool ICacheCheckingEnabled;
-
     static int StopSimAt;
 
     // Runtime call support.
     static void* RedirectNativeFunction(void* nativeFunction, ABIFunctionType type);
 
   private:
     enum Exception {
         kNone,
@@ -331,17 +338,18 @@ class Simulator {
 
     // Simulator support.
     char* stack_;
     uintptr_t stackLimit_;
     bool pc_modified_;
     int icount_;
     int break_count_;
 
-    int32_t resume_pc_;
+    // wasm async interrupt support
+    bool wasm_interrupt_;
 
     // Debugger input.
     char* lastDebuggerInput_;
 
     // Registered breakpoints.
     SimInstruction* break_pc_;
     Instr break_instr_;
 
--- a/js/src/shell/js.cpp
+++ b/js/src/shell/js.cpp
@@ -8050,17 +8050,17 @@ SetContextOptions(JSContext* cx, const O
     if (op.getBoolOption("arm-sim-icache-checks"))
         jit::SimulatorProcess::ICacheCheckingDisableCount = 0;
 
     int32_t stopAt = op.getIntOption("arm-sim-stop-at");
     if (stopAt >= 0)
         jit::Simulator::StopSimAt = stopAt;
 #elif defined(JS_SIMULATOR_MIPS32) || defined(JS_SIMULATOR_MIPS64)
     if (op.getBoolOption("mips-sim-icache-checks"))
-        jit::Simulator::ICacheCheckingEnabled = true;
+        jit::SimulatorProcess::ICacheCheckingDisableCount = 0;
 
     int32_t stopAt = op.getIntOption("mips-sim-stop-at");
     if (stopAt >= 0)
         jit::Simulator::StopSimAt = stopAt;
 #endif
 
     reportWarnings = op.getBoolOption('w');
     compileOnly = op.getBoolOption('c');