Bug 1396767 - MIPS: Fix MOVF in simulator. r=lth
authorMiran.Karic <Miran.Karic@imgtec.com>
Tue, 05 Sep 2017 03:16:00 -0400
changeset 378929 8bc120c1cd33
parent 378928 ef1033c0be43
child 378930 10a488d8110e
push id94548
push userryanvm@gmail.com
push dateTue, 05 Sep 2017 16:34:42 +0000
treeherdermozilla-inbound@10a488d8110e [default view] [failures only]
perfherder[talos] [build metrics] [platform microbench] (compared to previous push)
reviewerslth
bugs1396767
milestone57.0a1
first release with
nightly linux32
nightly linux64
nightly mac
nightly win32
nightly win64
last release without
nightly linux32
nightly linux64
nightly mac
nightly win32
nightly win64
Bug 1396767 - MIPS: Fix MOVF in simulator. r=lth When reading cc field for MOVF instruction, incorrect bits were accessed. This caused the test asm.js/testMathLib.js to fail.
js/src/jit/mips32/Simulator-mips32.cpp
js/src/jit/mips64/Simulator-mips64.cpp
--- a/js/src/jit/mips32/Simulator-mips32.cpp
+++ b/js/src/jit/mips32/Simulator-mips32.cpp
@@ -2813,16 +2813,19 @@ Simulator::decodeTypeRegister(SimInstruc
               case ff_trunc_l_fmt:
               case ff_floor_l_fmt:
               case ff_ceil_l_fmt:
               case ff_cvt_ps_s:
               case ff_c_f_fmt:
                 MOZ_CRASH();
                 break;
               case ff_movf_fmt:
+              // location of cc field in MOVF is equal to float branch instructions
+                cc = instr->fbccValue();
+                fcsr_cc = GetFCSRConditionBit(cc);
                 if (testFCSRBit(fcsr_cc)) {
                   setFpuRegisterFloat(fd_reg, getFpuRegisterFloat(fs_reg));
                 }
                 break;
               case ff_movz_fmt:
                 if (rt == 0) {
                   setFpuRegisterFloat(fd_reg, getFpuRegisterFloat(fs_reg));
                 }
@@ -2954,16 +2957,19 @@ Simulator::decodeTypeRegister(SimInstruc
               case ff_trunc_l_fmt:
               case ff_round_l_fmt:
               case ff_floor_l_fmt:
               case ff_ceil_l_fmt:
               case ff_c_f_fmt:
                 MOZ_CRASH();
                 break;
               case ff_movf_fmt:
+              // location of cc field in MOVF is equal to float branch instructions
+                cc = instr->fbccValue();
+                fcsr_cc = GetFCSRConditionBit(cc);
                 if (testFCSRBit(fcsr_cc)) {
                   setFpuRegisterDouble(fd_reg, getFpuRegisterDouble(fs_reg));
                 }
                 break;
               case ff_movz_fmt:
                 if (rt == 0) {
                   setFpuRegisterDouble(fd_reg, getFpuRegisterDouble(fs_reg));
                 }
--- a/js/src/jit/mips64/Simulator-mips64.cpp
+++ b/js/src/jit/mips64/Simulator-mips64.cpp
@@ -3036,16 +3036,19 @@ Simulator::decodeTypeRegister(SimInstruc
                 }
                 break;
               case ff_movn_fmt:
                 if (rt != 0) {
                   setFpuRegisterDouble(fd_reg, getFpuRegisterDouble(fs_reg));
                 }
                 break;
               case ff_movf_fmt:
+              // location of cc field in MOVF is equal to float branch instructions
+                cc = instr->fbccValue();
+                fcsr_cc = GetFCSRConditionBit(cc);
                 if (testFCSRBit(fcsr_cc)) {
                   setFpuRegisterDouble(fd_reg, getFpuRegisterDouble(fs_reg));
                 }
                 break;
               default:
                 MOZ_CRASH();
             }
             break;