Merge inbound to mozilla-central. a=merge
authorCiure Andrei <aciure@mozilla.com>
Sat, 22 Dec 2018 11:49:59 +0200
changeset 451815 0c5b666bed22df965e00de473ce8aff9544c50a7
parent 451814 4d03957994c13b57e6d325f59c004be995342636 (current diff)
parent 451804 1909ebb2e51fe6ba267f39eb6a9ce311fb40f821 (diff)
child 451816 ae14f16d9d015e982f3bf544b7cce5b32f211a5e
child 451828 6fc7ec309960d67a8d50a425fb5ff1d56106edef
child 451840 0124a534484d831c935794ac042be2737ef240ea
push id110733
push useraciure@mozilla.com
push dateSat, 22 Dec 2018 09:54:00 +0000
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perfherder[talos] [build metrics] [platform microbench] (compared to previous push)
reviewersmerge
milestone66.0a1
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Merge inbound to mozilla-central. a=merge
--- a/js/src/jit/arm64/MacroAssembler-arm64.h
+++ b/js/src/jit/arm64/MacroAssembler-arm64.h
@@ -953,37 +953,51 @@ class MacroAssemblerCompat : public vixl
   }
   void cmp32(Register lhs, Imm32 rhs) {
     Cmp(ARMRegister(lhs, 32), Operand(rhs.value));
   }
   void cmp32(Register a, Register b) {
     Cmp(ARMRegister(a, 32), Operand(ARMRegister(b, 32)));
   }
   void cmp32(const Address& lhs, Imm32 rhs) {
-    cmp32(Operand(lhs.base, lhs.offset), rhs);
+    vixl::UseScratchRegisterScope temps(this);
+    const ARMRegister scratch32 = temps.AcquireW();
+    MOZ_ASSERT(scratch32.asUnsized() != lhs.base);
+    Ldr(scratch32, toMemOperand(lhs));
+    Cmp(scratch32, Operand(rhs.value));
   }
   void cmp32(const Address& lhs, Register rhs) {
-    cmp32(Operand(lhs.base, lhs.offset), rhs);
+    vixl::UseScratchRegisterScope temps(this);
+    const ARMRegister scratch32 = temps.AcquireW();
+    MOZ_ASSERT(scratch32.asUnsized() != lhs.base);
+    MOZ_ASSERT(scratch32.asUnsized() != rhs);
+    Ldr(scratch32, toMemOperand(lhs));
+    Cmp(scratch32, Operand(ARMRegister(rhs, 32)));
   }
   void cmp32(Register lhs, const Address& rhs) {
-    cmp32(lhs, Operand(rhs.base, rhs.offset));
+    vixl::UseScratchRegisterScope temps(this);
+    const ARMRegister scratch32 = temps.AcquireW();
+    MOZ_ASSERT(scratch32.asUnsized() != rhs.base);
+    MOZ_ASSERT(scratch32.asUnsized() != lhs);
+    Ldr(scratch32, toMemOperand(rhs));
+    Cmp(scratch32, Operand(ARMRegister(lhs, 32)));
   }
-  void cmp32(const Operand& lhs, Imm32 rhs) {
+  void cmp32(const vixl::Operand& lhs, Imm32 rhs) {
     vixl::UseScratchRegisterScope temps(this);
     const ARMRegister scratch32 = temps.AcquireW();
     Mov(scratch32, lhs);
     Cmp(scratch32, Operand(rhs.value));
   }
-  void cmp32(const Operand& lhs, Register rhs) {
+  void cmp32(const vixl::Operand& lhs, Register rhs) {
     vixl::UseScratchRegisterScope temps(this);
     const ARMRegister scratch32 = temps.AcquireW();
     Mov(scratch32, lhs);
     Cmp(scratch32, Operand(ARMRegister(rhs, 32)));
   }
-  void cmp32(Register lhs, const Operand& rhs) {
+  void cmp32(Register lhs, const vixl::Operand& rhs) {
     vixl::UseScratchRegisterScope temps(this);
     const ARMRegister scratch32 = temps.AcquireW();
     Mov(scratch32, rhs);
     Cmp(scratch32, Operand(ARMRegister(lhs, 32)));
   }
 
   void cmpPtr(Register lhs, Imm32 rhs) {
     Cmp(ARMRegister(lhs, 64), Operand(rhs.value));
--- a/js/src/jit/arm64/vixl/Assembler-vixl.h
+++ b/js/src/jit/arm64/vixl/Assembler-vixl.h
@@ -697,32 +697,16 @@ class Operand {
           Shift shift = LSL,
           unsigned shift_amount = 0);   // NOLINT(runtime/explicit)
 
   // rm, {<extend> {#<shift_amount>}}
   // where <extend> is one of {UXTB, UXTH, UXTW, UXTX, SXTB, SXTH, SXTW, SXTX}.
   //       <shift_amount> is uint2_t.
   explicit Operand(Register reg, Extend extend, unsigned shift_amount = 0);
 
-  // FIXME: Temporary constructors for compilation.
-  // FIXME: These should be removed -- Operand should not leak into shared code.
-  // FIXME: Something like an LAllocationUnion for {gpreg, fpreg, Address} is wanted.
-  explicit Operand(js::jit::Register) {
-    MOZ_CRASH("Operand with Register");
-  }
-  explicit Operand(js::jit::FloatRegister) {
-    MOZ_CRASH("Operand with FloatRegister");
-  }
-  explicit Operand(js::jit::Register, int32_t) {
-    MOZ_CRASH("Operand with implicit Address");
-  }
-  explicit Operand(js::jit::RegisterOrSP, int32_t) {
-    MOZ_CRASH("Operand with implicit Address");
-  }
-
   bool IsImmediate() const;
   bool IsShiftedRegister() const;
   bool IsExtendedRegister() const;
   bool IsZero() const;
 
   // This returns an LSL shift (<= 4) operand as an equivalent extend operand,
   // which helps in the encoding of instructions that use the stack pointer.
   Operand ToExtendedRegister() const;