third_party/rust/cranelift-codegen-meta/src/isa/mod.rs
author Dan Gohman <sunfish@mozilla.com>
Tue, 27 Nov 2018 00:06:00 +0200
changeset 448222 3d330442ef3b3beddb0e71a95573e5cce49207dc
parent 445246 027bf8dee1e5bd49a0781a18e3b7d39051d70d6c
child 452567 9a4aab87dc85ec697a804bd0934bb8ae22908dcd
permissions -rw-r--r--
Bug 1507819 - Update to Cranelift 0.25. r=bbouvier

use cdsl::isa::TargetIsa;
use std::fmt;

mod arm32;
mod arm64;
mod riscv;
mod x86;

/// Represents known ISA target.
#[derive(Copy, Clone)]
pub enum Isa {
    Riscv,
    X86,
    Arm32,
    Arm64,
}

impl Isa {
    /// Creates isa target using name.
    pub fn new(name: &str) -> Option<Self> {
        Isa::all()
            .iter()
            .cloned()
            .filter(|isa| isa.to_string() == name)
            .next()
    }

    /// Creates isa target from arch.
    pub fn from_arch(arch: &str) -> Option<Isa> {
        Isa::all()
            .iter()
            .cloned()
            .filter(|isa| isa.is_arch_applicable(arch))
            .next()
    }

    /// Returns all supported isa targets.
    pub fn all() -> [Isa; 4] {
        [Isa::Riscv, Isa::X86, Isa::Arm32, Isa::Arm64]
    }

    /// Checks if arch is applicable for the isa target.
    fn is_arch_applicable(&self, arch: &str) -> bool {
        match *self {
            Isa::Riscv => arch == "riscv",
            Isa::X86 => ["x86_64", "i386", "i586", "i686"].contains(&arch),
            Isa::Arm32 => arch.starts_with("arm") || arch.starts_with("thumb"),
            Isa::Arm64 => arch == "aarch64",
        }
    }
}

impl fmt::Display for Isa {
    fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result {
        match *self {
            Isa::Riscv => write!(f, "riscv"),
            Isa::X86 => write!(f, "x86"),
            Isa::Arm32 => write!(f, "arm32"),
            Isa::Arm64 => write!(f, "arm64"),
        }
    }
}

pub fn define_all() -> Vec<TargetIsa> {
    vec![
        riscv::define(),
        arm32::define(),
        arm64::define(),
        x86::define(),
    ]
}