Bug 1111241 - SpiderMonkey: Make more assembler operand orderings consistent r=jandem
authorDan Gohman <sunfish@mozilla.com>
Mon, 15 Dec 2014 20:53:59 -0800
changeset 219887 c2a84c32dba0fcba7f897b026267fe055a175917
parent 219886 9638a136fbeebb1f8e4d1c41e37be22fe6e78aa4
child 219888 a8abb3321dc0469549094e328dcf03dc2ad61c4a
push id10419
push usercbook@mozilla.com
push dateTue, 16 Dec 2014 12:45:27 +0000
treeherderfx-team@ec87657146eb [default view] [failures only]
perfherder[talos] [build metrics] [platform microbench] (compared to previous push)
reviewersjandem
bugs1111241
milestone37.0a1
Bug 1111241 - SpiderMonkey: Make more assembler operand orderings consistent r=jandem
js/src/jit/shared/Assembler-x86-shared.h
js/src/jit/shared/BaseAssembler-x86-shared.h
js/src/jit/shared/CodeGenerator-x86-shared.cpp
js/src/jit/shared/MacroAssembler-x86-shared.cpp
js/src/jit/shared/MacroAssembler-x86-shared.h
js/src/jit/x64/Assembler-x64.h
js/src/jit/x64/BaselineIC-x64.cpp
js/src/jit/x64/CodeGenerator-x64.cpp
js/src/jit/x64/MacroAssembler-x64.cpp
js/src/jit/x64/MacroAssembler-x64.h
js/src/jit/x64/Trampoline-x64.cpp
js/src/jit/x86/Assembler-x86.h
js/src/jit/x86/BaselineIC-x86.cpp
js/src/jit/x86/CodeGenerator-x86.cpp
js/src/jit/x86/MacroAssembler-x86.cpp
js/src/jit/x86/MacroAssembler-x86.h
js/src/jit/x86/Trampoline-x86.cpp
--- a/js/src/jit/shared/Assembler-x86-shared.h
+++ b/js/src/jit/shared/Assembler-x86-shared.h
@@ -975,113 +975,95 @@ class AssemblerX86Shared : public Assemb
 
     static bool HasSSE2() { return CPUInfo::IsSSE2Present(); }
     static bool HasSSE3() { return CPUInfo::IsSSE3Present(); }
     static bool HasSSE41() { return CPUInfo::IsSSE41Present(); }
     static bool SupportsFloatingPoint() { return CPUInfo::IsSSE2Present(); }
     static bool SupportsSimd() { return CPUInfo::IsSSE2Present(); }
     static bool HasAVX() { return CPUInfo::IsAVXPresent(); }
 
-    // The below cmpl methods switch the lhs and rhs when it invokes the
-    // macroassembler to conform with intel standard.  When calling this
-    // function put the left operand on the left as you would expect.
-    void cmpl(Register lhs, Register rhs) {
+    void cmpl(Register rhs, Register lhs) {
         masm.cmpl_rr(rhs.code(), lhs.code());
     }
-    void cmpl(Register lhs, const Operand &rhs) {
+    void cmpl(const Operand &rhs, Register lhs) {
         switch (rhs.kind()) {
           case Operand::REG:
             masm.cmpl_rr(rhs.reg(), lhs.code());
             break;
           case Operand::MEM_REG_DISP:
             masm.cmpl_mr(rhs.disp(), rhs.base(), lhs.code());
             break;
-          default:
-            MOZ_CRASH("unexpected operand kind");
-        }
-    }
-    void cmpl(Register src, Imm32 imm) {
-        masm.cmpl_ir(imm.value, src.code());
-    }
-    void cmpl(const Operand &op, Imm32 imm) {
-        switch (op.kind()) {
-          case Operand::REG:
-            masm.cmpl_ir(imm.value, op.reg());
-            break;
-          case Operand::MEM_REG_DISP:
-            masm.cmpl_im(imm.value, op.disp(), op.base());
-            break;
-          case Operand::MEM_SCALE:
-            masm.cmpl_im(imm.value, op.disp(), op.base(), op.index(), op.scale());
-            break;
           case Operand::MEM_ADDRESS32:
-            masm.cmpl_im(imm.value, op.address());
+            masm.cmpl_mr(rhs.address(), lhs.code());
             break;
           default:
             MOZ_CRASH("unexpected operand kind");
         }
     }
-    void cmpl(const Operand &lhs, Register rhs) {
+    void cmpl(Register rhs, const Operand &lhs) {
         switch (lhs.kind()) {
           case Operand::REG:
             masm.cmpl_rr(rhs.code(), lhs.reg());
             break;
           case Operand::MEM_REG_DISP:
             masm.cmpl_rm(rhs.code(), lhs.disp(), lhs.base());
             break;
           case Operand::MEM_ADDRESS32:
             masm.cmpl_rm(rhs.code(), lhs.address());
             break;
           default:
             MOZ_CRASH("unexpected operand kind");
         }
     }
-    void cmpl(const Operand &op, ImmWord imm) {
-        switch (op.kind()) {
+    void cmpl(Imm32 rhs, Register lhs) {
+        masm.cmpl_ir(rhs.value, lhs.code());
+    }
+    void cmpl(Imm32 rhs, const Operand &lhs) {
+        switch (lhs.kind()) {
           case Operand::REG:
-            masm.cmpl_ir(imm.value, op.reg());
+            masm.cmpl_ir(rhs.value, lhs.reg());
             break;
           case Operand::MEM_REG_DISP:
-            masm.cmpl_im(imm.value, op.disp(), op.base());
+            masm.cmpl_im(rhs.value, lhs.disp(), lhs.base());
+            break;
+          case Operand::MEM_SCALE:
+            masm.cmpl_im(rhs.value, lhs.disp(), lhs.base(), lhs.index(), lhs.scale());
             break;
           case Operand::MEM_ADDRESS32:
-            masm.cmpl_im(imm.value, op.address());
+            masm.cmpl_im(rhs.value, lhs.address());
             break;
           default:
             MOZ_CRASH("unexpected operand kind");
         }
     }
-    void cmpl(const Operand &op, ImmPtr imm) {
-        cmpl(op, ImmWord(uintptr_t(imm.value)));
-    }
-    CodeOffsetLabel cmplWithPatch(Register lhs, Imm32 rhs) {
+    CodeOffsetLabel cmplWithPatch(Imm32 rhs, Register lhs) {
         masm.cmpl_i32r(rhs.value, lhs.code());
         return CodeOffsetLabel(masm.currentOffset());
     }
-    void cmpw(Register lhs, Register rhs) {
-        masm.cmpw_rr(lhs.code(), rhs.code());
+    void cmpw(Register rhs, Register lhs) {
+        masm.cmpw_rr(rhs.code(), lhs.code());
     }
     void setCC(Condition cond, Register r) {
         masm.setCC_r(static_cast<X86Assembler::Condition>(cond), r.code());
     }
-    void testb(Register lhs, Register rhs) {
+    void testb(Register rhs, Register lhs) {
+        MOZ_ASSERT(GeneralRegisterSet(Registers::SingleByteRegs).has(rhs));
         MOZ_ASSERT(GeneralRegisterSet(Registers::SingleByteRegs).has(lhs));
-        MOZ_ASSERT(GeneralRegisterSet(Registers::SingleByteRegs).has(rhs));
         masm.testb_rr(rhs.code(), lhs.code());
     }
-    void testw(Register lhs, Register rhs) {
-        masm.testw_rr(rhs.code(), lhs.code());
+    void testw(Register rhs, Register lhs) {
+        masm.testw_rr(lhs.code(), rhs.code());
     }
-    void testl(Register lhs, Register rhs) {
-        masm.testl_rr(rhs.code(), lhs.code());
+    void testl(Register rhs, Register lhs) {
+        masm.testl_rr(lhs.code(), rhs.code());
     }
-    void testl(Register lhs, Imm32 rhs) {
+    void testl(Imm32 rhs, Register lhs) {
         masm.testl_ir(rhs.value, lhs.code());
     }
-    void testl(const Operand &lhs, Imm32 rhs) {
+    void testl(Imm32 rhs, const Operand &lhs) {
         switch (lhs.kind()) {
           case Operand::REG:
             masm.testl_ir(rhs.value, lhs.reg());
             break;
           case Operand::MEM_REG_DISP:
             masm.testl_i32m(rhs.value, lhs.disp(), lhs.base());
             break;
           case Operand::MEM_ADDRESS32:
@@ -1644,29 +1626,29 @@ class AssemblerX86Shared : public Assemb
     void movmskpd(FloatRegister src, Register dest) {
         MOZ_ASSERT(HasSSE2());
         masm.movmskpd_rr(src.code(), dest.code());
     }
     void movmskps(FloatRegister src, Register dest) {
         MOZ_ASSERT(HasSSE2());
         masm.movmskps_rr(src.code(), dest.code());
     }
-    void ptest(FloatRegister lhs, FloatRegister rhs) {
+    void ptest(FloatRegister rhs, FloatRegister lhs) {
         MOZ_ASSERT(HasSSE41());
         masm.ptest_rr(rhs.code(), lhs.code());
     }
-    void ucomisd(FloatRegister lhs, FloatRegister rhs) {
+    void ucomisd(FloatRegister rhs, FloatRegister lhs) {
         MOZ_ASSERT(HasSSE2());
         masm.ucomisd_rr(rhs.code(), lhs.code());
     }
-    void ucomiss(FloatRegister lhs, FloatRegister rhs) {
+    void ucomiss(FloatRegister rhs, FloatRegister lhs) {
         MOZ_ASSERT(HasSSE2());
         masm.ucomiss_rr(rhs.code(), lhs.code());
     }
-    void pcmpeqw(FloatRegister lhs, FloatRegister rhs) {
+    void pcmpeqw(FloatRegister rhs, FloatRegister lhs) {
         MOZ_ASSERT(HasSSE2());
         masm.pcmpeqw_rr(rhs.code(), lhs.code());
     }
     void pcmpeqd(const Operand &src, FloatRegister dest) {
         MOZ_ASSERT(HasSSE2());
         switch (src.kind()) {
           case Operand::FPREG:
             masm.pcmpeqd_rr(src.fpu(), dest.code());
--- a/js/src/jit/shared/BaseAssembler-x86-shared.h
+++ b/js/src/jit/shared/BaseAssembler-x86-shared.h
@@ -1531,407 +1531,413 @@ public:
         spew("cmpxchg32  %s, %s0x%x(%s,%s,%d)",
              nameIReg(src), PRETTY_PRINT_OFFSET(offset), nameIReg(base), nameIReg(index), 1<<scale);
         m_formatter.twoByteOp(OP2_CMPXCHG_GvEw, offset, base, index, scale, src);
     }
 
 
     // Comparisons:
 
-    void cmpl_rr(RegisterID src, RegisterID dst)
-    {
-        spew("cmpl       %s, %s", nameIReg(4, src), nameIReg(4, dst));
-        m_formatter.oneByteOp(OP_CMP_GvEv, src, dst);
-    }
-
-    void cmpl_rm(RegisterID src, int offset, RegisterID base)
+    void cmpl_rr(RegisterID rhs, RegisterID lhs)
+    {
+        spew("cmpl       %s, %s", nameIReg(4, rhs), nameIReg(4, lhs));
+        m_formatter.oneByteOp(OP_CMP_GvEv, rhs, lhs);
+    }
+
+    void cmpl_rm(RegisterID rhs, int offset, RegisterID base)
     {
         spew("cmpl       %s, %s0x%x(%s)",
-             nameIReg(4, src), PRETTY_PRINT_OFFSET(offset), nameIReg(base));
-        m_formatter.oneByteOp(OP_CMP_EvGv, offset, base, src);
-    }
-
-    void cmpl_mr(int offset, RegisterID base, RegisterID src)
+             nameIReg(4, rhs), PRETTY_PRINT_OFFSET(offset), nameIReg(base));
+        m_formatter.oneByteOp(OP_CMP_EvGv, offset, base, rhs);
+    }
+
+    void cmpl_mr(int offset, RegisterID base, RegisterID lhs)
     {
         spew("cmpl       %s0x%x(%s), %s",
-             PRETTY_PRINT_OFFSET(offset), nameIReg(base), nameIReg(src));
-        m_formatter.oneByteOp(OP_CMP_GvEv, offset, base, src);
-    }
-
-    void cmpl_ir(int imm, RegisterID dst)
-    {
-        if (imm == 0) {
-            testl_rr(dst, dst);
+             PRETTY_PRINT_OFFSET(offset), nameIReg(base), nameIReg(4, lhs));
+        m_formatter.oneByteOp(OP_CMP_GvEv, offset, base, lhs);
+    }
+
+    void cmpl_mr(const void *address, RegisterID lhs)
+    {
+        spew("cmpl       %p, %s", address, nameIReg(4, lhs));
+        m_formatter.oneByteOp(OP_CMP_GvEv, address, lhs);
+    }
+
+    void cmpl_ir(int rhs, RegisterID lhs)
+    {
+        if (rhs == 0) {
+            testl_rr(lhs, lhs);
             return;
         }
 
-        spew("cmpl       $0x%x, %s", imm, nameIReg(4, dst));
-        if (CAN_SIGN_EXTEND_8_32(imm)) {
-            m_formatter.oneByteOp(OP_GROUP1_EvIb, dst, GROUP1_OP_CMP);
-            m_formatter.immediate8(imm);
+        spew("cmpl       $0x%x, %s", rhs, nameIReg(4, lhs));
+        if (CAN_SIGN_EXTEND_8_32(rhs)) {
+            m_formatter.oneByteOp(OP_GROUP1_EvIb, lhs, GROUP1_OP_CMP);
+            m_formatter.immediate8(rhs);
         } else {
-            m_formatter.oneByteOp(OP_GROUP1_EvIz, dst, GROUP1_OP_CMP);
-            m_formatter.immediate32(imm);
+            m_formatter.oneByteOp(OP_GROUP1_EvIz, lhs, GROUP1_OP_CMP);
+            m_formatter.immediate32(rhs);
         }
     }
 
-    void cmpl_i32r(int imm, RegisterID dst)
-    {
-        spew("cmpl       $0x%04x, %s", imm, nameIReg(4, dst));
-        m_formatter.oneByteOp(OP_GROUP1_EvIz, dst, GROUP1_OP_CMP);
-        m_formatter.immediate32(imm);
-    }
-
-    void cmpl_im(int imm, int offset, RegisterID base)
+    void cmpl_i32r(int rhs, RegisterID lhs)
+    {
+        spew("cmpl       $0x%04x, %s", rhs, nameIReg(4, lhs));
+        m_formatter.oneByteOp(OP_GROUP1_EvIz, lhs, GROUP1_OP_CMP);
+        m_formatter.immediate32(rhs);
+    }
+
+    void cmpl_im(int rhs, int offset, RegisterID base)
     {
         spew("cmpl       $0x%x, %s0x%x(%s)",
-             imm, PRETTY_PRINT_OFFSET(offset), nameIReg(base));
-        if (CAN_SIGN_EXTEND_8_32(imm)) {
+             rhs, PRETTY_PRINT_OFFSET(offset), nameIReg(base));
+        if (CAN_SIGN_EXTEND_8_32(rhs)) {
             m_formatter.oneByteOp(OP_GROUP1_EvIb, offset, base, GROUP1_OP_CMP);
-            m_formatter.immediate8(imm);
+            m_formatter.immediate8(rhs);
         } else {
             m_formatter.oneByteOp(OP_GROUP1_EvIz, offset, base, GROUP1_OP_CMP);
-            m_formatter.immediate32(imm);
+            m_formatter.immediate32(rhs);
         }
     }
 
-    void cmpb_im(int imm, int offset, RegisterID base)
+    void cmpb_im(int rhs, int offset, RegisterID base)
     {
         m_formatter.oneByteOp(OP_GROUP1_EbIb, offset, base, GROUP1_OP_CMP);
-        m_formatter.immediate8(imm);
-    }
-
-    void cmpb_im(int imm, int offset, RegisterID base, RegisterID index, int scale)
+        m_formatter.immediate8(rhs);
+    }
+
+    void cmpb_im(int rhs, int offset, RegisterID base, RegisterID index, int scale)
     {
         m_formatter.oneByteOp(OP_GROUP1_EbIb, offset, base, index, scale, GROUP1_OP_CMP);
-        m_formatter.immediate8(imm);
-    }
-
-    void cmpl_im(int imm, int offset, RegisterID base, RegisterID index, int scale)
+        m_formatter.immediate8(rhs);
+    }
+
+    void cmpl_im(int rhs, int offset, RegisterID base, RegisterID index, int scale)
     {
         spew("cmpl       $%d, %d(%s,%s,%d)",
-             imm, offset, nameIReg(base), nameIReg(index), 1<<scale);
-        if (CAN_SIGN_EXTEND_8_32(imm)) {
+             rhs, offset, nameIReg(base), nameIReg(index), 1<<scale);
+        if (CAN_SIGN_EXTEND_8_32(rhs)) {
             m_formatter.oneByteOp(OP_GROUP1_EvIb, offset, base, index, scale, GROUP1_OP_CMP);
-            m_formatter.immediate8(imm);
+            m_formatter.immediate8(rhs);
         } else {
             m_formatter.oneByteOp(OP_GROUP1_EvIz, offset, base, index, scale, GROUP1_OP_CMP);
-            m_formatter.immediate32(imm);
+            m_formatter.immediate32(rhs);
         }
     }
 
     MOZ_WARN_UNUSED_RESULT JmpSrc
-    cmpl_im_disp32(int imm, int offset, RegisterID base)
+    cmpl_im_disp32(int rhs, int offset, RegisterID base)
     {
         spew("cmpl       $0x%x, %s0x%04x(%s)",
-             imm, PRETTY_PRINT_OFFSET(offset), nameIReg(base));
+             rhs, PRETTY_PRINT_OFFSET(offset), nameIReg(base));
         JmpSrc r;
-        if (CAN_SIGN_EXTEND_8_32(imm)) {
+        if (CAN_SIGN_EXTEND_8_32(rhs)) {
             m_formatter.oneByteOp_disp32(OP_GROUP1_EvIb, offset, base, GROUP1_OP_CMP);
             r = JmpSrc(m_formatter.size());
-            m_formatter.immediate8(imm);
+            m_formatter.immediate8(rhs);
         } else {
             m_formatter.oneByteOp_disp32(OP_GROUP1_EvIz, offset, base, GROUP1_OP_CMP);
             r = JmpSrc(m_formatter.size());
-            m_formatter.immediate32(imm);
+            m_formatter.immediate32(rhs);
         }
         return r;
     }
 
     MOZ_WARN_UNUSED_RESULT JmpSrc
-    cmpl_im_disp32(int imm, const void *addr)
-    {
-        spew("cmpl       $0x%x, %p", imm, addr);
+    cmpl_im_disp32(int rhs, const void *addr)
+    {
+        spew("cmpl       $0x%x, %p", rhs, addr);
         JmpSrc r;
-        if (CAN_SIGN_EXTEND_8_32(imm)) {
+        if (CAN_SIGN_EXTEND_8_32(rhs)) {
             m_formatter.oneByteOp_disp32(OP_GROUP1_EvIb, addr, GROUP1_OP_CMP);
             r = JmpSrc(m_formatter.size());
-            m_formatter.immediate8(imm);
+            m_formatter.immediate8(rhs);
         } else {
             m_formatter.oneByteOp_disp32(OP_GROUP1_EvIz, addr, GROUP1_OP_CMP);
             r = JmpSrc(m_formatter.size());
-            m_formatter.immediate32(imm);
+            m_formatter.immediate32(rhs);
         }
         return r;
     }
 
-    void cmpl_i32m(int imm, int offset, RegisterID base)
+    void cmpl_i32m(int rhs, int offset, RegisterID base)
     {
         spew("cmpl       $0x%04x, %s0x%x(%s)",
-             imm, PRETTY_PRINT_OFFSET(offset), nameIReg(base));
+             rhs, PRETTY_PRINT_OFFSET(offset), nameIReg(base));
         m_formatter.oneByteOp(OP_GROUP1_EvIz, offset, base, GROUP1_OP_CMP);
-        m_formatter.immediate32(imm);
-    }
-
-    void cmpl_i32m(int imm, const void *addr)
-    {
-        spew("cmpl       $0x%04x, %p", imm, addr);
+        m_formatter.immediate32(rhs);
+    }
+
+    void cmpl_i32m(int rhs, const void *addr)
+    {
+        spew("cmpl       $0x%04x, %p", rhs, addr);
         m_formatter.oneByteOp(OP_GROUP1_EvIz, addr, GROUP1_OP_CMP);
-        m_formatter.immediate32(imm);
+        m_formatter.immediate32(rhs);
     }
 
 #ifdef JS_CODEGEN_X64
-    void cmpq_rr(RegisterID src, RegisterID dst)
-    {
-        spew("cmpq       %s, %s", nameIReg(8, src), nameIReg(8, dst));
-        m_formatter.oneByteOp64(OP_CMP_GvEv, src, dst);
-    }
-
-    void cmpq_rm(RegisterID src, int offset, RegisterID base)
-    {
-        spew("cmpq       %s, %d(%s)", nameIReg(8, src), offset, nameIReg(8, base));
-        m_formatter.oneByteOp64(OP_CMP_EvGv, offset, base, src);
-    }
-
-    void cmpq_mr(int offset, RegisterID base, RegisterID src)
-    {
-        spew("cmpq       %d(%s), %s", offset, nameIReg(8, base), nameIReg(8, src));
-        m_formatter.oneByteOp64(OP_CMP_GvEv, offset, base, src);
-    }
-
-    void cmpq_ir(int imm, RegisterID dst)
-    {
-        if (imm == 0) {
-            testq_rr(dst, dst);
+    void cmpq_rr(RegisterID rhs, RegisterID lhs)
+    {
+        spew("cmpq       %s, %s", nameIReg(8, rhs), nameIReg(8, lhs));
+        m_formatter.oneByteOp64(OP_CMP_GvEv, rhs, lhs);
+    }
+
+    void cmpq_rm(RegisterID rhs, int offset, RegisterID base)
+    {
+        spew("cmpq       %s, %d(%s)", nameIReg(8, rhs), offset, nameIReg(8, base));
+        m_formatter.oneByteOp64(OP_CMP_EvGv, offset, base, rhs);
+    }
+
+    void cmpq_mr(int offset, RegisterID base, RegisterID lhs)
+    {
+        spew("cmpq       %d(%s), %s", offset, nameIReg(8, base), nameIReg(8, lhs));
+        m_formatter.oneByteOp64(OP_CMP_GvEv, offset, base, lhs);
+    }
+
+    void cmpq_ir(int rhs, RegisterID lhs)
+    {
+        if (rhs == 0) {
+            testq_rr(lhs, lhs);
             return;
         }
 
-        spew("cmpq       $%d, %s", imm, nameIReg(8, dst));
-        if (CAN_SIGN_EXTEND_8_32(imm)) {
-            m_formatter.oneByteOp64(OP_GROUP1_EvIb, dst, GROUP1_OP_CMP);
-            m_formatter.immediate8(imm);
+        spew("cmpq       $%d, %s", rhs, nameIReg(8, lhs));
+        if (CAN_SIGN_EXTEND_8_32(rhs)) {
+            m_formatter.oneByteOp64(OP_GROUP1_EvIb, lhs, GROUP1_OP_CMP);
+            m_formatter.immediate8(rhs);
         } else {
-            m_formatter.oneByteOp64(OP_GROUP1_EvIz, dst, GROUP1_OP_CMP);
-            m_formatter.immediate32(imm);
+            m_formatter.oneByteOp64(OP_GROUP1_EvIz, lhs, GROUP1_OP_CMP);
+            m_formatter.immediate32(rhs);
         }
     }
 
-    void cmpq_im(int imm, int offset, RegisterID base)
+    void cmpq_im(int rhs, int offset, RegisterID base)
     {
         spew("cmpq       $%d, %s0x%x(%s)",
-             imm, PRETTY_PRINT_OFFSET(offset), nameIReg(base));
-        if (CAN_SIGN_EXTEND_8_32(imm)) {
+             rhs, PRETTY_PRINT_OFFSET(offset), nameIReg(base));
+        if (CAN_SIGN_EXTEND_8_32(rhs)) {
             m_formatter.oneByteOp64(OP_GROUP1_EvIb, offset, base, GROUP1_OP_CMP);
-            m_formatter.immediate8(imm);
+            m_formatter.immediate8(rhs);
         } else {
             m_formatter.oneByteOp64(OP_GROUP1_EvIz, offset, base, GROUP1_OP_CMP);
-            m_formatter.immediate32(imm);
+            m_formatter.immediate32(rhs);
         }
     }
 
-    void cmpq_im(int imm, int offset, RegisterID base, RegisterID index, int scale)
+    void cmpq_im(int rhs, int offset, RegisterID base, RegisterID index, int scale)
     {
         FIXME_INSN_PRINTING;
-        if (CAN_SIGN_EXTEND_8_32(imm)) {
+        if (CAN_SIGN_EXTEND_8_32(rhs)) {
             m_formatter.oneByteOp64(OP_GROUP1_EvIb, offset, base, index, scale, GROUP1_OP_CMP);
-            m_formatter.immediate8(imm);
+            m_formatter.immediate8(rhs);
         } else {
             m_formatter.oneByteOp64(OP_GROUP1_EvIz, offset, base, index, scale, GROUP1_OP_CMP);
-            m_formatter.immediate32(imm);
+            m_formatter.immediate32(rhs);
         }
     }
-    void cmpq_im(int imm, const void* addr)
-    {
-        spew("cmpq       $0x%x, %p", imm, addr);
-        if (CAN_SIGN_EXTEND_8_32(imm)) {
+    void cmpq_im(int rhs, const void* addr)
+    {
+        spew("cmpq       $0x%x, %p", rhs, addr);
+        if (CAN_SIGN_EXTEND_8_32(rhs)) {
             m_formatter.oneByteOp64(OP_GROUP1_EvIb, addr, GROUP1_OP_CMP);
-            m_formatter.immediate8(imm);
+            m_formatter.immediate8(rhs);
         } else {
             m_formatter.oneByteOp64(OP_GROUP1_EvIz, addr, GROUP1_OP_CMP);
-            m_formatter.immediate32(imm);
+            m_formatter.immediate32(rhs);
         }
     }
-    void cmpq_rm(RegisterID reg, const void* addr)
-    {
-        spew("cmpq       %s, %p", nameIReg(8, reg), addr);
-        m_formatter.oneByteOp64(OP_CMP_EvGv, addr, reg);
+    void cmpq_rm(RegisterID rhs, const void* addr)
+    {
+        spew("cmpq       %s, %p", nameIReg(8, rhs), addr);
+        m_formatter.oneByteOp64(OP_CMP_EvGv, addr, rhs);
     }
 #endif
-    void cmpl_rm(RegisterID reg, const void* addr)
-    {
-        spew("cmpl       %s, %p", nameIReg(4, reg), addr);
-        m_formatter.oneByteOp(OP_CMP_EvGv, addr, reg);
-    }
-
-    void cmpl_rm_disp32(RegisterID reg, const void* addr)
-    {
-        spew("cmpl       %s, %p", nameIReg(4, reg), addr);
-        m_formatter.oneByteOp_disp32(OP_CMP_EvGv, addr, reg);
-    }
-
-    void cmpl_im(int imm, const void* addr)
-    {
-        spew("cmpl       $0x%x, %p", imm, addr);
-        if (CAN_SIGN_EXTEND_8_32(imm)) {
+    void cmpl_rm(RegisterID rhs, const void* addr)
+    {
+        spew("cmpl       %s, %p", nameIReg(4, rhs), addr);
+        m_formatter.oneByteOp(OP_CMP_EvGv, addr, rhs);
+    }
+
+    void cmpl_rm_disp32(RegisterID rhs, const void* addr)
+    {
+        spew("cmpl       %s, %p", nameIReg(4, rhs), addr);
+        m_formatter.oneByteOp_disp32(OP_CMP_EvGv, addr, rhs);
+    }
+
+    void cmpl_im(int rhs, const void* addr)
+    {
+        spew("cmpl       $0x%x, %p", rhs, addr);
+        if (CAN_SIGN_EXTEND_8_32(rhs)) {
             m_formatter.oneByteOp(OP_GROUP1_EvIb, addr, GROUP1_OP_CMP);
-            m_formatter.immediate8(imm);
+            m_formatter.immediate8(rhs);
         } else {
             m_formatter.oneByteOp(OP_GROUP1_EvIz, addr, GROUP1_OP_CMP);
-            m_formatter.immediate32(imm);
+            m_formatter.immediate32(rhs);
         }
     }
 
-    void cmpw_rr(RegisterID src, RegisterID dst)
-    {
-        spew("cmpw       %s, %s", nameIReg(2, src), nameIReg(2, dst));
+    void cmpw_rr(RegisterID rhs, RegisterID lhs)
+    {
+        spew("cmpw       %s, %s", nameIReg(2, rhs), nameIReg(2, lhs));
         m_formatter.prefix(PRE_OPERAND_SIZE);
-        m_formatter.oneByteOp(OP_CMP_GvEv, src, dst);
-    }
-
-    void cmpw_rm(RegisterID src, int offset, RegisterID base, RegisterID index, int scale)
+        m_formatter.oneByteOp(OP_CMP_GvEv, rhs, lhs);
+    }
+
+    void cmpw_rm(RegisterID rhs, int offset, RegisterID base, RegisterID index, int scale)
     {
         FIXME_INSN_PRINTING;
         m_formatter.prefix(PRE_OPERAND_SIZE);
-        m_formatter.oneByteOp(OP_CMP_EvGv, offset, base, index, scale, src);
+        m_formatter.oneByteOp(OP_CMP_EvGv, offset, base, index, scale, rhs);
     }
 
     void cmpw_im(int imm, int offset, RegisterID base, RegisterID index, int scale)
     {
         FIXME_INSN_PRINTING;
         if (CAN_SIGN_EXTEND_8_32(imm)) {
             m_formatter.prefix(PRE_OPERAND_SIZE);
             m_formatter.oneByteOp(OP_GROUP1_EvIb, offset, base, index, scale, GROUP1_OP_CMP);
             m_formatter.immediate8(imm);
         } else {
             m_formatter.prefix(PRE_OPERAND_SIZE);
             m_formatter.oneByteOp(OP_GROUP1_EvIz, offset, base, index, scale, GROUP1_OP_CMP);
             m_formatter.immediate16(imm);
         }
     }
 
-    void testl_rr(RegisterID src, RegisterID dst)
-    {
-        spew("testl      %s, %s", nameIReg(4,src), nameIReg(4,dst));
-        m_formatter.oneByteOp(OP_TEST_EvGv, dst, src);
-    }
-
-    void testb_rr(RegisterID src, RegisterID dst)
-    {
-        spew("testb      %s, %s", nameIReg(1,src), nameIReg(1,dst));
-        m_formatter.oneByteOp(OP_TEST_EbGb, dst, src);
-    }
-
-    void testl_ir(int imm, RegisterID dst)
+    void testl_rr(RegisterID rhs, RegisterID lhs)
+    {
+        spew("testl      %s, %s", nameIReg(4, rhs), nameIReg(4, lhs));
+        m_formatter.oneByteOp(OP_TEST_EvGv, lhs, rhs);
+    }
+
+    void testb_rr(RegisterID rhs, RegisterID lhs)
+    {
+        spew("testb      %s, %s", nameIReg(1, rhs), nameIReg(1, lhs));
+        m_formatter.oneByteOp(OP_TEST_EbGb, lhs, rhs);
+    }
+
+    void testl_ir(int rhs, RegisterID lhs)
     {
         // If the mask fits in an 8-bit immediate, we can use testb with an
         // 8-bit subreg.
-        if (CAN_ZERO_EXTEND_8_32(imm) && X86Registers::hasSubregL(dst)) {
-            testb_i8r(imm, dst);
+        if (CAN_ZERO_EXTEND_8_32(rhs) && X86Registers::hasSubregL(lhs)) {
+            testb_i8r(rhs, lhs);
             return;
         }
         // If the mask is a subset of 0xff00, we can use testb with an h reg, if
         // one happens to be available.
-        if (CAN_ZERO_EXTEND_8H_32(imm) && X86Registers::hasSubregH(dst)) {
-            testb_i8r_norex(imm >> 8, X86Registers::getSubregH(dst));
+        if (CAN_ZERO_EXTEND_8H_32(rhs) && X86Registers::hasSubregH(lhs)) {
+            testb_i8r_norex(rhs >> 8, X86Registers::getSubregH(lhs));
             return;
         }
-        spew("testl      $0x%x, %s", imm, nameIReg(dst));
-        m_formatter.oneByteOp(OP_GROUP3_EvIz, dst, GROUP3_OP_TEST);
-        m_formatter.immediate32(imm);
-    }
-
-    void testl_i32m(int imm, int offset, RegisterID base)
+        spew("testl      $0x%x, %s", rhs, nameIReg(4, lhs));
+        m_formatter.oneByteOp(OP_GROUP3_EvIz, lhs, GROUP3_OP_TEST);
+        m_formatter.immediate32(rhs);
+    }
+
+    void testl_i32m(int rhs, int offset, RegisterID base)
     {
         spew("testl      $0x%x, %s0x%x(%s)",
-             imm, PRETTY_PRINT_OFFSET(offset), nameIReg(base));
+             rhs, PRETTY_PRINT_OFFSET(offset), nameIReg(base));
         m_formatter.oneByteOp(OP_GROUP3_EvIz, offset, base, GROUP3_OP_TEST);
-        m_formatter.immediate32(imm);
-    }
-
-    void testl_i32m(int imm, const void *addr)
-    {
-        spew("testl      $0x%x, %p", imm, addr);
+        m_formatter.immediate32(rhs);
+    }
+
+    void testl_i32m(int rhs, const void *addr)
+    {
+        spew("testl      $0x%x, %p", rhs, addr);
         m_formatter.oneByteOp(OP_GROUP3_EvIz, addr, GROUP3_OP_TEST);
-        m_formatter.immediate32(imm);
-    }
-
-    void testb_im(int imm, int offset, RegisterID base)
+        m_formatter.immediate32(rhs);
+    }
+
+    void testb_im(int rhs, int offset, RegisterID base)
     {
         FIXME_INSN_PRINTING;
         m_formatter.oneByteOp(OP_GROUP3_EbIb, offset, base, GROUP3_OP_TEST);
-        m_formatter.immediate8(imm);
-    }
-
-    void testb_im(int imm, int offset, RegisterID base, RegisterID index, int scale)
+        m_formatter.immediate8(rhs);
+    }
+
+    void testb_im(int rhs, int offset, RegisterID base, RegisterID index, int scale)
     {
         FIXME_INSN_PRINTING;
         m_formatter.oneByteOp(OP_GROUP3_EbIb, offset, base, index, scale, GROUP3_OP_TEST);
-        m_formatter.immediate8(imm);
-    }
-
-    void testl_i32m(int imm, int offset, RegisterID base, RegisterID index, int scale)
+        m_formatter.immediate8(rhs);
+    }
+
+    void testl_i32m(int rhs, int offset, RegisterID base, RegisterID index, int scale)
     {
         FIXME_INSN_PRINTING;
         m_formatter.oneByteOp(OP_GROUP3_EvIz, offset, base, index, scale, GROUP3_OP_TEST);
-        m_formatter.immediate32(imm);
+        m_formatter.immediate32(rhs);
     }
 
 #ifdef JS_CODEGEN_X64
-    void testq_rr(RegisterID src, RegisterID dst)
-    {
-        spew("testq      %s, %s", nameIReg(8,src), nameIReg(8,dst));
-        m_formatter.oneByteOp64(OP_TEST_EvGv, dst, src);
-    }
-
-    void testq_ir(int imm, RegisterID dst)
+    void testq_rr(RegisterID rhs, RegisterID lhs)
+    {
+        spew("testq      %s, %s", nameIReg(8, rhs), nameIReg(8, lhs));
+        m_formatter.oneByteOp64(OP_TEST_EvGv, lhs, rhs);
+    }
+
+    void testq_ir(int rhs, RegisterID lhs)
     {
         // If the mask fits in a 32-bit immediate, we can use testl with a
         // 32-bit subreg.
-        if (CAN_ZERO_EXTEND_32_64(imm)) {
-            testl_ir(imm, dst);
+        if (CAN_ZERO_EXTEND_32_64(rhs)) {
+            testl_ir(rhs, lhs);
             return;
         }
-        spew("testq      $0x%x, %s", imm, nameIReg(dst));
-        m_formatter.oneByteOp64(OP_GROUP3_EvIz, dst, GROUP3_OP_TEST);
-        m_formatter.immediate32(imm);
-    }
-
-    void testq_i32m(int imm, int offset, RegisterID base)
+        spew("testq      $0x%x, %s", rhs, nameIReg(8, lhs));
+        m_formatter.oneByteOp64(OP_GROUP3_EvIz, lhs, GROUP3_OP_TEST);
+        m_formatter.immediate32(rhs);
+    }
+
+    void testq_i32m(int rhs, int offset, RegisterID base)
     {
         spew("testq      $0x%x, %s0x%x(%s)",
-             imm, PRETTY_PRINT_OFFSET(offset), nameIReg(base));
+             rhs, PRETTY_PRINT_OFFSET(offset), nameIReg(base));
         m_formatter.oneByteOp64(OP_GROUP3_EvIz, offset, base, GROUP3_OP_TEST);
-        m_formatter.immediate32(imm);
-    }
-
-    void testq_i32m(int imm, int offset, RegisterID base, RegisterID index, int scale)
+        m_formatter.immediate32(rhs);
+    }
+
+    void testq_i32m(int rhs, int offset, RegisterID base, RegisterID index, int scale)
     {
         FIXME_INSN_PRINTING;
         m_formatter.oneByteOp64(OP_GROUP3_EvIz, offset, base, index, scale, GROUP3_OP_TEST);
-        m_formatter.immediate32(imm);
+        m_formatter.immediate32(rhs);
     }
 #endif
 
-    void testw_rr(RegisterID src, RegisterID dst)
+    void testw_rr(RegisterID rhs, RegisterID lhs)
     {
         FIXME_INSN_PRINTING;
         m_formatter.prefix(PRE_OPERAND_SIZE);
-        m_formatter.oneByteOp(OP_TEST_EvGv, dst, src);
-    }
-
-    void testb_i8r(int imm, RegisterID dst)
-    {
-        spew("testb      $0x%x, %s", imm, nameIReg(1,dst));
-        m_formatter.oneByteOp8(OP_GROUP3_EbIb, dst, GROUP3_OP_TEST);
-        m_formatter.immediate8(imm);
+        m_formatter.oneByteOp(OP_TEST_EvGv, lhs, rhs);
+    }
+
+    void testb_i8r(int rhs, RegisterID lhs)
+    {
+        spew("testb      $0x%x, %s", rhs, nameIReg(1, lhs));
+        m_formatter.oneByteOp8(OP_GROUP3_EbIb, lhs, GROUP3_OP_TEST);
+        m_formatter.immediate8(rhs);
     }
 
     // Like testb_i8r, but never emits a REX prefix. This may be used to
     // reference ah..bh.
-    void testb_i8r_norex(int imm, RegisterID dst)
-    {
-        spew("testb      $0x%x, %s", imm, nameIReg(1,dst));
-        m_formatter.oneByteOp8_norex(OP_GROUP3_EbIb, dst, GROUP3_OP_TEST);
-        m_formatter.immediate8(imm);
-    }
-
-    void setCC_r(Condition cond, RegisterID dst)
-    {
-        spew("set%s      %s", nameCC(cond), nameIReg(1,dst));
-        m_formatter.twoByteOp8(setccOpcode(cond), dst, (GroupOpcodeID)0);
+    void testb_i8r_norex(int rhs, RegisterID lhs)
+    {
+        spew("testb      $0x%x, %s", rhs, nameIReg(1, lhs));
+        m_formatter.oneByteOp8_norex(OP_GROUP3_EbIb, lhs, GROUP3_OP_TEST);
+        m_formatter.immediate8(rhs);
+    }
+
+    void setCC_r(Condition cond, RegisterID lhs)
+    {
+        spew("set%s      %s", nameCC(cond), nameIReg(1, lhs));
+        m_formatter.twoByteOp8(setccOpcode(cond), lhs, (GroupOpcodeID)0);
     }
 
     void sete_r(RegisterID dst)
     {
         setCC_r(ConditionE, dst);
     }
 
     void setz_r(RegisterID dst)
@@ -3195,19 +3201,19 @@ public:
 
     void movmskps_rr(XMMRegisterID src, RegisterID dst)
     {
         spew("movmskps   %s, %s", nameFPReg(src), nameIReg(dst));
         m_formatter.twoByteOp(OP2_MOVMSKPD_EdVd, (RegisterID)src, dst);
     }
 
     void ptest_rr(XMMRegisterID rhs, XMMRegisterID lhs) {
-        spew("ptest      %s, %s", nameFPReg(lhs), nameFPReg(rhs));
+        spew("ptest      %s, %s", nameFPReg(rhs), nameFPReg(lhs));
         m_formatter.prefix(PRE_SSE_66);
-        m_formatter.threeByteOp(OP3_PTEST_VdVd, ESCAPE_PTEST, (RegisterID)lhs, (RegisterID)rhs);
+        m_formatter.threeByteOp(OP3_PTEST_VdVd, ESCAPE_PTEST, (RegisterID)rhs, (RegisterID)lhs);
     }
 
     void movd_rr(XMMRegisterID src, RegisterID dst)
     {
         spew("movd       %s, %s", nameFPReg(src), nameIReg(dst));
         m_formatter.prefix(PRE_SSE_66);
         m_formatter.twoByteOp(OP2_MOVD_EdVd, dst, (RegisterID)src);
     }
@@ -3688,35 +3694,35 @@ public:
         twoByteOpSimd("vsubsd", VEX_SD, OP2_SUBSD_VsdWsd, offset, base, src0, dst);
     }
 
     void vsubss_mr(int offset, RegisterID base, XMMRegisterID src0, XMMRegisterID dst)
     {
         twoByteOpSimd("vsubss", VEX_SS, OP2_SUBSD_VsdWsd, offset, base, src0, dst);
     }
 
-    void ucomiss_rr(XMMRegisterID src, XMMRegisterID dst)
-    {
-        spew("ucomiss    %s, %s", nameFPReg(src), nameFPReg(dst));
-        m_formatter.twoByteOp(OP2_UCOMISD_VsdWsd, (RegisterID)src, (RegisterID)dst);
-    }
-
-    void ucomisd_rr(XMMRegisterID src, XMMRegisterID dst)
-    {
-        spew("ucomisd    %s, %s", nameFPReg(src), nameFPReg(dst));
+    void ucomiss_rr(XMMRegisterID rhs, XMMRegisterID lhs)
+    {
+        spew("ucomiss    %s, %s", nameFPReg(rhs), nameFPReg(lhs));
+        m_formatter.twoByteOp(OP2_UCOMISD_VsdWsd, (RegisterID)rhs, (RegisterID)lhs);
+    }
+
+    void ucomisd_rr(XMMRegisterID rhs, XMMRegisterID lhs)
+    {
+        spew("ucomisd    %s, %s", nameFPReg(rhs), nameFPReg(lhs));
         m_formatter.prefix(PRE_SSE_66);
-        m_formatter.twoByteOp(OP2_UCOMISD_VsdWsd, (RegisterID)src, (RegisterID)dst);
-    }
-
-    void ucomisd_mr(int offset, RegisterID base, XMMRegisterID dst)
+        m_formatter.twoByteOp(OP2_UCOMISD_VsdWsd, (RegisterID)rhs, (RegisterID)lhs);
+    }
+
+    void ucomisd_mr(int offset, RegisterID base, XMMRegisterID lhs)
     {
         spew("ucomisd    %s0x%x(%s), %s",
-             PRETTY_PRINT_OFFSET(offset), nameIReg(base), nameFPReg(dst));
+             PRETTY_PRINT_OFFSET(offset), nameIReg(base), nameFPReg(lhs));
         m_formatter.prefix(PRE_SSE_66);
-        m_formatter.twoByteOp(OP2_UCOMISD_VsdWsd, offset, base, (RegisterID)dst);
+        m_formatter.twoByteOp(OP2_UCOMISD_VsdWsd, offset, base, (RegisterID)lhs);
     }
 
     void vdivsd_rr(XMMRegisterID src1, XMMRegisterID src0, XMMRegisterID dst)
     {
         twoByteOpSimd("vdivsd", VEX_SD, OP2_DIVSD_VsdWsd, src1, src0, dst);
     }
 
     void vdivss_rr(XMMRegisterID src1, XMMRegisterID src0, XMMRegisterID dst)
--- a/js/src/jit/shared/CodeGenerator-x86-shared.cpp
+++ b/js/src/jit/shared/CodeGenerator-x86-shared.cpp
@@ -111,17 +111,17 @@ CodeGeneratorX86Shared::visitFloat32(LFl
 }
 
 void
 CodeGeneratorX86Shared::visitTestIAndBranch(LTestIAndBranch *test)
 {
     const LAllocation *opd = test->input();
 
     // Test the operand
-    masm.testl(ToRegister(opd), ToRegister(opd));
+    masm.test32(ToRegister(opd), ToRegister(opd));
     emitBranch(Assembler::NonZero, test->ifTrue(), test->ifFalse());
 }
 
 void
 CodeGeneratorX86Shared::visitTestDAndBranch(LTestDAndBranch *test)
 {
     const LAllocation *opd = test->input();
 
@@ -131,54 +131,54 @@ CodeGeneratorX86Shared::visitTestDAndBra
     //      NaN    1  1  1
     //        >    0  0  0
     //        <    0  0  1
     //        =    1  0  0
     //
     // NaN is falsey, so comparing against 0 and then using the Z flag is
     // enough to determine which branch to take.
     masm.zeroDouble(ScratchDoubleReg);
-    masm.ucomisd(ToFloatRegister(opd), ScratchDoubleReg);
+    masm.ucomisd(ScratchDoubleReg, ToFloatRegister(opd));
     emitBranch(Assembler::NotEqual, test->ifTrue(), test->ifFalse());
 }
 
 void
 CodeGeneratorX86Shared::visitTestFAndBranch(LTestFAndBranch *test)
 {
     const LAllocation *opd = test->input();
     // ucomiss flags are the same as doubles; see comment above
     masm.zeroFloat32(ScratchFloat32Reg);
-    masm.ucomiss(ToFloatRegister(opd), ScratchFloat32Reg);
+    masm.ucomiss(ScratchFloat32Reg, ToFloatRegister(opd));
     emitBranch(Assembler::NotEqual, test->ifTrue(), test->ifFalse());
 }
 
 void
 CodeGeneratorX86Shared::visitBitAndAndBranch(LBitAndAndBranch *baab)
 {
     if (baab->right()->isConstant())
-        masm.testl(ToRegister(baab->left()), Imm32(ToInt32(baab->right())));
+        masm.test32(ToRegister(baab->left()), Imm32(ToInt32(baab->right())));
     else
-        masm.testl(ToRegister(baab->left()), ToRegister(baab->right()));
+        masm.test32(ToRegister(baab->left()), ToRegister(baab->right()));
     emitBranch(Assembler::NonZero, baab->ifTrue(), baab->ifFalse());
 }
 
 void
 CodeGeneratorX86Shared::emitCompare(MCompare::CompareType type, const LAllocation *left, const LAllocation *right)
 {
 #ifdef JS_CODEGEN_X64
     if (type == MCompare::Compare_Object) {
-        masm.cmpq(ToRegister(left), ToOperand(right));
+        masm.cmpPtr(ToRegister(left), ToOperand(right));
         return;
     }
 #endif
 
     if (right->isConstant())
-        masm.cmpl(ToRegister(left), Imm32(ToInt32(right)));
+        masm.cmp32(ToRegister(left), Imm32(ToInt32(right)));
     else
-        masm.cmpl(ToRegister(left), ToOperand(right));
+        masm.cmp32(ToRegister(left), ToOperand(right));
 }
 
 void
 CodeGeneratorX86Shared::visitCompare(LCompare *comp)
 {
     MCompare *mir = comp->mir();
     emitCompare(mir->compareType(), comp->left(), comp->right());
     masm.emitSet(JSOpToCondition(mir->compareType(), comp->jsop()), ToRegister(comp->output()));
@@ -223,17 +223,17 @@ CodeGeneratorX86Shared::visitCompareF(LC
 
     masm.compareFloat(cond, lhs, rhs);
     masm.emitSet(Assembler::ConditionFromDoubleCondition(cond), ToRegister(comp->output()), nanCond);
 }
 
 void
 CodeGeneratorX86Shared::visitNotI(LNotI *ins)
 {
-    masm.cmpl(ToRegister(ins->input()), Imm32(0));
+    masm.cmp32(ToRegister(ins->input()), Imm32(0));
     masm.emitSet(Assembler::Equal, ToRegister(ins->output()));
 }
 
 void
 CodeGeneratorX86Shared::visitNotD(LNotD *ins)
 {
     FloatRegister opd = ToFloatRegister(ins->input());
 
@@ -492,17 +492,17 @@ CodeGeneratorX86Shared::visitMinMaxD(LMi
 
     Label done, nan, minMaxInst;
 
     // Do a ucomisd to catch equality and NaNs, which both require special
     // handling. If the operands are ordered and inequal, we branch straight to
     // the min/max instruction. If we wanted, we could also branch for less-than
     // or greater-than here instead of using min/max, however these conditions
     // will sometimes be hard on the branch predictor.
-    masm.ucomisd(first, second);
+    masm.ucomisd(second, first);
     masm.j(Assembler::NotEqual, &minMaxInst);
     if (!ins->mir()->range() || ins->mir()->range()->canBeNaN())
         masm.j(Assembler::Parity, &nan);
 
     // Ordered and equal. The operands are bit-identical unless they are zero
     // and negative zero. These instructions merge the sign bits in that
     // case, and are no-ops otherwise.
     if (ins->mir()->isMax())
@@ -543,17 +543,17 @@ CodeGeneratorX86Shared::visitMinMaxF(LMi
 
     Label done, nan, minMaxInst;
 
     // Do a ucomiss to catch equality and NaNs, which both require special
     // handling. If the operands are ordered and inequal, we branch straight to
     // the min/max instruction. If we wanted, we could also branch for less-than
     // or greater-than here instead of using min/max, however these conditions
     // will sometimes be hard on the branch predictor.
-    masm.ucomiss(first, second);
+    masm.ucomiss(second, first);
     masm.j(Assembler::NotEqual, &minMaxInst);
     if (!ins->mir()->range() || ins->mir()->range()->canBeNaN())
         masm.j(Assembler::Parity, &nan);
 
     // Ordered and equal. The operands are bit-identical unless they are zero
     // and negative zero. These instructions merge the sign bits in that
     // case, and are no-ops otherwise.
     if (ins->mir()->isMax())
@@ -608,17 +608,17 @@ void
 CodeGeneratorX86Shared::visitClzI(LClzI *ins)
 {
     Register input = ToRegister(ins->input());
     Register output = ToRegister(ins->output());
 
     // bsr is undefined on 0
     Label done, nonzero;
     if (!ins->mir()->operandIsNeverZero()) {
-        masm.testl(input, input);
+        masm.test32(input, input);
         masm.j(Assembler::NonZero, &nonzero);
         masm.move32(Imm32(32), output);
         masm.jump(&done);
     }
 
     masm.bind(&nonzero);
     masm.bsr(input, output);
     masm.xor32(Imm32(0x1F), output);
@@ -791,17 +791,17 @@ CodeGeneratorX86Shared::visitMulI(LMulI 
     MMul *mul = ins->mir();
     MOZ_ASSERT_IF(mul->mode() == MMul::Integer, !mul->canBeNegativeZero() && !mul->canOverflow());
 
     if (rhs->isConstant()) {
         // Bailout on -0.0
         int32_t constant = ToInt32(rhs);
         if (mul->canBeNegativeZero() && constant <= 0) {
             Assembler::Condition bailoutCond = (constant == 0) ? Assembler::Signed : Assembler::Equal;
-            masm.testl(ToRegister(lhs), ToRegister(lhs));
+            masm.test32(ToRegister(lhs), ToRegister(lhs));
             bailoutIf(bailoutCond, ins->snapshot());
         }
 
         switch (constant) {
           case -1:
             masm.negl(ToOperand(lhs));
             break;
           case 0:
@@ -835,17 +835,17 @@ CodeGeneratorX86Shared::visitMulI(LMulI 
         if (mul->canOverflow())
             bailoutIf(Assembler::Overflow, ins->snapshot());
 
         if (mul->canBeNegativeZero()) {
             // Jump to an OOL path if the result is 0.
             MulNegativeZeroCheck *ool = new(alloc()) MulNegativeZeroCheck(ins);
             addOutOfLineCode(ool, mul);
 
-            masm.testl(ToRegister(lhs), ToRegister(lhs));
+            masm.test32(ToRegister(lhs), ToRegister(lhs));
             masm.j(Assembler::Zero, ool->entry());
             masm.bind(ool->rejoin());
         }
     }
 }
 
 class ReturnZero : public OutOfLineCodeBase<CodeGeneratorX86Shared>
 {
@@ -885,41 +885,41 @@ CodeGeneratorX86Shared::visitUDivOrMod(L
     ReturnZero *ool = nullptr;
 
     // Put the lhs in eax.
     if (lhs != eax)
         masm.mov(lhs, eax);
 
     // Prevent divide by zero.
     if (ins->canBeDivideByZero()) {
-        masm.testl(rhs, rhs);
+        masm.test32(rhs, rhs);
         if (ins->mir()->isTruncated()) {
             if (!ool)
                 ool = new(alloc()) ReturnZero(output);
             masm.j(Assembler::Zero, ool->entry());
         } else {
             bailoutIf(Assembler::Zero, ins->snapshot());
         }
     }
 
     // Zero extend the lhs into edx to make (edx:eax), since udiv is 64-bit.
     masm.mov(ImmWord(0), edx);
     masm.udiv(rhs);
 
     // If the remainder is > 0, bailout since this must be a double.
     if (ins->mir()->isDiv() && !ins->mir()->toDiv()->canTruncateRemainder()) {
         Register remainder = ToRegister(ins->remainder());
-        masm.testl(remainder, remainder);
+        masm.test32(remainder, remainder);
         bailoutIf(Assembler::NonZero, ins->snapshot());
     }
 
     // Unsigned div or mod can return a value that's not a signed int32.
     // If our users aren't expecting that, bail.
     if (!ins->mir()->isTruncated()) {
-        masm.testl(output, output);
+        masm.test32(output, output);
         bailoutIf(Assembler::Signed, ins->snapshot());
     }
 
     if (ool) {
         addOutOfLineCode(ool, ins->mir());
         masm.bind(ool->rejoin());
     }
 }
@@ -953,24 +953,24 @@ CodeGeneratorX86Shared::visitDivPowTwoI(
     MDiv *mir = ins->mir();
 
     // We use defineReuseInput so these should always be the same, which is
     // convenient since all of our instructions here are two-address.
     MOZ_ASSERT(lhs == output);
 
     if (!mir->isTruncated() && negativeDivisor) {
         // 0 divided by a negative number must return a double.
-        masm.testl(lhs, lhs);
+        masm.test32(lhs, lhs);
         bailoutIf(Assembler::Zero, ins->snapshot());
     }
 
     if (shift != 0) {
         if (!mir->isTruncated()) {
             // If the remainder is != 0, bailout since this must be a double.
-            masm.testl(lhs, Imm32(UINT32_MAX >> (32 - shift)));
+            masm.test32(lhs, Imm32(UINT32_MAX >> (32 - shift)));
             bailoutIf(Assembler::NonZero, ins->snapshot());
         }
 
         // Adjust the value so that shifting produces a correctly rounded result
         // when the numerator is negative. See 10-1 "Signed Division by a Known
         // Power of 2" in Henry S. Warren, Jr.'s Hacker's Delight.
         if (mir->canBeNegativeDividend()) {
             Register lhsCopy = ToRegister(ins->numeratorCopy());
@@ -1039,34 +1039,34 @@ CodeGeneratorX86Shared::visitDivOrModCon
         masm.addl(lhs, eax);
     }
 
     if (!ins->mir()->isTruncated()) {
         if (isDiv) {
             // This is a division op. Multiply the obtained value by d to check if
             // the correct answer is an integer. This cannot overflow, since |d| > 1.
             masm.imull(Imm32(d), edx, eax);
-            masm.cmpl(lhs, eax);
+            masm.cmp32(lhs, eax);
             bailoutIf(Assembler::NotEqual, ins->snapshot());
 
             // If lhs is zero and the divisor is negative, the answer should have
             // been -0.
             if (d < 0) {
-                masm.testl(lhs, lhs);
+                masm.test32(lhs, lhs);
                 bailoutIf(Assembler::Zero, ins->snapshot());
             }
         } else if (ins->canBeNegativeDividend()) {
             // This is a mod op. If the computed value is zero and lhs
             // is negative, the answer should have been -0.
             Label done;
 
-            masm.cmpl(lhs, Imm32(0));
+            masm.cmp32(lhs, Imm32(0));
             masm.j(Assembler::GreaterThanOrEqual, &done);
 
-            masm.testl(eax, eax);
+            masm.test32(eax, eax);
             bailoutIf(Assembler::Zero, ins->snapshot());
 
             masm.bind(&done);
         }
     }
 }
 
 void
@@ -1089,64 +1089,64 @@ CodeGeneratorX86Shared::visitDivI(LDivI 
 
     // Put the lhs in eax, for either the negative overflow case or the regular
     // divide case.
     if (lhs != eax)
         masm.mov(lhs, eax);
 
     // Handle divide by zero.
     if (mir->canBeDivideByZero()) {
-        masm.testl(rhs, rhs);
+        masm.test32(rhs, rhs);
         if (mir->canTruncateInfinities()) {
             // Truncated division by zero is zero (Infinity|0 == 0)
             if (!ool)
                 ool = new(alloc()) ReturnZero(output);
             masm.j(Assembler::Zero, ool->entry());
         } else {
             MOZ_ASSERT(mir->fallible());
             bailoutIf(Assembler::Zero, ins->snapshot());
         }
     }
 
     // Handle an integer overflow exception from -2147483648 / -1.
     if (mir->canBeNegativeOverflow()) {
         Label notmin;
-        masm.cmpl(lhs, Imm32(INT32_MIN));
+        masm.cmp32(lhs, Imm32(INT32_MIN));
         masm.j(Assembler::NotEqual, &notmin);
-        masm.cmpl(rhs, Imm32(-1));
+        masm.cmp32(rhs, Imm32(-1));
         if (mir->canTruncateOverflow()) {
             // (-INT32_MIN)|0 == INT32_MIN and INT32_MIN is already in the
             // output register (lhs == eax).
             masm.j(Assembler::Equal, &done);
         } else {
             MOZ_ASSERT(mir->fallible());
             bailoutIf(Assembler::Equal, ins->snapshot());
         }
         masm.bind(&notmin);
     }
 
     // Handle negative 0.
     if (!mir->canTruncateNegativeZero() && mir->canBeNegativeZero()) {
         Label nonzero;
-        masm.testl(lhs, lhs);
+        masm.test32(lhs, lhs);
         masm.j(Assembler::NonZero, &nonzero);
-        masm.cmpl(rhs, Imm32(0));
+        masm.cmp32(rhs, Imm32(0));
         bailoutIf(Assembler::LessThan, ins->snapshot());
         masm.bind(&nonzero);
     }
 
     // Sign extend the lhs into edx to make (edx:eax), since idiv is 64-bit.
     if (lhs != eax)
         masm.mov(lhs, eax);
     masm.cdq();
     masm.idiv(rhs);
 
     if (!mir->canTruncateRemainder()) {
         // If the remainder is > 0, bailout since this must be a double.
-        masm.testl(remainder, remainder);
+        masm.test32(remainder, remainder);
         bailoutIf(Assembler::NonZero, ins->snapshot());
     }
 
     masm.bind(&done);
 
     if (ool) {
         addOutOfLineCode(ool, mir);
         masm.bind(ool->rejoin());
@@ -1217,17 +1217,17 @@ class ModOverflowCheck : public OutOfLin
     Register rhs() const {
         return rhs_;
     }
 };
 
 void
 CodeGeneratorX86Shared::visitModOverflowCheck(ModOverflowCheck *ool)
 {
-    masm.cmpl(ool->rhs(), Imm32(-1));
+    masm.cmp32(ool->rhs(), Imm32(-1));
     if (ool->ins()->mir()->isTruncated()) {
         masm.j(Assembler::NotEqual, ool->rejoin());
         masm.mov(ImmWord(0), edx);
         masm.jmp(ool->done());
     } else {
         bailoutIf(Assembler::Equal, ool->ins()->snapshot());
         masm.jmp(ool->rejoin());
     }
@@ -1251,17 +1251,17 @@ CodeGeneratorX86Shared::visitModI(LModI 
     ModOverflowCheck *overflow = nullptr;
 
     // Set up eax in preparation for doing a div.
     if (lhs != eax)
         masm.mov(lhs, eax);
 
     // Prevent divide by zero.
     if (ins->mir()->canBeDivideByZero()) {
-        masm.testl(rhs, rhs);
+        masm.test32(rhs, rhs);
         if (ins->mir()->isTruncated()) {
             if (!ool)
                 ool = new(alloc()) ReturnZero(edx);
             masm.j(Assembler::Zero, ool->entry());
         } else {
             bailoutIf(Assembler::Zero, ins->snapshot());
         }
     }
@@ -1303,26 +1303,26 @@ CodeGeneratorX86Shared::visitModI(LModI 
     // Otherwise, we have to beware of two special cases:
     if (ins->mir()->canBeNegativeDividend()) {
         masm.jump(&done);
 
         masm.bind(&negative);
 
         // Prevent an integer overflow exception from -2147483648 % -1
         Label notmin;
-        masm.cmpl(lhs, Imm32(INT32_MIN));
+        masm.cmp32(lhs, Imm32(INT32_MIN));
         overflow = new(alloc()) ModOverflowCheck(ins, rhs);
         masm.j(Assembler::Equal, overflow->entry());
         masm.bind(overflow->rejoin());
         masm.cdq();
         masm.idiv(rhs);
 
         if (!ins->mir()->isTruncated()) {
             // A remainder of 0 means that the rval must be -0, which is a double.
-            masm.testl(remainder, remainder);
+            masm.test32(remainder, remainder);
             bailoutIf(Assembler::Zero, ins->snapshot());
         }
     }
 
     masm.bind(&done);
 
     if (overflow) {
         addOutOfLineCode(overflow, ins->mir());
@@ -1391,17 +1391,17 @@ CodeGeneratorX86Shared::visitShiftI(LShi
             if (shift)
                 masm.sarl(Imm32(shift), lhs);
             break;
           case JSOP_URSH:
             if (shift) {
                 masm.shrl(Imm32(shift), lhs);
             } else if (ins->mir()->toUrsh()->fallible()) {
                 // x >>> 0 can overflow.
-                masm.testl(lhs, lhs);
+                masm.test32(lhs, lhs);
                 bailoutIf(Assembler::Signed, ins->snapshot());
             }
             break;
           default:
             MOZ_CRASH("Unexpected shift op");
         }
     } else {
         MOZ_ASSERT(ToRegister(rhs) == ecx);
@@ -1411,17 +1411,17 @@ CodeGeneratorX86Shared::visitShiftI(LShi
             break;
           case JSOP_RSH:
             masm.sarl_cl(lhs);
             break;
           case JSOP_URSH:
             masm.shrl_cl(lhs);
             if (ins->mir()->toUrsh()->fallible()) {
                 // x >>> 0 can overflow.
-                masm.testl(lhs, lhs);
+                masm.test32(lhs, lhs);
                 bailoutIf(Assembler::Signed, ins->snapshot());
             }
             break;
           default:
             MOZ_CRASH("Unexpected shift op");
         }
     }
 }
@@ -1509,17 +1509,17 @@ CodeGeneratorX86Shared::emitTableSwitchD
     Label *defaultcase = skipTrivialBlocks(mir->getDefault())->lir()->label();
 
     // Lower value with low value
     if (mir->low() != 0)
         masm.subl(Imm32(mir->low()), index);
 
     // Jump to default case if input is out of range
     int32_t cases = mir->numCases();
-    masm.cmpl(index, Imm32(cases));
+    masm.cmp32(index, Imm32(cases));
     masm.j(AssemblerX86Shared::AboveOrEqual, defaultcase);
 
     // To fill in the CodeLabels for the case entries, we need to first
     // generate the case entries (we don't yet know their offsets in the
     // instruction stream).
     OutOfLineTableSwitch *ool = new(alloc()) OutOfLineTableSwitch(mir);
     addOutOfLineCode(ool, mir);
 
@@ -1847,17 +1847,17 @@ CodeGeneratorX86Shared::visitRound(LRoun
         masm.addDouble(input, temp);
         masm.roundsd(X86Assembler::RoundDown, temp, scratch);
 
         // Truncate.
         bailoutCvttsd2si(scratch, output, lir->snapshot());
 
         // If the result is positive zero, then the actual result is -0. Bail.
         // Otherwise, the truncation will have produced the correct negative integer.
-        masm.testl(output, output);
+        masm.test32(output, output);
         bailoutIf(Assembler::Zero, lir->snapshot());
     } else {
         masm.addDouble(input, temp);
 
         // Round toward -Infinity without the benefit of ROUNDSD.
         {
             // If input + 0.5 >= 0, input is a negative number >= -0.5 and the result is -0.
             masm.compareDouble(Assembler::DoubleGreaterThanOrEqual, temp, scratch);
@@ -1930,17 +1930,17 @@ CodeGeneratorX86Shared::visitRoundF(LRou
         masm.addFloat32(input, temp);
         masm.roundss(X86Assembler::RoundDown, temp, scratch);
 
         // Truncate.
         bailoutCvttss2si(scratch, output, lir->snapshot());
 
         // If the result is positive zero, then the actual result is -0. Bail.
         // Otherwise, the truncation will have produced the correct negative integer.
-        masm.testl(output, output);
+        masm.test32(output, output);
         bailoutIf(Assembler::Zero, lir->snapshot());
     } else {
         masm.addFloat32(input, temp);
         // Round toward -Infinity without the benefit of ROUNDSS.
         {
             // If input + 0.5 >= 0, input is a negative number >= -0.5 and the result is -0.
             masm.compareFloat(Assembler::DoubleGreaterThanOrEqual, temp, scratch);
             bailoutIf(Assembler::DoubleGreaterThanOrEqual, lir->snapshot());
--- a/js/src/jit/shared/MacroAssembler-x86-shared.cpp
+++ b/js/src/jit/shared/MacroAssembler-x86-shared.cpp
@@ -227,22 +227,22 @@ MacroAssemblerX86Shared::branchNegativeZ
 
     // If reg is 1 or 3, input is negative zero.
     // If reg is 0 or 2, input is a normal zero.
     branchTest32(NonZero, scratch, Imm32(1), label);
 
     bind(&nonZero);
 #elif defined(JS_CODEGEN_X64)
     movq(reg, scratch);
-    cmpq(scratch, Imm32(1));
+    cmpq(Imm32(1), scratch);
     j(Overflow, label);
 #endif
 }
 
 void
 MacroAssemblerX86Shared::branchNegativeZeroFloat32(FloatRegister reg,
                                                    Register scratch,
                                                    Label *label)
 {
     movd(reg, scratch);
-    cmpl(scratch, Imm32(1));
+    cmp32(scratch, Imm32(1));
     j(Overflow, label);
 }
--- a/js/src/jit/shared/MacroAssembler-x86-shared.h
+++ b/js/src/jit/shared/MacroAssembler-x86-shared.h
@@ -33,19 +33,19 @@ class MacroAssemblerX86Shared : public A
     using Assembler::call;
 
     MacroAssemblerX86Shared()
       : framePushed_(0)
     { }
 
     void compareDouble(DoubleCondition cond, FloatRegister lhs, FloatRegister rhs) {
         if (cond & DoubleConditionBitInvert)
-            ucomisd(rhs, lhs);
+            ucomisd(lhs, rhs);
         else
-            ucomisd(lhs, rhs);
+            ucomisd(rhs, lhs);
     }
     void branchDouble(DoubleCondition cond, FloatRegister lhs, FloatRegister rhs, Label *label)
     {
         compareDouble(cond, lhs, rhs);
 
         if (cond == DoubleEqual) {
             Label unordered;
             j(Parity, &unordered);
@@ -60,19 +60,19 @@ class MacroAssemblerX86Shared : public A
         }
 
         MOZ_ASSERT(!(cond & DoubleConditionBitSpecial));
         j(ConditionFromDoubleCondition(cond), label);
     }
 
     void compareFloat(DoubleCondition cond, FloatRegister lhs, FloatRegister rhs) {
         if (cond & DoubleConditionBitInvert)
-            ucomiss(rhs, lhs);
+            ucomiss(lhs, rhs);
         else
-            ucomiss(lhs, rhs);
+            ucomiss(rhs, lhs);
     }
     void branchFloat(DoubleCondition cond, FloatRegister lhs, FloatRegister rhs, Label *label)
     {
         compareFloat(cond, lhs, rhs);
 
         if (cond == DoubleEqual) {
             Label unordered;
             j(Parity, &unordered);
@@ -128,51 +128,69 @@ class MacroAssemblerX86Shared : public A
     }
     void or32(Imm32 imm, const Address &dest) {
         orl(imm, Operand(dest));
     }
     void neg32(Register reg) {
         negl(reg);
     }
     void test32(Register lhs, Register rhs) {
-        testl(lhs, rhs);
+        testl(rhs, lhs);
     }
     void test32(const Address &addr, Imm32 imm) {
-        testl(Operand(addr), imm);
+        testl(imm, Operand(addr));
+    }
+    void test32(const Operand lhs, Imm32 imm) {
+        testl(imm, lhs);
     }
     void test32(Register lhs, Imm32 rhs) {
-        testl(lhs, rhs);
+        testl(rhs, lhs);
     }
     void cmp32(Register lhs, Imm32 rhs) {
-        cmpl(lhs, rhs);
+        cmpl(rhs, lhs);
     }
-    void cmp32(Register a, Register b) {
-        cmpl(a, b);
+    void cmp32(Register lhs, Register rhs) {
+        cmpl(rhs, lhs);
     }
     void cmp32(const Operand &lhs, Imm32 rhs) {
-        cmpl(lhs, rhs);
+        cmpl(rhs, lhs);
     }
     void cmp32(const Operand &lhs, Register rhs) {
-        cmpl(lhs, rhs);
+        cmpl(rhs, lhs);
+    }
+    void cmp32(Register lhs, const Operand &rhs) {
+        cmpl(rhs, lhs);
+    }
+    CodeOffsetLabel cmp32WithPatch(Register lhs, Imm32 rhs) {
+        return cmplWithPatch(rhs, lhs);
     }
     void add32(Register src, Register dest) {
         addl(src, dest);
     }
     void add32(Imm32 imm, Register dest) {
         addl(imm, dest);
     }
+    void add32(Imm32 imm, const Operand &dest) {
+        addl(imm, dest);
+    }
     void add32(Imm32 imm, const Address &dest) {
         addl(imm, Operand(dest));
     }
     void sub32(Imm32 imm, Register dest) {
         subl(imm, dest);
     }
+    void sub32(const Operand &src, Register dest) {
+        subl(src, dest);
+    }
     void sub32(Register src, Register dest) {
         subl(src, dest);
     }
+    void sub32(Register src, const Operand &dest) {
+        subl(src, dest);
+    }
     template <typename T>
     void branchAdd32(Condition cond, T src, Register dest, Label *label) {
         add32(src, dest);
         j(cond, label);
     }
     template <typename T>
     void branchSub32(Condition cond, T src, Register dest, Label *label) {
         sub32(src, dest);
@@ -478,68 +496,68 @@ class MacroAssemblerX86Shared : public A
         // This implementation follows Linux.
         if (HasSSE2())
             masm.mfence();
         else
             lock_addl(Imm32(0), Operand(Address(esp, 0)));
     }
 
     void branch16(Condition cond, Register lhs, Register rhs, Label *label) {
-        cmpw(lhs, rhs);
+        cmpw(rhs, lhs);
         j(cond, label);
     }
     void branch32(Condition cond, const Operand &lhs, Register rhs, Label *label) {
-        cmpl(lhs, rhs);
+        cmp32(lhs, rhs);
         j(cond, label);
     }
     void branch32(Condition cond, const Operand &lhs, Imm32 rhs, Label *label) {
-        cmpl(lhs, rhs);
+        cmp32(lhs, rhs);
         j(cond, label);
     }
     void branch32(Condition cond, const Address &lhs, Register rhs, Label *label) {
-        cmpl(Operand(lhs), rhs);
+        cmp32(Operand(lhs), rhs);
         j(cond, label);
     }
     void branch32(Condition cond, const Address &lhs, Imm32 imm, Label *label) {
-        cmpl(Operand(lhs), imm);
+        cmp32(Operand(lhs), imm);
         j(cond, label);
     }
     void branch32(Condition cond, const BaseIndex &lhs, Register rhs, Label *label) {
-        cmpl(Operand(lhs), rhs);
+        cmp32(Operand(lhs), rhs);
         j(cond, label);
     }
     void branch32(Condition cond, const BaseIndex &lhs, Imm32 imm, Label *label) {
-        cmpl(Operand(lhs), imm);
+        cmp32(Operand(lhs), imm);
         j(cond, label);
     }
     void branch32(Condition cond, Register lhs, Imm32 imm, Label *label) {
-        cmpl(lhs, imm);
+        cmp32(lhs, imm);
         j(cond, label);
     }
     void branch32(Condition cond, Register lhs, Register rhs, Label *label) {
-        cmpl(lhs, rhs);
+        cmp32(lhs, rhs);
         j(cond, label);
     }
     void branchTest16(Condition cond, Register lhs, Register rhs, Label *label) {
-        testw(lhs, rhs);
+        testw(rhs, lhs);
         j(cond, label);
     }
     void branchTest32(Condition cond, Register lhs, Register rhs, Label *label) {
         MOZ_ASSERT(cond == Zero || cond == NonZero || cond == Signed || cond == NotSigned);
-        testl(lhs, rhs);
+        test32(lhs, rhs);
         j(cond, label);
     }
     void branchTest32(Condition cond, Register lhs, Imm32 imm, Label *label) {
         MOZ_ASSERT(cond == Zero || cond == NonZero || cond == Signed || cond == NotSigned);
-        testl(lhs, imm);
+        test32(lhs, imm);
         j(cond, label);
     }
     void branchTest32(Condition cond, const Address &address, Imm32 imm, Label *label) {
         MOZ_ASSERT(cond == Zero || cond == NonZero || cond == Signed || cond == NotSigned);
-        testl(Operand(address), imm);
+        test32(Operand(address), imm);
         j(cond, label);
     }
 
     // The following functions are exposed for use in platform-shared code.
     template <typename T>
     void Push(const T &t) {
         push(t);
         framePushed_ += sizeof(intptr_t);
@@ -620,17 +638,17 @@ class MacroAssemblerX86Shared : public A
     }
     void convertInt32ToFloat32(const Operand &src, FloatRegister dest) {
         // Clear the output register first to break dependencies; see above;
         zeroFloat32(dest);
         cvtsi2ss(src, dest);
     }
     Condition testDoubleTruthy(bool truthy, FloatRegister reg) {
         zeroDouble(ScratchDoubleReg);
-        ucomisd(ScratchDoubleReg, reg);
+        ucomisd(reg, ScratchDoubleReg);
         return truthy ? NonZero : Zero;
     }
     void branchTestDoubleTruthy(bool truthy, FloatRegister reg, Label *label) {
         Condition cond = testDoubleTruthy(truthy, reg);
         j(cond, label);
     }
     void load8ZeroExtend(const Address &src, Register dest) {
         movzbl(Operand(src), dest);
@@ -1067,17 +1085,17 @@ class MacroAssemblerX86Shared : public A
                               bool negativeZeroCheck = true)
     {
         // Check for -0.0
         if (negativeZeroCheck)
             branchNegativeZero(src, dest, fail);
 
         cvttsd2si(src, dest);
         cvtsi2sd(dest, ScratchDoubleReg);
-        ucomisd(src, ScratchDoubleReg);
+        ucomisd(ScratchDoubleReg, src);
         j(Assembler::Parity, fail);
         j(Assembler::NotEqual, fail);
 
     }
 
     // Checks whether a float32 is representable as a 32-bit integer. If so, the
     // integer is written to the output register. Otherwise, a bailout is taken to
     // the given snapshot. This function overwrites the scratch float register.
@@ -1085,17 +1103,17 @@ class MacroAssemblerX86Shared : public A
                                bool negativeZeroCheck = true)
     {
         // Check for -0.0
         if (negativeZeroCheck)
             branchNegativeZeroFloat32(src, dest, fail);
 
         cvttss2si(src, dest);
         convertInt32ToFloat32(dest, ScratchFloat32Reg);
-        ucomiss(src, ScratchFloat32Reg);
+        ucomiss(ScratchFloat32Reg, src);
         j(Assembler::Parity, fail);
         j(Assembler::NotEqual, fail);
     }
 
     void clampIntToUint8(Register reg) {
         Label inRange;
         branchTest32(Assembler::Zero, reg, Imm32(0xffffff00), &inRange);
         {
--- a/js/src/jit/x64/Assembler-x64.h
+++ b/js/src/jit/x64/Assembler-x64.h
@@ -634,75 +634,72 @@ class Assembler : public AssemblerX86Sha
         CodeOffsetLabel label = loadRipRelativeInt64(dest);
         append(AsmJSGlobalAccess(label, AsmJSActivationGlobalDataOffset));
     }
     void loadAsmJSHeapRegisterFromGlobalData() {
         CodeOffsetLabel label = loadRipRelativeInt64(HeapReg);
         append(AsmJSGlobalAccess(label, AsmJSHeapGlobalDataOffset));
     }
 
-    // The below cmpq methods switch the lhs and rhs when it invokes the
-    // macroassembler to conform with intel standard.  When calling this
-    // function put the left operand on the left as you would expect.
-    void cmpq(const Operand &lhs, Register rhs) {
+    void cmpq(Register rhs, Register lhs) {
+        masm.cmpq_rr(rhs.code(), lhs.code());
+    }
+    void cmpq(Register rhs, const Operand &lhs) {
         switch (lhs.kind()) {
           case Operand::REG:
             masm.cmpq_rr(rhs.code(), lhs.reg());
             break;
           case Operand::MEM_REG_DISP:
             masm.cmpq_rm(rhs.code(), lhs.disp(), lhs.base());
             break;
           case Operand::MEM_ADDRESS32:
             masm.cmpq_rm(rhs.code(), lhs.address());
             break;
           default:
             MOZ_CRASH("unexpected operand kind");
         }
     }
-    void cmpq(const Operand &lhs, Imm32 rhs) {
+    void cmpq(Imm32 rhs, Register lhs) {
+        masm.cmpq_ir(rhs.value, lhs.code());
+    }
+    void cmpq(Imm32 rhs, const Operand &lhs) {
         switch (lhs.kind()) {
           case Operand::REG:
             masm.cmpq_ir(rhs.value, lhs.reg());
             break;
           case Operand::MEM_REG_DISP:
             masm.cmpq_im(rhs.value, lhs.disp(), lhs.base());
             break;
           case Operand::MEM_ADDRESS32:
             masm.cmpq_im(rhs.value, lhs.address());
             break;
           default:
             MOZ_CRASH("unexpected operand kind");
         }
     }
-    void cmpq(Register lhs, const Operand &rhs) {
+    void cmpq(const Operand &rhs, Register lhs) {
         switch (rhs.kind()) {
           case Operand::REG:
             masm.cmpq_rr(rhs.reg(), lhs.code());
             break;
           case Operand::MEM_REG_DISP:
             masm.cmpq_mr(rhs.disp(), rhs.base(), lhs.code());
             break;
           default:
             MOZ_CRASH("unexpected operand kind");
         }
     }
-    void cmpq(Register lhs, Register rhs) {
-        masm.cmpq_rr(rhs.code(), lhs.code());
-    }
-    void cmpq(Register lhs, Imm32 rhs) {
-        masm.cmpq_ir(rhs.value, lhs.code());
-    }
 
-    void testq(Register lhs, Imm32 rhs) {
+    void testq(Imm32 rhs, Register lhs) {
         masm.testq_ir(rhs.value, lhs.code());
     }
-    void testq(Register lhs, Register rhs) {
+    void testq(Register rhs, Register lhs) {
         masm.testq_rr(rhs.code(), lhs.code());
     }
-    void testq(const Operand &lhs, Imm32 rhs) {
+    void testq(Imm32 rhs, const Operand &lhs) {
         switch (lhs.kind()) {
           case Operand::REG:
             masm.testq_ir(rhs.value, lhs.reg());
             break;
           case Operand::MEM_REG_DISP:
             masm.testq_i32m(rhs.value, lhs.disp(), lhs.base());
             break;
           default:
--- a/js/src/jit/x64/BaselineIC-x64.cpp
+++ b/js/src/jit/x64/BaselineIC-x64.cpp
@@ -21,17 +21,17 @@ ICCompare_Int32::Compiler::generateStubC
     // Guard that R0 is an integer and R1 is an integer.
     Label failure;
     masm.branchTestInt32(Assembler::NotEqual, R0, &failure);
     masm.branchTestInt32(Assembler::NotEqual, R1, &failure);
 
     // Directly compare the int32 payload of R0 and R1.
     Assembler::Condition cond = JSOpToCondition(op, /* signed = */true);
     masm.mov(ImmWord(0), ScratchReg);
-    masm.cmpl(R0.valueReg(), R1.valueReg());
+    masm.cmp32(R0.valueReg(), R1.valueReg());
     masm.setCC(cond, ScratchReg);
 
     // Box the result and return
     masm.boxValue(JSVAL_TYPE_BOOLEAN, ScratchReg, R0.valueReg());
     EmitReturnFromIC(masm);
 
     // Failure case - jump to next stub
     masm.bind(&failure);
@@ -161,17 +161,17 @@ ICBinaryArith_Int32::Compiler::generateS
       case JSOP_URSH:
         if (!allowDouble_)
             masm.movq(R0.valueReg(), ScratchReg);
 
         masm.unboxInt32(R0, ExtractTemp0);
         masm.unboxInt32(R1, ecx); // This clobbers R0
 
         masm.shrl_cl(ExtractTemp0);
-        masm.testl(ExtractTemp0, ExtractTemp0);
+        masm.test32(ExtractTemp0, ExtractTemp0);
         if (allowDouble_) {
             Label toUint;
             masm.j(Assembler::Signed, &toUint);
 
             // Box and return.
             masm.boxValue(JSVAL_TYPE_INT32, ExtractTemp0, R0.valueReg());
             EmitReturnFromIC(masm);
 
--- a/js/src/jit/x64/CodeGenerator-x64.cpp
+++ b/js/src/jit/x64/CodeGenerator-x64.cpp
@@ -148,17 +148,17 @@ CodeGeneratorX64::visitCompareB(LCompare
 
     // Load boxed boolean in ScratchReg.
     if (rhs->isConstant())
         masm.moveValue(*rhs->toConstant(), ScratchReg);
     else
         masm.boxValue(JSVAL_TYPE_BOOLEAN, ToRegister(rhs), ScratchReg);
 
     // Perform the comparison.
-    masm.cmpq(lhs.valueReg(), ScratchReg);
+    masm.cmpPtr(lhs.valueReg(), ScratchReg);
     masm.emitSet(JSOpToCondition(mir->compareType(), mir->jsop()), output);
 }
 
 void
 CodeGeneratorX64::visitCompareBAndBranch(LCompareBAndBranch *lir)
 {
     MCompare *mir = lir->cmpMir();
 
@@ -169,46 +169,46 @@ CodeGeneratorX64::visitCompareBAndBranch
 
     // Load boxed boolean in ScratchReg.
     if (rhs->isConstant())
         masm.moveValue(*rhs->toConstant(), ScratchReg);
     else
         masm.boxValue(JSVAL_TYPE_BOOLEAN, ToRegister(rhs), ScratchReg);
 
     // Perform the comparison.
-    masm.cmpq(lhs.valueReg(), ScratchReg);
+    masm.cmpPtr(lhs.valueReg(), ScratchReg);
     emitBranch(JSOpToCondition(mir->compareType(), mir->jsop()), lir->ifTrue(), lir->ifFalse());
 }
 
 void
 CodeGeneratorX64::visitCompareV(LCompareV *lir)
 {
     MCompare *mir = lir->mir();
     const ValueOperand lhs = ToValue(lir, LCompareV::LhsInput);
     const ValueOperand rhs = ToValue(lir, LCompareV::RhsInput);
     const Register output = ToRegister(lir->output());
 
     MOZ_ASSERT(IsEqualityOp(mir->jsop()));
 
-    masm.cmpq(lhs.valueReg(), rhs.valueReg());
+    masm.cmpPtr(lhs.valueReg(), rhs.valueReg());
     masm.emitSet(JSOpToCondition(mir->compareType(), mir->jsop()), output);
 }
 
 void
 CodeGeneratorX64::visitCompareVAndBranch(LCompareVAndBranch *lir)
 {
     MCompare *mir = lir->cmpMir();
 
     const ValueOperand lhs = ToValue(lir, LCompareVAndBranch::LhsInput);
     const ValueOperand rhs = ToValue(lir, LCompareVAndBranch::RhsInput);
 
     MOZ_ASSERT(mir->jsop() == JSOP_EQ || mir->jsop() == JSOP_STRICTEQ ||
                mir->jsop() == JSOP_NE || mir->jsop() == JSOP_STRICTNE);
 
-    masm.cmpq(lhs.valueReg(), rhs.valueReg());
+    masm.cmpPtr(lhs.valueReg(), rhs.valueReg());
     emitBranch(JSOpToCondition(mir->compareType(), mir->jsop()), lir->ifTrue(), lir->ifFalse());
 }
 
 void
 CodeGeneratorX64::visitAsmJSUInt32ToDouble(LAsmJSUInt32ToDouble *lir)
 {
     masm.convertUInt32ToDouble(ToRegister(lir->input()), ToFloatRegister(lir->output()));
 }
@@ -273,17 +273,17 @@ CodeGeneratorX64::visitAsmJSLoadHeap(LAs
 
     memoryBarrier(ins->mir()->barrierBefore());
     OutOfLineLoadTypedArrayOutOfBounds *ool = nullptr;
     uint32_t maybeCmpOffset = AsmJSHeapAccess::NoLengthCheck;
     if (mir->needsBoundsCheck()) {
         ool = new(alloc()) OutOfLineLoadTypedArrayOutOfBounds(ToAnyRegister(out), vt);
         addOutOfLineCode(ool, ins->mir());
 
-        CodeOffsetLabel cmp = masm.cmplWithPatch(ToRegister(ptr), Imm32(0));
+        CodeOffsetLabel cmp = masm.cmp32WithPatch(ToRegister(ptr), Imm32(0));
         masm.j(Assembler::AboveOrEqual, ool->entry());
         maybeCmpOffset = cmp.offset();
     }
 
     uint32_t before = masm.size();
     switch (vt) {
       case Scalar::Int8:      masm.movsbl(srcAddr, ToRegister(out)); break;
       case Scalar::Uint8:     masm.movzbl(srcAddr, ToRegister(out)); break;
@@ -321,17 +321,17 @@ CodeGeneratorX64::visitAsmJSStoreHeap(LA
     } else {
         dstAddr = Operand(HeapReg, ToRegister(ptr), TimesOne);
     }
 
     memoryBarrier(ins->mir()->barrierBefore());
     Label rejoin;
     uint32_t maybeCmpOffset = AsmJSHeapAccess::NoLengthCheck;
     if (mir->needsBoundsCheck()) {
-        CodeOffsetLabel cmp = masm.cmplWithPatch(ToRegister(ptr), Imm32(0));
+        CodeOffsetLabel cmp = masm.cmp32WithPatch(ToRegister(ptr), Imm32(0));
         masm.j(Assembler::AboveOrEqual, &rejoin);
         maybeCmpOffset = cmp.offset();
     }
 
     uint32_t before = masm.size();
     if (ins->value()->isConstant()) {
         switch (vt) {
           case Scalar::Int8:
@@ -383,17 +383,17 @@ CodeGeneratorX64::visitAsmJSCompareExcha
     BaseIndex srcAddr(HeapReg, ToRegister(ptr), TimesOne);
 
     Register oldval = ToRegister(ins->oldValue());
     Register newval = ToRegister(ins->newValue());
 
     Label rejoin;
     uint32_t maybeCmpOffset = AsmJSHeapAccess::NoLengthCheck;
     if (mir->needsBoundsCheck()) {
-        maybeCmpOffset = masm.cmplWithPatch(ToRegister(ptr), Imm32(0)).offset();
+        maybeCmpOffset = masm.cmp32WithPatch(ToRegister(ptr), Imm32(0)).offset();
         Label goahead;
         masm.j(Assembler::Below, &goahead);
         memoryBarrier(MembarFull);
         Register out = ToRegister(ins->output());
         masm.xorl(out, out);
         masm.jmp(&rejoin);
         masm.bind(&goahead);
     }
@@ -420,17 +420,17 @@ CodeGeneratorX64::visitAsmJSAtomicBinopH
     AtomicOp op = mir->operation();
 
     MOZ_ASSERT(ptr->isRegister());
     BaseIndex srcAddr(HeapReg, ToRegister(ptr), TimesOne);
 
     Label rejoin;
     uint32_t maybeCmpOffset = AsmJSHeapAccess::NoLengthCheck;
     if (mir->needsBoundsCheck()) {
-        maybeCmpOffset = masm.cmplWithPatch(ToRegister(ptr), Imm32(0)).offset();
+        maybeCmpOffset = masm.cmp32WithPatch(ToRegister(ptr), Imm32(0)).offset();
         Label goahead;
         masm.j(Assembler::Below, &goahead);
         memoryBarrier(MembarFull);
         Register out = ToRegister(ins->output());
         masm.xorl(out,out);
         masm.jmp(&rejoin);
         masm.bind(&goahead);
     }
--- a/js/src/jit/x64/MacroAssembler-x64.cpp
+++ b/js/src/jit/x64/MacroAssembler-x64.cpp
@@ -288,17 +288,17 @@ MacroAssemblerX64::callWithABIPre(uint32
         MoveEmitter emitter(*this);
         emitter.emit(moveResolver_);
         emitter.finish();
     }
 
 #ifdef DEBUG
     {
         Label good;
-        testq(rsp, Imm32(ABIStackAlignment - 1));
+        testPtr(rsp, Imm32(ABIStackAlignment - 1));
         j(Equal, &good);
         breakpoint();
         bind(&good);
     }
 #endif
 }
 
 void
--- a/js/src/jit/x64/MacroAssembler-x64.h
+++ b/js/src/jit/x64/MacroAssembler-x64.h
@@ -266,76 +266,76 @@ class MacroAssemblerX64 : public MacroAs
         }
 #endif
         mov(ImmShiftedTag(tag), dest);
         orq(src, dest);
     }
 
     Condition testUndefined(Condition cond, Register tag) {
         MOZ_ASSERT(cond == Equal || cond == NotEqual);
-        cmpl(tag, ImmTag(JSVAL_TAG_UNDEFINED));
+        cmp32(tag, ImmTag(JSVAL_TAG_UNDEFINED));
         return cond;
     }
     Condition testInt32(Condition cond, Register tag) {
         MOZ_ASSERT(cond == Equal || cond == NotEqual);
-        cmpl(tag, ImmTag(JSVAL_TAG_INT32));
+        cmp32(tag, ImmTag(JSVAL_TAG_INT32));
         return cond;
     }
     Condition testBoolean(Condition cond, Register tag) {
         MOZ_ASSERT(cond == Equal || cond == NotEqual);
-        cmpl(tag, ImmTag(JSVAL_TAG_BOOLEAN));
+        cmp32(tag, ImmTag(JSVAL_TAG_BOOLEAN));
         return cond;
     }
     Condition testNull(Condition cond, Register tag) {
         MOZ_ASSERT(cond == Equal || cond == NotEqual);
-        cmpl(tag, ImmTag(JSVAL_TAG_NULL));
+        cmp32(tag, ImmTag(JSVAL_TAG_NULL));
         return cond;
     }
     Condition testString(Condition cond, Register tag) {
         MOZ_ASSERT(cond == Equal || cond == NotEqual);
-        cmpl(tag, ImmTag(JSVAL_TAG_STRING));
+        cmp32(tag, ImmTag(JSVAL_TAG_STRING));
         return cond;
     }
     Condition testSymbol(Condition cond, Register tag) {
         MOZ_ASSERT(cond == Equal || cond == NotEqual);
-        cmpl(tag, ImmTag(JSVAL_TAG_SYMBOL));
+        cmp32(tag, ImmTag(JSVAL_TAG_SYMBOL));
         return cond;
     }
     Condition testObject(Condition cond, Register tag) {
         MOZ_ASSERT(cond == Equal || cond == NotEqual);
-        cmpl(tag, ImmTag(JSVAL_TAG_OBJECT));
+        cmp32(tag, ImmTag(JSVAL_TAG_OBJECT));
         return cond;
     }
     Condition testDouble(Condition cond, Register tag) {
         MOZ_ASSERT(cond == Equal || cond == NotEqual);
-        cmpl(tag, Imm32(JSVAL_TAG_MAX_DOUBLE));
+        cmp32(tag, Imm32(JSVAL_TAG_MAX_DOUBLE));
         return cond == Equal ? BelowOrEqual : Above;
     }
     Condition testNumber(Condition cond, Register tag) {
         MOZ_ASSERT(cond == Equal || cond == NotEqual);
-        cmpl(tag, Imm32(JSVAL_UPPER_INCL_TAG_OF_NUMBER_SET));
+        cmp32(tag, Imm32(JSVAL_UPPER_INCL_TAG_OF_NUMBER_SET));
         return cond == Equal ? BelowOrEqual : Above;
     }
     Condition testGCThing(Condition cond, Register tag) {
         MOZ_ASSERT(cond == Equal || cond == NotEqual);
-        cmpl(tag, Imm32(JSVAL_LOWER_INCL_TAG_OF_GCTHING_SET));
+        cmp32(tag, Imm32(JSVAL_LOWER_INCL_TAG_OF_GCTHING_SET));
         return cond == Equal ? AboveOrEqual : Below;
     }
 
     Condition testMagic(Condition cond, Register tag) {
         MOZ_ASSERT(cond == Equal || cond == NotEqual);
-        cmpl(tag, ImmTag(JSVAL_TAG_MAGIC));
+        cmp32(tag, ImmTag(JSVAL_TAG_MAGIC));
         return cond;
     }
     Condition testError(Condition cond, Register tag) {
         return testMagic(cond, tag);
     }
     Condition testPrimitive(Condition cond, Register tag) {
         MOZ_ASSERT(cond == Equal || cond == NotEqual);
-        cmpl(tag, ImmTag(JSVAL_UPPER_EXCL_TAG_OF_PRIMITIVE_SET));
+        cmp32(tag, ImmTag(JSVAL_UPPER_EXCL_TAG_OF_PRIMITIVE_SET));
         return cond == Equal ? Below : AboveOrEqual;
     }
 
     Condition testUndefined(Condition cond, const ValueOperand &src) {
         splitTag(src, ScratchReg);
         return testUndefined(cond, ScratchReg);
     }
     Condition testInt32(Condition cond, const ValueOperand &src) {
@@ -475,75 +475,84 @@ class MacroAssemblerX64 : public MacroAs
         uint64_t magic = MagicValue(why).asRawBits();
         cmpPtr(src.valueReg(), ImmWord(magic));
         return cond;
     }
 
     void cmpPtr(Register lhs, const ImmWord rhs) {
         MOZ_ASSERT(lhs != ScratchReg);
         if (intptr_t(rhs.value) <= INT32_MAX && intptr_t(rhs.value) >= INT32_MIN) {
-            cmpq(lhs, Imm32(int32_t(rhs.value)));
+            cmpPtr(lhs, Imm32(int32_t(rhs.value)));
         } else {
-            movq(rhs, ScratchReg);
-            cmpq(lhs, ScratchReg);
+            movePtr(rhs, ScratchReg);
+            cmpPtr(lhs, ScratchReg);
         }
     }
     void cmpPtr(Register lhs, const ImmPtr rhs) {
         cmpPtr(lhs, ImmWord(uintptr_t(rhs.value)));
     }
     void cmpPtr(Register lhs, const ImmGCPtr rhs) {
         MOZ_ASSERT(lhs != ScratchReg);
-        movq(rhs, ScratchReg);
-        cmpq(lhs, ScratchReg);
+        movePtr(rhs, ScratchReg);
+        cmpPtr(lhs, ScratchReg);
     }
     void cmpPtr(Register lhs, const Imm32 rhs) {
-        cmpq(lhs, rhs);
+        cmpq(rhs, lhs);
     }
     void cmpPtr(const Operand &lhs, const ImmGCPtr rhs) {
         MOZ_ASSERT(!lhs.containsReg(ScratchReg));
-        movq(rhs, ScratchReg);
-        cmpq(lhs, ScratchReg);
+        movePtr(rhs, ScratchReg);
+        cmpPtr(lhs, ScratchReg);
     }
     void cmpPtr(const Operand &lhs, const ImmMaybeNurseryPtr rhs) {
         cmpPtr(lhs, noteMaybeNurseryPtr(rhs));
     }
     void cmpPtr(const Operand &lhs, const ImmWord rhs) {
         if ((intptr_t)rhs.value <= INT32_MAX && (intptr_t)rhs.value >= INT32_MIN) {
-            cmpq(lhs, Imm32((int32_t)rhs.value));
+            cmpPtr(lhs, Imm32((int32_t)rhs.value));
         } else {
-            mov(rhs, ScratchReg);
-            cmpq(lhs, ScratchReg);
+            movePtr(rhs, ScratchReg);
+            cmpPtr(lhs, ScratchReg);
         }
     }
     void cmpPtr(const Operand &lhs, const ImmPtr rhs) {
         cmpPtr(lhs, ImmWord(uintptr_t(rhs.value)));
     }
     void cmpPtr(const Address &lhs, const ImmGCPtr rhs) {
         cmpPtr(Operand(lhs), rhs);
     }
     void cmpPtr(const Address &lhs, const ImmWord rhs) {
         cmpPtr(Operand(lhs), rhs);
     }
     void cmpPtr(const Address &lhs, const ImmPtr rhs) {
         cmpPtr(lhs, ImmWord(uintptr_t(rhs.value)));
     }
     void cmpPtr(const Operand &lhs, Register rhs) {
-        cmpq(lhs, rhs);
+        cmpq(rhs, lhs);
+    }
+    void cmpPtr(Register lhs, const Operand &rhs) {
+        cmpq(rhs, lhs);
     }
     void cmpPtr(const Operand &lhs, const Imm32 rhs) {
-        cmpq(lhs, rhs);
+        cmpq(rhs, lhs);
     }
     void cmpPtr(const Address &lhs, Register rhs) {
         cmpPtr(Operand(lhs), rhs);
     }
     void cmpPtr(Register lhs, Register rhs) {
-        return cmpq(lhs, rhs);
+        cmpq(rhs, lhs);
     }
     void testPtr(Register lhs, Register rhs) {
-        testq(lhs, rhs);
+        testq(rhs, lhs);
+    }
+    void testPtr(Register lhs, Imm32 rhs) {
+        testq(rhs, lhs);
+    }
+    void testPtr(const Operand &lhs, Imm32 rhs) {
+        testq(rhs, lhs);
     }
 
     template <typename T1, typename T2>
     void cmpPtrSet(Assembler::Condition cond, T1 lhs, T2 rhs, Register dest)
     {
         cmpPtr(lhs, rhs);
         emitSet(cond, dest);
     }
@@ -638,20 +647,20 @@ class MacroAssemblerX64 : public MacroAs
             branch32(cond, Operand(lhs), rhs, label);
         } else {
             mov(ImmPtr(lhs.addr), ScratchReg);
             branch32(cond, Address(ScratchReg, 0), rhs, label);
         }
     }
     void branchTest32(Condition cond, AbsoluteAddress address, Imm32 imm, Label *label) {
         if (X86Assembler::isAddressImmediate(address.addr)) {
-            testl(Operand(address), imm);
+            test32(Operand(address), imm);
         } else {
             mov(ImmPtr(address.addr), ScratchReg);
-            testl(Operand(ScratchReg, 0), imm);
+            test32(Operand(ScratchReg, 0), imm);
         }
         j(cond, label);
     }
 
     // Specialization for AbsoluteAddress.
     void branchPtr(Condition cond, AbsoluteAddress addr, Register ptr, Label *label) {
         MOZ_ASSERT(ptr != ScratchReg);
         if (X86Assembler::isAddressImmediate(addr.addr)) {
@@ -711,25 +720,25 @@ class MacroAssemblerX64 : public MacroAs
         cmpPtr(lhs, ptr);
         return jumpWithPatch(label, cond);
     }
     void branchPtr(Condition cond, Register lhs, Register rhs, Label *label) {
         cmpPtr(lhs, rhs);
         j(cond, label);
     }
     void branchTestPtr(Condition cond, Register lhs, Register rhs, Label *label) {
-        testq(lhs, rhs);
+        testPtr(lhs, rhs);
         j(cond, label);
     }
     void branchTestPtr(Condition cond, Register lhs, Imm32 imm, Label *label) {
-        testq(lhs, imm);
+        testPtr(lhs, imm);
         j(cond, label);
     }
     void branchTestPtr(Condition cond, const Address &lhs, Imm32 imm, Label *label) {
-        testq(Operand(lhs), imm);
+        testPtr(Operand(lhs), imm);
         j(cond, label);
     }
     void decBranchPtr(Condition cond, Register lhs, Imm32 imm, Label *label) {
         subPtr(imm, lhs);
         j(cond, label);
     }
 
     void movePtr(Register src, Register dest) {
@@ -874,17 +883,17 @@ class MacroAssemblerX64 : public MacroAs
 
     // Extracts the tag of a value and places it in ScratchReg.
     Register splitTagForTest(const ValueOperand &value) {
         splitTag(value, ScratchReg);
         return ScratchReg;
     }
     void cmpTag(const ValueOperand &operand, ImmTag tag) {
         Register reg = splitTagForTest(operand);
-        cmpl(reg, tag);
+        cmp32(reg, tag);
     }
 
     void branchTestUndefined(Condition cond, Register tag, Label *label) {
         cond = testUndefined(cond, tag);
         j(cond, label);
     }
     void branchTestInt32(Condition cond, Register tag, Label *label) {
         cond = testInt32(cond, tag);
@@ -919,26 +928,26 @@ class MacroAssemblerX64 : public MacroAs
         j(cond, label);
     }
 
     // x64 can test for certain types directly from memory when the payload
     // of the type is limited to 32 bits. This avoids loading into a register,
     // accesses half as much memory, and removes a right-shift.
     void branchTestUndefined(Condition cond, const Operand &operand, Label *label) {
         MOZ_ASSERT(cond == Equal || cond == NotEqual);
-        cmpl(ToUpper32(operand), Imm32(Upper32Of(GetShiftedTag(JSVAL_TYPE_UNDEFINED))));
+        cmp32(ToUpper32(operand), Imm32(Upper32Of(GetShiftedTag(JSVAL_TYPE_UNDEFINED))));
         j(cond, label);
     }
     void branchTestUndefined(Condition cond, const Address &address, Label *label) {
         MOZ_ASSERT(cond == Equal || cond == NotEqual);
         branchTestUndefined(cond, Operand(address), label);
     }
     void branchTestInt32(Condition cond, const Operand &operand, Label *label) {
         MOZ_ASSERT(cond == Equal || cond == NotEqual);
-        cmpl(ToUpper32(operand), Imm32(Upper32Of(GetShiftedTag(JSVAL_TYPE_INT32))));
+        cmp32(ToUpper32(operand), Imm32(Upper32Of(GetShiftedTag(JSVAL_TYPE_INT32))));
         j(cond, label);
     }
     void branchTestInt32(Condition cond, const Address &address, Label *label) {
         MOZ_ASSERT(cond == Equal || cond == NotEqual);
         branchTestInt32(cond, Operand(address), label);
     }
     void branchTestDouble(Condition cond, const Operand &operand, Label *label) {
         MOZ_ASSERT(cond == Equal || cond == NotEqual);
@@ -946,22 +955,22 @@ class MacroAssemblerX64 : public MacroAs
         branchTestDouble(cond, ScratchReg, label);
     }
     void branchTestDouble(Condition cond, const Address &address, Label *label) {
         MOZ_ASSERT(cond == Equal || cond == NotEqual);
         branchTestDouble(cond, Operand(address), label);
     }
     void branchTestBoolean(Condition cond, const Operand &operand, Label *label) {
         MOZ_ASSERT(cond == Equal || cond == NotEqual);
-        cmpl(ToUpper32(operand), Imm32(Upper32Of(GetShiftedTag(JSVAL_TYPE_BOOLEAN))));
+        cmp32(ToUpper32(operand), Imm32(Upper32Of(GetShiftedTag(JSVAL_TYPE_BOOLEAN))));
         j(cond, label);
     }
     void branchTestNull(Condition cond, const Operand &operand, Label *label) {
         MOZ_ASSERT(cond == Equal || cond == NotEqual);
-        cmpl(ToUpper32(operand), Imm32(Upper32Of(GetShiftedTag(JSVAL_TYPE_NULL))));
+        cmp32(ToUpper32(operand), Imm32(Upper32Of(GetShiftedTag(JSVAL_TYPE_NULL))));
         j(cond, label);
     }
     void branchTestNull(Condition cond, const Address &address, Label *label) {
         MOZ_ASSERT(cond == Equal || cond == NotEqual);
         branchTestNull(cond, Operand(address), label);
     }
 
     // Perform a type-test on a full Value loaded into a register.
@@ -1064,17 +1073,17 @@ class MacroAssemblerX64 : public MacroAs
         return testMagic(cond, ScratchReg);
     }
     Condition testError(Condition cond, const ValueOperand &src) {
         return testMagic(cond, src);
     }
     void branchTestValue(Condition cond, const ValueOperand &value, const Value &v, Label *label) {
         MOZ_ASSERT(value.valueReg() != ScratchReg);
         moveValue(v, ScratchReg);
-        cmpq(value.valueReg(), ScratchReg);
+        cmpPtr(value.valueReg(), ScratchReg);
         j(cond, label);
     }
     void branchTestValue(Condition cond, const Address &valaddr, const ValueOperand &value,
                          Label *label)
     {
         MOZ_ASSERT(cond == Equal || cond == NotEqual);
         branchPtr(cond, valaddr, value.valueReg(), label);
     }
@@ -1269,46 +1278,46 @@ class MacroAssemblerX64 : public MacroAs
     void loadConstantFloat32x4(const SimdConstant &v, FloatRegister dest);
 
     void branchTruncateDouble(FloatRegister src, Register dest, Label *fail) {
         cvttsd2sq(src, dest);
 
         // cvttsd2sq returns 0x8000000000000000 on failure. Test for it by
         // subtracting 1 and testing overflow (this avoids the need to
         // materialize that value in a register).
-        cmpq(dest, Imm32(1));
+        cmpPtr(dest, Imm32(1));
         j(Assembler::Overflow, fail);
 
         movl(dest, dest); // Zero upper 32-bits.
     }
     void branchTruncateFloat32(FloatRegister src, Register dest, Label *fail) {
         cvttss2sq(src, dest);
 
         // Same trick as for Doubles
-        cmpq(dest, Imm32(1));
+        cmpPtr(dest, Imm32(1));
         j(Assembler::Overflow, fail);
 
         movl(dest, dest); // Zero upper 32-bits.
     }
 
     Condition testInt32Truthy(bool truthy, const ValueOperand &operand) {
-        testl(operand.valueReg(), operand.valueReg());
+        test32(operand.valueReg(), operand.valueReg());
         return truthy ? NonZero : Zero;
     }
     void branchTestInt32Truthy(bool truthy, const ValueOperand &operand, Label *label) {
         Condition cond = testInt32Truthy(truthy, operand);
         j(cond, label);
     }
     void branchTestBooleanTruthy(bool truthy, const ValueOperand &operand, Label *label) {
-        testl(operand.valueReg(), operand.valueReg());
+        test32(operand.valueReg(), operand.valueReg());
         j(truthy ? NonZero : Zero, label);
     }
     Condition testStringTruthy(bool truthy, const ValueOperand &value) {
         unboxString(value, ScratchReg);
-        cmpl(Operand(ScratchReg, JSString::offsetOfLength()), Imm32(0));
+        cmp32(Operand(ScratchReg, JSString::offsetOfLength()), Imm32(0));
         return truthy ? Assembler::NotEqual : Assembler::Equal;
     }
     void branchTestStringTruthy(bool truthy, const ValueOperand &value, Label *label) {
         Condition cond = testStringTruthy(truthy, value);
         j(cond, label);
     }
 
     void loadInt32OrDouble(const Operand &operand, FloatRegister dest) {
--- a/js/src/jit/x64/Trampoline-x64.cpp
+++ b/js/src/jit/x64/Trampoline-x64.cpp
@@ -112,17 +112,17 @@ JitRuntime::generateEnterJIT(JSContext *
     // r13 still stores the number of bytes in the argument vector.
     masm.addq(reg_argv, r13); // r13 points above last argument.
 
     // while r13 > rdx, push arguments.
     {
         Label header, footer;
         masm.bind(&header);
 
-        masm.cmpq(r13, reg_argv);
+        masm.cmpPtr(r13, reg_argv);
         masm.j(AssemblerX86Shared::BelowOrEqual, &footer);
 
         masm.subq(Imm32(8), r13);
         masm.push(Operand(r13, 0));
         masm.jmp(&header);
 
         masm.bind(&footer);
     }
--- a/js/src/jit/x86/Assembler-x86.h
+++ b/js/src/jit/x86/Assembler-x86.h
@@ -324,55 +324,55 @@ class Assembler : public AssemblerX86Sha
           case Operand::MEM_REG_DISP:
             masm.fstp32_m(src.disp(), src.base());
             break;
           default:
             MOZ_CRASH("unexpected operand kind");
         }
     }
 
-    void cmpl(const Register src, ImmWord ptr) {
-        masm.cmpl_ir(ptr.value, src.code());
+    void cmpl(ImmWord rhs, Register lhs) {
+        masm.cmpl_ir(rhs.value, lhs.code());
     }
-    void cmpl(const Register src, ImmPtr imm) {
-        cmpl(src, ImmWord(uintptr_t(imm.value)));
+    void cmpl(ImmPtr rhs, Register lhs) {
+        cmpl(ImmWord(uintptr_t(rhs.value)), lhs);
     }
-    void cmpl(const Register src, ImmGCPtr ptr) {
-        masm.cmpl_i32r(uintptr_t(ptr.value), src.code());
-        writeDataRelocation(ptr);
+    void cmpl(ImmGCPtr rhs, Register lhs) {
+        masm.cmpl_i32r(uintptr_t(rhs.value), lhs.code());
+        writeDataRelocation(rhs);
     }
-    void cmpl(Register lhs, Register rhs) {
+    void cmpl(Register rhs, Register lhs) {
         masm.cmpl_rr(rhs.code(), lhs.code());
     }
-    void cmpl(const Operand &op, ImmGCPtr imm) {
-        switch (op.kind()) {
+    void cmpl(ImmGCPtr rhs, const Operand &lhs) {
+        switch (lhs.kind()) {
           case Operand::REG:
-            masm.cmpl_i32r(uintptr_t(imm.value), op.reg());
-            writeDataRelocation(imm);
+            masm.cmpl_i32r(uintptr_t(rhs.value), lhs.reg());
+            writeDataRelocation(rhs);
             break;
           case Operand::MEM_REG_DISP:
-            masm.cmpl_i32m(uintptr_t(imm.value), op.disp(), op.base());
-            writeDataRelocation(imm);
+            masm.cmpl_i32m(uintptr_t(rhs.value), lhs.disp(), lhs.base());
+            writeDataRelocation(rhs);
             break;
           case Operand::MEM_ADDRESS32:
-            masm.cmpl_i32m(uintptr_t(imm.value), op.address());
-            writeDataRelocation(imm);
+            masm.cmpl_i32m(uintptr_t(rhs.value), lhs.address());
+            writeDataRelocation(rhs);
             break;
           default:
             MOZ_CRASH("unexpected operand kind");
         }
     }
-    void cmpl(const Operand &op, ImmMaybeNurseryPtr imm) {
-        cmpl(op, noteMaybeNurseryPtr(imm));
+    void cmpl(ImmMaybeNurseryPtr rhs, const Operand &lhs) {
+        cmpl(noteMaybeNurseryPtr(rhs), lhs);
     }
-    void cmpl(AsmJSAbsoluteAddress lhs, Register rhs) {
+    void cmpl(Register rhs, AsmJSAbsoluteAddress lhs) {
         masm.cmpl_rm_disp32(rhs.code(), (void*)-1);
         append(AsmJSAbsoluteLink(CodeOffsetLabel(masm.currentOffset()), lhs.kind()));
     }
-    void cmpl(AsmJSAbsoluteAddress lhs, Imm32 rhs) {
+    void cmpl(Imm32 rhs, AsmJSAbsoluteAddress lhs) {
         JmpSrc src = masm.cmpl_im_disp32(rhs.value, (void*)-1);
         append(AsmJSAbsoluteLink(CodeOffsetLabel(src.offset()), lhs.kind()));
     }
 
     void jmp(ImmPtr target, Relocation::Kind reloc = Relocation::HARDCODED) {
         JmpSrc src = masm.jmp();
         addPendingJump(src, target, reloc);
     }
--- a/js/src/jit/x86/BaselineIC-x86.cpp
+++ b/js/src/jit/x86/BaselineIC-x86.cpp
@@ -23,17 +23,17 @@ ICCompare_Int32::Compiler::generateStubC
 {
     // Guard that R0 is an integer and R1 is an integer.
     Label failure;
     masm.branchTestInt32(Assembler::NotEqual, R0, &failure);
     masm.branchTestInt32(Assembler::NotEqual, R1, &failure);
 
     // Compare payload regs of R0 and R1.
     Assembler::Condition cond = JSOpToCondition(op, /* signed = */true);
-    masm.cmpl(R0.payloadReg(), R1.payloadReg());
+    masm.cmp32(R0.payloadReg(), R1.payloadReg());
     masm.setCC(cond, R0.payloadReg());
     masm.movzbl(R0.payloadReg(), R0.payloadReg());
 
     // Box the result and return
     masm.tagValue(JSVAL_TYPE_BOOLEAN, R0.payloadReg(), R0);
     EmitReturnFromIC(masm);
 
     // Failure case - jump to next stub
@@ -76,17 +76,17 @@ ICBinaryArith_Int32::Compiler::generateS
         masm.j(Assembler::Overflow, &failure);
         masm.movl(scratchReg, R0.payloadReg());
         break;
       case JSOP_MUL:
         masm.movl(R0.payloadReg(), scratchReg);
         masm.imull(R1.payloadReg(), scratchReg);
         masm.j(Assembler::Overflow, &failure);
 
-        masm.testl(scratchReg, scratchReg);
+        masm.test32(scratchReg, scratchReg);
         masm.j(Assembler::Zero, &maybeNegZero);
 
         masm.movl(scratchReg, R0.payloadReg());
         break;
       case JSOP_DIV:
       {
         // Prevent division by 0.
         masm.branchTest32(Assembler::Zero, R1.payloadReg(), R1.payloadReg(), &failure);
@@ -168,17 +168,17 @@ ICBinaryArith_Int32::Compiler::generateS
         masm.tagValue(JSVAL_TYPE_INT32, R0.payloadReg(), R0);
         break;
       case JSOP_URSH:
         if (!allowDouble_)
             masm.movl(R0.payloadReg(), scratchReg);
 
         masm.movl(R1.payloadReg(), ecx);
         masm.shrl_cl(R0.payloadReg());
-        masm.testl(R0.payloadReg(), R0.payloadReg());
+        masm.test32(R0.payloadReg(), R0.payloadReg());
         if (allowDouble_) {
             Label toUint;
             masm.j(Assembler::Signed, &toUint);
 
             // Box and return.
             masm.tagValue(JSVAL_TYPE_INT32, R0.payloadReg(), R0);
             EmitReturnFromIC(masm);
 
--- a/js/src/jit/x86/CodeGenerator-x86.cpp
+++ b/js/src/jit/x86/CodeGenerator-x86.cpp
@@ -122,17 +122,17 @@ CodeGeneratorX86::visitBoxFloatingPoint(
 void
 CodeGeneratorX86::visitUnbox(LUnbox *unbox)
 {
     // Note that for unbox, the type and payload indexes are switched on the
     // inputs.
     MUnbox *mir = unbox->mir();
 
     if (mir->fallible()) {
-        masm.cmpl(ToOperand(unbox->type()), Imm32(MIRTypeToTag(mir->type())));
+        masm.cmp32(ToOperand(unbox->type()), Imm32(MIRTypeToTag(mir->type())));
         bailoutIf(Assembler::NotEqual, unbox->snapshot());
     }
 }
 
 void
 CodeGeneratorX86::visitCompareB(LCompareB *lir)
 {
     MCompare *mir = lir->mir();
@@ -298,17 +298,17 @@ CodeGeneratorX86::visitLoadTypedArrayEle
 
     if (mir->needsBoundsCheck()) {
         MOZ_ASSERT(offset == 0);
         if (!mir->fallible()) {
             ool = new(alloc()) OutOfLineLoadTypedArrayOutOfBounds(ToAnyRegister(out), vt);
             addOutOfLineCode(ool, ins->mir());
         }
 
-        masm.cmpl(ptr, Imm32(mir->length()));
+        masm.cmpPtr(ptr, ImmWord(mir->length()));
         if (ool)
             masm.j(Assembler::AboveOrEqual, ool->entry());
         else
             bailoutIf(Assembler::AboveOrEqual, ins->snapshot());
     }
 
     Address srcAddr(ptr, int32_t(mir->base()) + int32_t(offset));
     load(vt, srcAddr, out);
@@ -380,17 +380,17 @@ CodeGeneratorX86::visitAsmJSLoadHeap(LAs
         loadAndNoteViewTypeElement(vt, srcAddr, out);
         memoryBarrier(ins->mir()->barrierAfter());
         return;
     }
 
     OutOfLineLoadTypedArrayOutOfBounds *ool = new(alloc()) OutOfLineLoadTypedArrayOutOfBounds(ToAnyRegister(out), vt);
     addOutOfLineCode(ool, mir);
 
-    CodeOffsetLabel cmp = masm.cmplWithPatch(ptrReg, Imm32(0));
+    CodeOffsetLabel cmp = masm.cmp32WithPatch(ptrReg, Imm32(0));
     masm.j(Assembler::AboveOrEqual, ool->entry());
 
     uint32_t before = masm.size();
     load(vt, srcAddr, out);
     uint32_t after = masm.size();
     masm.bind(ool->rejoin());
     memoryBarrier(ins->mir()->barrierAfter());
     masm.append(AsmJSHeapAccess(before, after, vt, ToAnyRegister(out), cmp.offset()));
@@ -438,17 +438,17 @@ CodeGeneratorX86::visitStoreTypedArrayEl
 
     if (!mir->needsBoundsCheck()) {
         Address dstAddr(ptr, int32_t(mir->base()) + int32_t(offset));
         store(vt, value, dstAddr);
         return;
     }
 
     MOZ_ASSERT(offset == 0);
-    masm.cmpl(ptr, Imm32(mir->length()));
+    masm.cmpPtr(ptr, ImmWord(mir->length()));
     Label rejoin;
     masm.j(Assembler::AboveOrEqual, &rejoin);
 
     Address dstAddr(ptr, (int32_t) mir->base());
     store(vt, value, dstAddr);
     masm.bind(&rejoin);
 }
 
@@ -477,17 +477,17 @@ CodeGeneratorX86::visitAsmJSStoreHeap(LA
     Address dstAddr(ptrReg, 0);
 
     if (!mir->needsBoundsCheck()) {
         storeAndNoteViewTypeElement(vt, value, dstAddr);
         memoryBarrier(ins->mir()->barrierAfter());
         return;
     }
 
-    CodeOffsetLabel cmp = masm.cmplWithPatch(ptrReg, Imm32(0));
+    CodeOffsetLabel cmp = masm.cmp32WithPatch(ptrReg, Imm32(0));
     Label rejoin;
     masm.j(Assembler::AboveOrEqual, &rejoin);
 
     uint32_t before = masm.size();
     store(vt, value, dstAddr);
     uint32_t after = masm.size();
     masm.bind(&rejoin);
     memoryBarrier(ins->mir()->barrierAfter());
@@ -506,17 +506,17 @@ CodeGeneratorX86::visitAsmJSCompareExcha
     MOZ_ASSERT(ptr->isRegister());
     // Set up the offset within the heap in the pointer reg.
     Register ptrReg = ToRegister(ptr);
 
     Label rejoin;
     uint32_t maybeCmpOffset = AsmJSHeapAccess::NoLengthCheck;
 
     if (mir->needsBoundsCheck()) {
-        maybeCmpOffset = masm.cmplWithPatch(ptrReg, Imm32(0)).offset();
+        maybeCmpOffset = masm.cmp32WithPatch(ptrReg, Imm32(0)).offset();
         Label goahead;
         masm.j(Assembler::Below, &goahead);
         memoryBarrier(MembarFull);
         Register out = ToRegister(ins->output());
         masm.xorl(out,out);
         masm.jmp(&rejoin);
         masm.bind(&goahead);
     }
@@ -552,17 +552,17 @@ CodeGeneratorX86::visitAsmJSAtomicBinopH
     MOZ_ASSERT(ptr->isRegister());
     // Set up the offset within the heap in the pointer reg.
     Register ptrReg = ToRegister(ptr);
 
     Label rejoin;
     uint32_t maybeCmpOffset = AsmJSHeapAccess::NoLengthCheck;
 
     if (mir->needsBoundsCheck()) {
-        maybeCmpOffset = masm.cmplWithPatch(ptrReg, Imm32(0)).offset();
+        maybeCmpOffset = masm.cmp32WithPatch(ptrReg, Imm32(0)).offset();
         Label goahead;
         masm.j(Assembler::Below, &goahead);
         memoryBarrier(MembarFull);
         Register out = ToRegister(ins->output());
         masm.xorl(out,out);
         masm.jmp(&rejoin);
         masm.bind(&goahead);
     }
@@ -841,17 +841,17 @@ CodeGeneratorX86::visitOutOfLineTruncate
     } else {
         FloatRegister temp = ToFloatRegister(ins->tempFloat());
 
         // Try to convert doubles representing integers within 2^32 of a signed
         // integer, by adding/subtracting 2^32 and then trying to convert to int32.
         // This has to be an exact conversion, as otherwise the truncation works
         // incorrectly on the modified value.
         masm.zeroDouble(ScratchDoubleReg);
-        masm.ucomisd(input, ScratchDoubleReg);
+        masm.ucomisd(ScratchDoubleReg, input);
         masm.j(Assembler::Parity, &fail);
 
         {
             Label positive;
             masm.j(Assembler::Above, &positive);
 
             masm.loadConstantDouble(4294967296.0, temp);
             Label skip;
@@ -861,17 +861,17 @@ CodeGeneratorX86::visitOutOfLineTruncate
             masm.loadConstantDouble(-4294967296.0, temp);
             masm.bind(&skip);
         }
 
         masm.addDouble(input, temp);
         masm.cvttsd2si(temp, output);
         masm.cvtsi2sd(output, ScratchDoubleReg);
 
-        masm.ucomisd(temp, ScratchDoubleReg);
+        masm.ucomisd(ScratchDoubleReg, temp);
         masm.j(Assembler::Parity, &fail);
         masm.j(Assembler::Equal, ool->rejoin());
     }
 
     masm.bind(&fail);
     {
         saveVolatile(output);
 
@@ -915,32 +915,32 @@ CodeGeneratorX86::visitOutOfLineTruncate
         masm.and32(Imm32(EXPONENT_MASK), output);
         masm.branch32(Assembler::GreaterThanOrEqual, output, Imm32(TOO_BIG_EXPONENT), &failPopFloat);
 
         // Load float, perform 32-bit truncation.
         masm.fld32(Operand(esp, 0));
         masm.fisttp(Operand(esp, 0));
 
         // Load low word, pop 64bits and jump back.
-        masm.movl(Operand(esp, 0), output);
+        masm.load32(Address(esp, 0), output);
         masm.addl(Imm32(sizeof(uint64_t)), esp);
         masm.jump(ool->rejoin());
 
         masm.bind(&failPopFloat);
         masm.addl(Imm32(sizeof(uint64_t)), esp);
         masm.jump(&fail);
     } else {
         FloatRegister temp = ToFloatRegister(ins->tempFloat());
 
         // Try to convert float32 representing integers within 2^32 of a signed
         // integer, by adding/subtracting 2^32 and then trying to convert to int32.
         // This has to be an exact conversion, as otherwise the truncation works
         // incorrectly on the modified value.
         masm.zeroFloat32(ScratchFloat32Reg);
-        masm.ucomiss(input, ScratchFloat32Reg);
+        masm.ucomiss(ScratchFloat32Reg, input);
         masm.j(Assembler::Parity, &fail);
 
         {
             Label positive;
             masm.j(Assembler::Above, &positive);
 
             masm.loadConstantFloat32(4294967296.f, temp);
             Label skip;
@@ -950,17 +950,17 @@ CodeGeneratorX86::visitOutOfLineTruncate
             masm.loadConstantFloat32(-4294967296.f, temp);
             masm.bind(&skip);
         }
 
         masm.addFloat32(input, temp);
         masm.cvttss2si(temp, output);
         masm.cvtsi2ss(output, ScratchFloat32Reg);
 
-        masm.ucomiss(temp, ScratchFloat32Reg);
+        masm.ucomiss(ScratchFloat32Reg, temp);
         masm.j(Assembler::Parity, &fail);
         masm.j(Assembler::Equal, ool->rejoin());
     }
 
     masm.bind(&fail);
     {
         saveVolatile(output);
 
--- a/js/src/jit/x86/MacroAssembler-x86.cpp
+++ b/js/src/jit/x86/MacroAssembler-x86.cpp
@@ -286,17 +286,17 @@ MacroAssemblerX86::callWithABIPre(uint32
         emitter.emit(moveResolver_);
         emitter.finish();
     }
 
 #ifdef DEBUG
     {
         // Check call alignment.
         Label good;
-        testl(esp, Imm32(ABIStackAlignment - 1));
+        test32(esp, Imm32(ABIStackAlignment - 1));
         j(Equal, &good);
         breakpoint();
         bind(&good);
     }
 #endif
 }
 
 void
@@ -438,33 +438,33 @@ MacroAssemblerX86::handleFailureWithHand
     jmp(Operand(esp, offsetof(ResumeFromException, target)));
 }
 
 void
 MacroAssemblerX86::branchTestValue(Condition cond, const ValueOperand &value, const Value &v, Label *label)
 {
     jsval_layout jv = JSVAL_TO_IMPL(v);
     if (v.isMarkable())
-        cmpl(value.payloadReg(), ImmGCPtr(reinterpret_cast<gc::Cell *>(v.toGCThing())));
+        cmpPtr(value.payloadReg(), ImmGCPtr(reinterpret_cast<gc::Cell *>(v.toGCThing())));
     else
-        cmpl(value.payloadReg(), Imm32(jv.s.payload.i32));
+        cmpPtr(value.payloadReg(), ImmWord(jv.s.payload.i32));
 
     if (cond == Equal) {
         Label done;
         j(NotEqual, &done);
         {
-            cmpl(value.typeReg(), Imm32(jv.s.tag));
+            cmp32(value.typeReg(), Imm32(jv.s.tag));
             j(Equal, label);
         }
         bind(&done);
     } else {
         MOZ_ASSERT(cond == NotEqual);
         j(NotEqual, label);
 
-        cmpl(value.typeReg(), Imm32(jv.s.tag));
+        cmp32(value.typeReg(), Imm32(jv.s.tag));
         j(NotEqual, label);
     }
 }
 
 template <typename T>
 void
 MacroAssemblerX86::storeUnboxedValue(ConstantOrRegister value, MIRType valueType, const T &dest,
                                      MIRType slotType)
--- a/js/src/jit/x86/MacroAssembler-x86.h
+++ b/js/src/jit/x86/MacroAssembler-x86.h
@@ -266,125 +266,125 @@ class MacroAssemblerX86 : public MacroAs
 
     // Returns the register containing the type tag.
     Register splitTagForTest(const ValueOperand &value) {
         return value.typeReg();
     }
 
     Condition testUndefined(Condition cond, Register tag) {
         MOZ_ASSERT(cond == Equal || cond == NotEqual);
-        cmpl(tag, ImmTag(JSVAL_TAG_UNDEFINED));
+        cmp32(tag, ImmTag(JSVAL_TAG_UNDEFINED));
         return cond;
     }
     Condition testBoolean(Condition cond, Register tag) {
         MOZ_ASSERT(cond == Equal || cond == NotEqual);
-        cmpl(tag, ImmTag(JSVAL_TAG_BOOLEAN));
+        cmp32(tag, ImmTag(JSVAL_TAG_BOOLEAN));
         return cond;
     }
     Condition testInt32(Condition cond, Register tag) {
         MOZ_ASSERT(cond == Equal || cond == NotEqual);
-        cmpl(tag, ImmTag(JSVAL_TAG_INT32));
+        cmp32(tag, ImmTag(JSVAL_TAG_INT32));
         return cond;
     }
     Condition testDouble(Condition cond, Register tag) {
         MOZ_ASSERT(cond == Assembler::Equal || cond == Assembler::NotEqual);
         Condition actual = (cond == Equal) ? Below : AboveOrEqual;
-        cmpl(tag, ImmTag(JSVAL_TAG_CLEAR));
+        cmp32(tag, ImmTag(JSVAL_TAG_CLEAR));
         return actual;
     }
     Condition testNull(Condition cond, Register tag) {
         MOZ_ASSERT(cond == Equal || cond == NotEqual);
-        cmpl(tag, ImmTag(JSVAL_TAG_NULL));
+        cmp32(tag, ImmTag(JSVAL_TAG_NULL));
         return cond;
     }
     Condition testString(Condition cond, Register tag) {
         MOZ_ASSERT(cond == Equal || cond == NotEqual);
-        cmpl(tag, ImmTag(JSVAL_TAG_STRING));
+        cmp32(tag, ImmTag(JSVAL_TAG_STRING));
         return cond;
     }
     Condition testSymbol(Condition cond, Register tag) {
         MOZ_ASSERT(cond == Equal || cond == NotEqual);
-        cmpl(tag, ImmTag(JSVAL_TAG_SYMBOL));
+        cmp32(tag, ImmTag(JSVAL_TAG_SYMBOL));
         return cond;
     }
     Condition testObject(Condition cond, Register tag) {
         MOZ_ASSERT(cond == Equal || cond == NotEqual);
-        cmpl(tag, ImmTag(JSVAL_TAG_OBJECT));
+        cmp32(tag, ImmTag(JSVAL_TAG_OBJECT));
         return cond;
     }
     Condition testNumber(Condition cond, Register tag) {
         MOZ_ASSERT(cond == Equal || cond == NotEqual);
-        cmpl(tag, ImmTag(JSVAL_UPPER_INCL_TAG_OF_NUMBER_SET));
+        cmp32(tag, ImmTag(JSVAL_UPPER_INCL_TAG_OF_NUMBER_SET));
         return cond == Equal ? BelowOrEqual : Above;
     }
     Condition testGCThing(Condition cond, Register tag) {
         MOZ_ASSERT(cond == Equal || cond == NotEqual);
-        cmpl(tag, ImmTag(JSVAL_LOWER_INCL_TAG_OF_GCTHING_SET));
+        cmp32(tag, ImmTag(JSVAL_LOWER_INCL_TAG_OF_GCTHING_SET));
         return cond == Equal ? AboveOrEqual : Below;
     }
     Condition testGCThing(Condition cond, const Address &address) {
         MOZ_ASSERT(cond == Equal || cond == NotEqual);
-        cmpl(tagOf(address), ImmTag(JSVAL_LOWER_INCL_TAG_OF_GCTHING_SET));
+        cmp32(tagOf(address), ImmTag(JSVAL_LOWER_INCL_TAG_OF_GCTHING_SET));
         return cond == Equal ? AboveOrEqual : Below;
     }
     Condition testMagic(Condition cond, const Address &address) {
         MOZ_ASSERT(cond == Equal || cond == NotEqual);
-        cmpl(tagOf(address), ImmTag(JSVAL_TAG_MAGIC));
+        cmp32(tagOf(address), ImmTag(JSVAL_TAG_MAGIC));
         return cond;
     }
     Condition testMagic(Condition cond, Register tag) {
         MOZ_ASSERT(cond == Equal || cond == NotEqual);
-        cmpl(tag, ImmTag(JSVAL_TAG_MAGIC));
+        cmp32(tag, ImmTag(JSVAL_TAG_MAGIC));
         return cond;
     }
     Condition testMagic(Condition cond, const Operand &operand) {
         MOZ_ASSERT(cond == Equal || cond == NotEqual);
-        cmpl(ToType(operand), ImmTag(JSVAL_TAG_MAGIC));
+        cmp32(ToType(operand), ImmTag(JSVAL_TAG_MAGIC));
         return cond;
     }
     Condition testPrimitive(Condition cond, Register tag) {
         MOZ_ASSERT(cond == Equal || cond == NotEqual);
-        cmpl(tag, ImmTag(JSVAL_UPPER_EXCL_TAG_OF_PRIMITIVE_SET));
+        cmp32(tag, ImmTag(JSVAL_UPPER_EXCL_TAG_OF_PRIMITIVE_SET));
         return cond == Equal ? Below : AboveOrEqual;
     }
     Condition testError(Condition cond, Register tag) {
         return testMagic(cond, tag);
     }
     Condition testInt32(Condition cond, const Operand &operand) {
         MOZ_ASSERT(cond == Equal || cond == NotEqual);
-        cmpl(ToType(operand), ImmTag(JSVAL_TAG_INT32));
+        cmp32(ToType(operand), ImmTag(JSVAL_TAG_INT32));
         return cond;
     }
     Condition testInt32(Condition cond, const Address &address) {
         MOZ_ASSERT(cond == Equal || cond == NotEqual);
         return testInt32(cond, Operand(address));
     }
     Condition testDouble(Condition cond, const Operand &operand) {
         MOZ_ASSERT(cond == Equal || cond == NotEqual);
         Condition actual = (cond == Equal) ? Below : AboveOrEqual;
-        cmpl(ToType(operand), ImmTag(JSVAL_TAG_CLEAR));
+        cmp32(ToType(operand), ImmTag(JSVAL_TAG_CLEAR));
         return actual;
     }
     Condition testDouble(Condition cond, const Address &address) {
         MOZ_ASSERT(cond == Equal || cond == NotEqual);
         return testDouble(cond, Operand(address));
     }
 
 
     Condition testUndefined(Condition cond, const Operand &operand) {
         MOZ_ASSERT(cond == Equal || cond == NotEqual);
-        cmpl(ToType(operand), ImmTag(JSVAL_TAG_UNDEFINED));
+        cmp32(ToType(operand), ImmTag(JSVAL_TAG_UNDEFINED));
         return cond;
     }
     Condition testUndefined(Condition cond, const Address &addr) {
         return testUndefined(cond, Operand(addr));
     }
     Condition testNull(Condition cond, const Operand &operand) {
         MOZ_ASSERT(cond == Equal || cond == NotEqual);
-        cmpl(ToType(operand), ImmTag(JSVAL_TAG_NULL));
+        cmp32(ToType(operand), ImmTag(JSVAL_TAG_NULL));
         return cond;
     }
     Condition testNull(Condition cond, const Address &addr) {
         return testNull(cond, Operand(addr));
     }
 
     Condition testUndefined(Condition cond, const ValueOperand &value) {
         return testUndefined(cond, value.typeReg());
@@ -424,63 +424,63 @@ class MacroAssemblerX86 : public MacroAs
     }
     Condition testPrimitive(Condition cond, const ValueOperand &value) {
         return testPrimitive(cond, value.typeReg());
     }
 
 
     Condition testUndefined(Condition cond, const BaseIndex &address) {
         MOZ_ASSERT(cond == Equal || cond == NotEqual);
-        cmpl(tagOf(address), ImmTag(JSVAL_TAG_UNDEFINED));
+        cmp32(tagOf(address), ImmTag(JSVAL_TAG_UNDEFINED));
         return cond;
     }
     Condition testNull(Condition cond, const BaseIndex &address) {
         MOZ_ASSERT(cond == Equal || cond == NotEqual);
-        cmpl(tagOf(address), ImmTag(JSVAL_TAG_NULL));
+        cmp32(tagOf(address), ImmTag(JSVAL_TAG_NULL));
         return cond;
     }
     Condition testBoolean(Condition cond, const BaseIndex &address) {
         MOZ_ASSERT(cond == Equal || cond == NotEqual);
-        cmpl(tagOf(address), ImmTag(JSVAL_TAG_BOOLEAN));
+        cmp32(tagOf(address), ImmTag(JSVAL_TAG_BOOLEAN));
         return cond;
     }
     Condition testString(Condition cond, const BaseIndex &address) {
         MOZ_ASSERT(cond == Equal || cond == NotEqual);
-        cmpl(tagOf(address), ImmTag(JSVAL_TAG_STRING));
+        cmp32(tagOf(address), ImmTag(JSVAL_TAG_STRING));
         return cond;
     }
     Condition testSymbol(Condition cond, const BaseIndex &address) {
         MOZ_ASSERT(cond == Equal || cond == NotEqual);
-        cmpl(tagOf(address), ImmTag(JSVAL_TAG_SYMBOL));
+        cmp32(tagOf(address), ImmTag(JSVAL_TAG_SYMBOL));
         return cond;
     }
     Condition testInt32(Condition cond, const BaseIndex &address) {
         MOZ_ASSERT(cond == Equal || cond == NotEqual);
-        cmpl(tagOf(address), ImmTag(JSVAL_TAG_INT32));
+        cmp32(tagOf(address), ImmTag(JSVAL_TAG_INT32));
         return cond;
     }
     Condition testObject(Condition cond, const BaseIndex &address) {
         MOZ_ASSERT(cond == Equal || cond == NotEqual);
-        cmpl(tagOf(address), ImmTag(JSVAL_TAG_OBJECT));
+        cmp32(tagOf(address), ImmTag(JSVAL_TAG_OBJECT));
         return cond;
     }
     Condition testDouble(Condition cond, const BaseIndex &address) {
         MOZ_ASSERT(cond == Equal || cond == NotEqual);
         Condition actual = (cond == Equal) ? Below : AboveOrEqual;
-        cmpl(tagOf(address), ImmTag(JSVAL_TAG_CLEAR));
+        cmp32(tagOf(address), ImmTag(JSVAL_TAG_CLEAR));
         return actual;
     }
     Condition testMagic(Condition cond, const BaseIndex &address) {
         MOZ_ASSERT(cond == Equal || cond == NotEqual);
-        cmpl(tagOf(address), ImmTag(JSVAL_TAG_MAGIC));
+        cmp32(tagOf(address), ImmTag(JSVAL_TAG_MAGIC));
         return cond;
     }
     Condition testGCThing(Condition cond, const BaseIndex &address) {
         MOZ_ASSERT(cond == Equal || cond == NotEqual);
-        cmpl(tagOf(address), ImmTag(JSVAL_LOWER_INCL_TAG_OF_GCTHING_SET));
+        cmp32(tagOf(address), ImmTag(JSVAL_LOWER_INCL_TAG_OF_GCTHING_SET));
         return cond == Equal ? AboveOrEqual : Below;
     }
 
 
 
     void branchTestValue(Condition cond, const ValueOperand &value, const Value &v, Label *label);
     void branchTestValue(Condition cond, const Address &valaddr, const ValueOperand &value,
                          Label *label)
@@ -510,53 +510,68 @@ class MacroAssemblerX86 : public MacroAs
     }
 
     void testUndefinedSet(Condition cond, const ValueOperand &value, Register dest) {
         cond = testUndefined(cond, value);
         emitSet(cond, dest);
     }
 
     void cmpPtr(Register lhs, const ImmWord rhs) {
-        cmpl(lhs, Imm32(rhs.value));
+        cmpl(Imm32(rhs.value), lhs);
     }
     void cmpPtr(Register lhs, const ImmPtr imm) {
         cmpPtr(lhs, ImmWord(uintptr_t(imm.value)));
     }
     void cmpPtr(Register lhs, const ImmGCPtr rhs) {
-        cmpl(lhs, rhs);
+        cmpl(rhs, lhs);
     }
-    void cmpPtr(Register lhs, const Imm32 rhs) {
-        cmpl(lhs, rhs);
+    void cmpPtr(const Operand &lhs, Imm32 rhs) {
+        cmp32(lhs, rhs);
     }
     void cmpPtr(const Operand &lhs, const ImmWord rhs) {
-        cmpl(lhs, rhs);
+        cmp32(lhs, Imm32(rhs.value));
     }
     void cmpPtr(const Operand &lhs, const ImmPtr imm) {
         cmpPtr(lhs, ImmWord(uintptr_t(imm.value)));
     }
     void cmpPtr(const Operand &lhs, const ImmGCPtr rhs) {
-        cmpl(lhs, rhs);
-    }
-    void cmpPtr(const Operand &lhs, const Imm32 rhs) {
-        cmpl(lhs, rhs);
+        cmpl(rhs, lhs);
     }
     void cmpPtr(const Address &lhs, Register rhs) {
-        cmpl(Operand(lhs), rhs);
+        cmpPtr(Operand(lhs), rhs);
+    }
+    void cmpPtr(const Operand &lhs, Register rhs) {
+        cmp32(lhs, rhs);
     }
     void cmpPtr(const Address &lhs, const ImmWord rhs) {
-        cmpl(Operand(lhs), rhs);
+        cmpPtr(Operand(lhs), rhs);
     }
     void cmpPtr(const Address &lhs, const ImmPtr rhs) {
         cmpPtr(lhs, ImmWord(uintptr_t(rhs.value)));
     }
     void cmpPtr(Register lhs, Register rhs) {
-        cmpl(lhs, rhs);
+        cmp32(lhs, rhs);
+    }
+    void cmpPtr(const Operand &lhs, ImmMaybeNurseryPtr rhs) {
+        cmpl(rhs, lhs);
     }
     void testPtr(Register lhs, Register rhs) {
-        testl(lhs, rhs);
+        test32(lhs, rhs);
+    }
+    void testPtr(Register lhs, Imm32 rhs) {
+        test32(lhs, rhs);
+    }
+    void testPtr(Register lhs, ImmWord rhs) {
+        test32(lhs, Imm32(rhs.value));
+    }
+    void testPtr(const Operand &lhs, Imm32 rhs) {
+        test32(lhs, rhs);
+    }
+    void testPtr(const Operand &lhs, ImmWord rhs) {
+        test32(lhs, Imm32(rhs.value));
     }
 
     template <typename T1, typename T2>
     void cmpPtrSet(Assembler::Condition cond, T1 lhs, T2 rhs, Register dest)
     {
         cmpPtr(lhs, rhs);
         emitSet(cond, dest);
     }
@@ -587,92 +602,92 @@ class MacroAssemblerX86 : public MacroAs
             addl(Imm32(amount), StackPointer);
         framePushed_ -= amount;
     }
     void freeStack(Register amount) {
         addl(amount, StackPointer);
     }
 
     void addPtr(Register src, Register dest) {
-        addl(src, dest);
+        add32(src, dest);
     }
     void addPtr(Imm32 imm, Register dest) {
-        addl(imm, dest);
+        add32(imm, dest);
     }
     void addPtr(ImmWord imm, Register dest) {
-        addl(Imm32(imm.value), dest);
+        add32(Imm32(imm.value), dest);
     }
     void addPtr(ImmPtr imm, Register dest) {
         addPtr(ImmWord(uintptr_t(imm.value)), dest);
     }
     void addPtr(Imm32 imm, const Address &dest) {
-        addl(imm, Operand(dest));
+        add32(imm, Operand(dest));
     }
     void addPtr(Imm32 imm, const Operand &dest) {
-        addl(imm, dest);
+        add32(imm, dest);
     }
     void addPtr(const Address &src, Register dest) {
         addl(Operand(src), dest);
     }
     void subPtr(Imm32 imm, Register dest) {
-        subl(imm, dest);
+        sub32(imm, dest);
     }
     void subPtr(Register src, Register dest) {
-        subl(src, dest);
+        sub32(src, dest);
     }
     void subPtr(const Address &addr, Register dest) {
-        subl(Operand(addr), dest);
+        sub32(Operand(addr), dest);
     }
     void subPtr(Register src, const Address &dest) {
-        subl(src, Operand(dest));
+        sub32(src, Operand(dest));
     }
     void mulBy3(const Register &src, const Register &dest) {
         lea(Operand(src, src, TimesTwo), dest);
     }
 
     void branch32(Condition cond, AbsoluteAddress lhs, Imm32 rhs, Label *label) {
-        cmpl(Operand(lhs), rhs);
+        cmp32(Operand(lhs), rhs);
         j(cond, label);
     }
     void branch32(Condition cond, AsmJSAbsoluteAddress lhs, Imm32 rhs, Label *label) {
-        cmpl(lhs, rhs);
+        cmpl(rhs, lhs);
         j(cond, label);
     }
     void branch32(Condition cond, AbsoluteAddress lhs, Register rhs, Label *label) {
-        cmpl(Operand(lhs), rhs);
+        cmp32(Operand(lhs), rhs);
         j(cond, label);
     }
     void branchTest32(Condition cond, AbsoluteAddress address, Imm32 imm, Label *label) {
-        testl(Operand(address), imm);
+        test32(Operand(address), imm);
         j(cond, label);
     }
 
     // Specialization for AsmJSAbsoluteAddress.
     void branchPtr(Condition cond, AsmJSAbsoluteAddress lhs, Register ptr, Label *label) {
-        cmpl(lhs, ptr);
+        cmpl(ptr, lhs);
         j(cond, label);
     }
 
     template <typename T, typename S>
     void branchPtr(Condition cond, T lhs, S ptr, Label *label) {
-        cmpl(Operand(lhs), ptr);
+        cmpPtr(Operand(lhs), ptr);
         j(cond, label);
     }
 
     void branchPrivatePtr(Condition cond, const Address &lhs, ImmPtr ptr, Label *label) {
         branchPtr(cond, lhs, ptr, label);
     }
 
     void branchPrivatePtr(Condition cond, const Address &lhs, Register ptr, Label *label) {
         branchPtr(cond, lhs, ptr, label);
     }
 
     template <typename T, typename S>
     void branchPtr(Condition cond, T lhs, S ptr, RepatchLabel *label) {
-        cmpl(Operand(lhs), ptr);
+        cmpPtr(Operand(lhs), ptr);
         j(cond, label);
     }
 
     CodeOffsetJump jumpWithPatch(RepatchLabel *label) {
         jump(label);
         return CodeOffsetJump(size());
     }
 
@@ -686,33 +701,33 @@ class MacroAssemblerX86 : public MacroAs
     }
 
     template <typename S, typename T>
     CodeOffsetJump branchPtrWithPatch(Condition cond, S lhs, T ptr, RepatchLabel *label) {
         branchPtr(cond, lhs, ptr, label);
         return CodeOffsetJump(size());
     }
     void branchPtr(Condition cond, Register lhs, Register rhs, RepatchLabel *label) {
-        cmpl(lhs, rhs);
+        cmpPtr(lhs, rhs);
         j(cond, label);
     }
     void branchPtr(Condition cond, Register lhs, Register rhs, Label *label) {
-        cmpl(lhs, rhs);
+        cmpPtr(lhs, rhs);
         j(cond, label);
     }
     void branchTestPtr(Condition cond, Register lhs, Register rhs, Label *label) {
-        testl(lhs, rhs);
+        testPtr(lhs, rhs);
         j(cond, label);
     }
     void branchTestPtr(Condition cond, Register lhs, Imm32 imm, Label *label) {
-        testl(lhs, imm);
+        testPtr(lhs, imm);
         j(cond, label);
     }
     void branchTestPtr(Condition cond, const Address &lhs, Imm32 imm, Label *label) {
-        testl(Operand(lhs), imm);
+        testPtr(Operand(lhs), imm);
         j(cond, label);
     }
     void decBranchPtr(Condition cond, Register lhs, Imm32 imm, Label *label) {
         subPtr(imm, lhs);
         j(cond, label);
     }
 
     void movePtr(ImmWord imm, Register dest) {
@@ -981,44 +996,44 @@ class MacroAssemblerX86 : public MacroAs
     void loadConstantFloat32x4(const SimdConstant &v, FloatRegister dest);
 
     void branchTruncateDouble(FloatRegister src, Register dest, Label *fail) {
         cvttsd2si(src, dest);
 
         // cvttsd2si returns 0x80000000 on failure. Test for it by
         // subtracting 1 and testing overflow (this permits the use of a
         // smaller immediate field).
-        cmpl(dest, Imm32(1));
+        cmp32(dest, Imm32(1));
         j(Assembler::Overflow, fail);
     }
     void branchTruncateFloat32(FloatRegister src, Register dest, Label *fail) {
         cvttss2si(src, dest);
 
         // cvttss2si returns 0x80000000 on failure. Test for it by
         // subtracting 1 and testing overflow (this permits the use of a
         // smaller immediate field).
-        cmpl(dest, Imm32(1));
+        cmp32(dest, Imm32(1));
         j(Assembler::Overflow, fail);
     }
 
     Condition testInt32Truthy(bool truthy, const ValueOperand &operand) {
-        testl(operand.payloadReg(), operand.payloadReg());
+        test32(operand.payloadReg(), operand.payloadReg());
         return truthy ? NonZero : Zero;
     }
     void branchTestInt32Truthy(bool truthy, const ValueOperand &operand, Label *label) {
         Condition cond = testInt32Truthy(truthy, operand);
         j(cond, label);
     }
     void branchTestBooleanTruthy(bool truthy, const ValueOperand &operand, Label *label) {
-        testl(operand.payloadReg(), operand.payloadReg());
+        test32(operand.payloadReg(), operand.payloadReg());
         j(truthy ? NonZero : Zero, label);
     }
     Condition testStringTruthy(bool truthy, const ValueOperand &value) {
         Register string = value.payloadReg();
-        cmpl(Operand(string, JSString::offsetOfLength()), Imm32(0));
+        cmp32(Operand(string, JSString::offsetOfLength()), Imm32(0));
         return truthy ? Assembler::NotEqual : Assembler::Equal;
     }
     void branchTestStringTruthy(bool truthy, const ValueOperand &value, Label *label) {
         Condition cond = testStringTruthy(truthy, value);
         j(cond, label);
     }
 
     void loadInt32OrDouble(const Operand &operand, FloatRegister dest) {
@@ -1161,17 +1176,17 @@ class MacroAssemblerX86 : public MacroAs
     void handleFailureWithHandlerTail();
 
     void makeFrameDescriptor(Register frameSizeReg, FrameType type) {
         shll(Imm32(FRAMESIZE_SHIFT), frameSizeReg);
         orl(Imm32(type), frameSizeReg);
     }
 
     void callWithExitFrame(JitCode *target, Register dynStack) {
-        addPtr(Imm32(framePushed()), dynStack);
+        addPtr(ImmWord(framePushed()), dynStack);
         makeFrameDescriptor(dynStack, JitFrame_IonJS);
         Push(dynStack);
         call(target);
     }
 
     void branchPtrInNurseryRange(Condition cond, Register ptr, Register temp, Label *label);
     void branchValueIsNurseryObject(Condition cond, ValueOperand value, Register temp, Label *label);
 };
--- a/js/src/jit/x86/Trampoline-x86.cpp
+++ b/js/src/jit/x86/Trampoline-x86.cpp
@@ -100,17 +100,17 @@ JitRuntime::generateEnterJIT(JSContext *
     // eax = argv[8(argc)]  --eax now points one value past the last argument
     masm.addl(ebx, eax);
 
     // while (eax > ebx)  --while still looping through arguments
     {
         Label header, footer;
         masm.bind(&header);
 
-        masm.cmpl(eax, ebx);
+        masm.cmp32(eax, ebx);
         masm.j(Assembler::BelowOrEqual, &footer);
 
         // eax -= 8  --move to previous argument
         masm.subl(Imm32(8), eax);
 
         // Push what eax points to on stack, a Value is 2 words
         masm.push(Operand(eax, 4));
         masm.push(Operand(eax, 0));