Backed out changeset 2e15d016544a (bug 1044256) for failures in testSIMD.js; CLOSED TREE
authorEd Morley <emorley@mozilla.com>
Tue, 07 Oct 2014 16:25:08 +0100
changeset 209201 279aac062e97caa4f4c3c14f0e1d8edb292758f5
parent 209200 a9a291cb900b6223ced10e5a68e3387e30d1d0d3
child 209202 9a8039fb50557f576e7f8b6cb8c4f3c1ce574136
push id11223
push userryanvm@gmail.com
push dateTue, 07 Oct 2014 20:12:37 +0000
treeherderb2g-inbound@f01a513e84a5 [default view] [failures only]
perfherder[talos] [build metrics] [platform microbench] (compared to previous push)
bugs1044256
milestone35.0a1
backs out2e15d016544a16ddf87004dc206e93e664de0847
Backed out changeset 2e15d016544a (bug 1044256) for failures in testSIMD.js; CLOSED TREE
js/src/jit/IonTypes.h
js/src/jit/LIR-Common.h
js/src/jit/LOpcodes.h
js/src/jit/Lowering.cpp
js/src/jit/Lowering.h
js/src/jit/MIR.h
js/src/jit/MOpcodes.h
js/src/jit/ParallelSafetyAnalysis.cpp
js/src/jit/shared/Assembler-x86-shared.h
js/src/jit/shared/BaseAssembler-x86-shared.h
js/src/jit/shared/CodeGenerator-x86-shared.cpp
js/src/jit/shared/CodeGenerator-x86-shared.h
js/src/jit/shared/MacroAssembler-x86-shared.h
--- a/js/src/jit/IonTypes.h
+++ b/js/src/jit/IonTypes.h
@@ -279,36 +279,26 @@ class SimdConstant {
         cst.fillInt32x4(x, y, z, w);
         return cst;
     }
     static SimdConstant CreateX4(int32_t *array) {
         SimdConstant cst;
         cst.fillInt32x4(array[0], array[1], array[2], array[3]);
         return cst;
     }
-    static SimdConstant SplatX4(int32_t v) {
-        SimdConstant cst;
-        cst.fillInt32x4(v, v, v, v);
-        return cst;
-    }
     static SimdConstant CreateX4(float x, float y, float z, float w) {
         SimdConstant cst;
         cst.fillFloat32x4(x, y, z, w);
         return cst;
     }
     static SimdConstant CreateX4(float *array) {
         SimdConstant cst;
         cst.fillFloat32x4(array[0], array[1], array[2], array[3]);
         return cst;
     }
-    static SimdConstant SplatX4(float v) {
-        SimdConstant cst;
-        cst.fillFloat32x4(v, v, v, v);
-        return cst;
-    }
 
     uint32_t length() const {
         MOZ_ASSERT(defined());
         switch(type_) {
           case Int32x4:
           case Float32x4:
             return 4;
           case Undefined:
--- a/js/src/jit/LIR-Common.h
+++ b/js/src/jit/LIR-Common.h
@@ -305,44 +305,16 @@ class LSimdBinaryArithIx4 : public LSimd
 // Binary SIMD arithmetic operation between two Float32x4 operands
 class LSimdBinaryArithFx4 : public LSimdBinaryArith
 {
   public:
     LIR_HEADER(SimdBinaryArithFx4);
     LSimdBinaryArithFx4() : LSimdBinaryArith() {}
 };
 
-// Unary SIMD arithmetic operation on a SIMD operand
-class LSimdUnaryArith : public LInstructionHelper<1, 1, 0>
-{
-  public:
-    explicit LSimdUnaryArith(const LAllocation &in) {
-        setOperand(0, in);
-    }
-    MSimdUnaryArith::Operation operation() const {
-        return mir_->toSimdUnaryArith()->operation();
-    }
-};
-
-// Unary SIMD arithmetic operation on a Int32x4 operand
-class LSimdUnaryArithIx4 : public LSimdUnaryArith
-{
-  public:
-    LIR_HEADER(SimdUnaryArithIx4);
-    explicit LSimdUnaryArithIx4(const LAllocation &in) : LSimdUnaryArith(in) {}
-};
-
-// Unary SIMD arithmetic operation on a Float32x4 operand
-class LSimdUnaryArithFx4 : public LSimdUnaryArith
-{
-  public:
-    LIR_HEADER(SimdUnaryArithFx4);
-    explicit LSimdUnaryArithFx4(const LAllocation &in) : LSimdUnaryArith(in) {}
-};
-
 // Binary SIMD bitwise operation between two int32x4 or float32x4 operands
 class LSimdBinaryBitwiseX4 : public LInstructionHelper<1, 2, 0>
 {
   public:
     LIR_HEADER(SimdBinaryBitwiseX4);
     const LAllocation *lhs() {
         return getOperand(0);
     }
--- a/js/src/jit/LOpcodes.h
+++ b/js/src/jit/LOpcodes.h
@@ -19,18 +19,16 @@
     _(SimdSplatX4)                  \
     _(Int32x4)                      \
     _(Float32x4)                    \
     _(SimdExtractElementI)          \
     _(SimdExtractElementF)          \
     _(SimdInsertElementI)           \
     _(SimdInsertElementF)           \
     _(SimdSignMaskX4)               \
-    _(SimdUnaryArithIx4)            \
-    _(SimdUnaryArithFx4)            \
     _(SimdBinaryCompIx4)            \
     _(SimdBinaryCompFx4)            \
     _(SimdBinaryArithIx4)           \
     _(SimdBinaryArithFx4)           \
     _(SimdBinaryBitwiseX4)          \
     _(SimdShift)                    \
     _(SimdSelect)                   \
     _(Value)                        \
--- a/js/src/jit/Lowering.cpp
+++ b/js/src/jit/Lowering.cpp
@@ -3797,38 +3797,16 @@ LIRGenerator::visitSimdSignMask(MSimdSig
         return define(new(alloc()) LSimdSignMaskX4(use), ins);
       default:
         MOZ_CRASH("Unexpected SIMD type extracting sign bits.");
         break;
     }
 }
 
 bool
-LIRGenerator::visitSimdUnaryArith(MSimdUnaryArith *ins)
-{
-    MOZ_ASSERT(IsSimdType(ins->type()));
-
-    // Cannot be at start, as the ouput is used as a temporary to store values.
-    LUse in = use(ins->input());
-
-    if (ins->type() == MIRType_Int32x4) {
-        LSimdUnaryArithIx4 *lir = new(alloc()) LSimdUnaryArithIx4(in);
-        return define(lir, ins);
-    }
-
-    if (ins->type() == MIRType_Float32x4) {
-        LSimdUnaryArithFx4 *lir = new(alloc()) LSimdUnaryArithFx4(in);
-        return define(lir, ins);
-    }
-
-    MOZ_CRASH("Unknown SIMD kind for unary operation");
-    return false;
-}
-
-bool
 LIRGenerator::visitSimdBinaryComp(MSimdBinaryComp *ins)
 {
     MOZ_ASSERT(ins->type() == MIRType_Int32x4);
 
     if (ShouldReorderCommutative(ins->lhs(), ins->rhs(), ins))
         ins->reverse();
 
     if (ins->compareType() == MSimdBinaryComp::CompareInt32x4) {
--- a/js/src/jit/Lowering.h
+++ b/js/src/jit/Lowering.h
@@ -266,17 +266,16 @@ class LIRGenerator : public LIRGenerator
     bool visitAsmJSCall(MAsmJSCall *ins);
     bool visitSetDOMProperty(MSetDOMProperty *ins);
     bool visitGetDOMProperty(MGetDOMProperty *ins);
     bool visitGetDOMMember(MGetDOMMember *ins);
     bool visitRecompileCheck(MRecompileCheck *ins);
     bool visitSimdExtractElement(MSimdExtractElement *ins);
     bool visitSimdInsertElement(MSimdInsertElement *ins);
     bool visitSimdSignMask(MSimdSignMask *ins);
-    bool visitSimdUnaryArith(MSimdUnaryArith *ins);
     bool visitSimdBinaryComp(MSimdBinaryComp *ins);
     bool visitSimdBinaryArith(MSimdBinaryArith *ins);
     bool visitSimdBinaryBitwise(MSimdBinaryBitwise *ins);
     bool visitSimdShift(MSimdShift *ins);
     bool visitSimdConstant(MSimdConstant *ins);
     bool visitSimdConvert(MSimdConvert *ins);
     bool visitSimdReinterpretCast(MSimdReinterpretCast *ins);
     bool visitPhi(MPhi *ins);
--- a/js/src/jit/MIR.h
+++ b/js/src/jit/MIR.h
@@ -1558,62 +1558,16 @@ class MSimdSignMask : public MUnaryInstr
         if (!ins->isSimdSignMask())
             return false;
         return congruentIfOperandsEqual(ins);
     }
 
     ALLOW_CLONE(MSimdSignMask)
 };
 
-class MSimdUnaryArith : public MUnaryInstruction
-{
-  public:
-    enum Operation {
-        abs,
-        neg,
-        not_,
-        reciprocal,
-        reciprocalSqrt,
-        sqrt
-    };
-
-  private:
-    Operation operation_;
-
-    MSimdUnaryArith(MDefinition *def, Operation op, MIRType type)
-      : MUnaryInstruction(def), operation_(op)
-    {
-        MOZ_ASSERT(IsSimdType(type));
-        MOZ_ASSERT(def->type() == type);
-        MOZ_ASSERT_IF(type == MIRType_Int32x4, op == neg || op == not_);
-        setResultType(type);
-        setMovable();
-    }
-
-  public:
-    INSTRUCTION_HEADER(SimdUnaryArith);
-    static MSimdUnaryArith *NewAsmJS(TempAllocator &alloc, MDefinition *def,
-                                     Operation op, MIRType t)
-    {
-        return new(alloc) MSimdUnaryArith(def, op, t);
-    }
-
-    Operation operation() const { return operation_; }
-
-    AliasSet getAliasSet() const {
-        return AliasSet::None();
-    }
-
-    bool congruentTo(const MDefinition *ins) const {
-        return congruentIfOperandsEqual(ins) && ins->toSimdUnaryArith()->operation() == operation();
-    }
-
-    ALLOW_CLONE(MSimdUnaryArith);
-};
-
 // Compares each value of a SIMD vector to each corresponding lane's value of
 // another SIMD vector, and returns a int32x4 vector containing the results of
 // the comparison: all bits are set to 1 if the comparison is true, 0 otherwise.
 class MSimdBinaryComp : public MBinaryInstruction
 {
   public:
     enum Operation {
         greaterThan,
--- a/js/src/jit/MOpcodes.h
+++ b/js/src/jit/MOpcodes.h
@@ -15,17 +15,16 @@ namespace jit {
     _(SimdValueX4)                                                          \
     _(SimdSplatX4)                                                          \
     _(SimdConstant)                                                         \
     _(SimdConvert)                                                          \
     _(SimdReinterpretCast)                                                  \
     _(SimdExtractElement)                                                   \
     _(SimdInsertElement)                                                    \
     _(SimdSignMask)                                                         \
-    _(SimdUnaryArith)                                                       \
     _(SimdBinaryComp)                                                       \
     _(SimdBinaryArith)                                                      \
     _(SimdBinaryBitwise)                                                    \
     _(SimdShift)                                                            \
     _(SimdTernaryBitwise)                                                   \
     _(CloneLiteral)                                                         \
     _(Parameter)                                                            \
     _(Callee)                                                               \
--- a/js/src/jit/ParallelSafetyAnalysis.cpp
+++ b/js/src/jit/ParallelSafetyAnalysis.cpp
@@ -114,17 +114,16 @@ class ParallelSafetyVisitor : public MDe
     SAFE_OP(SimdValueX4)
     SAFE_OP(SimdSplatX4)
     SAFE_OP(SimdConstant)
     SAFE_OP(SimdConvert)
     SAFE_OP(SimdReinterpretCast)
     SAFE_OP(SimdExtractElement)
     SAFE_OP(SimdInsertElement)
     SAFE_OP(SimdSignMask)
-    SAFE_OP(SimdUnaryArith)
     SAFE_OP(SimdBinaryComp)
     SAFE_OP(SimdBinaryArith)
     SAFE_OP(SimdBinaryBitwise)
     SAFE_OP(SimdShift)
     SAFE_OP(SimdTernaryBitwise)
     UNSAFE_OP(CloneLiteral)
     SAFE_OP(Parameter)
     SAFE_OP(Callee)
--- a/js/src/jit/shared/Assembler-x86-shared.h
+++ b/js/src/jit/shared/Assembler-x86-shared.h
@@ -1595,64 +1595,16 @@ class AssemblerX86Shared : public Assemb
             break;
           case Operand::MEM_ADDRESS32:
             masm.cmpps_mr(src.address(), dest.code(), order);
             break;
           default:
             MOZ_CRASH("unexpected operand kind");
         }
     }
-    void rcpps(const Operand &src, FloatRegister dest) {
-        MOZ_ASSERT(HasSSE2());
-        switch (src.kind()) {
-          case Operand::FPREG:
-            masm.rcpps_rr(src.fpu(), dest.code());
-            break;
-          case Operand::MEM_REG_DISP:
-            masm.rcpps_mr(src.disp(), src.base(), dest.code());
-            break;
-          case Operand::MEM_ADDRESS32:
-            masm.rcpps_mr(src.address(), dest.code());
-            break;
-          default:
-            MOZ_CRASH("unexpected operand kind");
-        }
-    }
-    void sqrtps(const Operand &src, FloatRegister dest) {
-        MOZ_ASSERT(HasSSE2());
-        switch (src.kind()) {
-          case Operand::FPREG:
-            masm.sqrtps_rr(src.fpu(), dest.code());
-            break;
-          case Operand::MEM_REG_DISP:
-            masm.sqrtps_mr(src.disp(), src.base(), dest.code());
-            break;
-          case Operand::MEM_ADDRESS32:
-            masm.sqrtps_mr(src.address(), dest.code());
-            break;
-          default:
-            MOZ_CRASH("unexpected operand kind");
-        }
-    }
-    void rsqrtps(const Operand &src, FloatRegister dest) {
-        MOZ_ASSERT(HasSSE2());
-        switch (src.kind()) {
-          case Operand::FPREG:
-            masm.rsqrtps_rr(src.fpu(), dest.code());
-            break;
-          case Operand::MEM_REG_DISP:
-            masm.rsqrtps_mr(src.disp(), src.base(), dest.code());
-            break;
-          case Operand::MEM_ADDRESS32:
-            masm.rsqrtps_mr(src.address(), dest.code());
-            break;
-          default:
-            MOZ_CRASH("unexpected operand kind");
-        }
-    }
     void movd(Register src, FloatRegister dest) {
         MOZ_ASSERT(HasSSE2());
         masm.movd_rr(src.code(), dest.code());
     }
     void movd(FloatRegister src, Register dest) {
         MOZ_ASSERT(HasSSE2());
         masm.movd_rr(src.code(), dest.code());
     }
--- a/js/src/jit/shared/BaseAssembler-x86-shared.h
+++ b/js/src/jit/shared/BaseAssembler-x86-shared.h
@@ -321,19 +321,16 @@ private:
         OP2_MINPS_VpsWps    = 0x5D,
         OP2_DIVSD_VsdWsd    = 0x5E,
         OP2_DIVPS_VpsWps    = 0x5E,
         OP2_MAXSD_VsdWsd    = 0x5F,
         OP2_MAXSS_VssWss    = 0x5F,
         OP2_MAXPS_VpsWps    = 0x5F,
         OP2_SQRTSD_VsdWsd   = 0x51,
         OP2_SQRTSS_VssWss   = 0x51,
-        OP2_SQRTPS_VpsWps   = 0x51,
-        OP2_RSQRTPS_VpsWps  = 0x52,
-        OP2_RCPPS_VpsWps    = 0x53,
         OP2_ANDPD_VpdWpd    = 0x54,
         OP2_ORPD_VpdWpd     = 0x56,
         OP2_XORPD_VpdWpd    = 0x57,
         OP2_PCMPGTD_VdqWdq  = 0x66,
         OP2_MOVD_VdEd       = 0x6E,
         OP2_MOVDQ_VsdWsd    = 0x6F,
         OP2_MOVDQ_VdqWdq    = 0x6F,
         OP2_PSHUFD_VdqWdqIb = 0x70,
@@ -2672,66 +2669,16 @@ public:
     void cmpps_mr(const void* address, XMMRegisterID dst, uint8_t order)
     {
         spew("cmpps     %p, %s, %u",
              address, nameFPReg(dst), order);
         m_formatter.twoByteOp(OP2_CMPPS_VpsWps, (RegisterID)dst, address);
         m_formatter.immediate8(order);
     }
 
-    void rcpps_rr(XMMRegisterID src, XMMRegisterID dst){
-        spew("rcpps      %s, %s",
-             nameFPReg(src), nameFPReg(dst));
-        m_formatter.twoByteOp(OP2_RCPPS_VpsWps, (RegisterID)dst, (RegisterID)src);
-    }
-    void rcpps_mr(int offset, RegisterID base, XMMRegisterID dst){
-        spew("rcpps      %s0x%x(%s), %s",
-             PRETTY_PRINT_OFFSET(offset), nameIReg(base), nameFPReg(dst));
-        m_formatter.twoByteOp(OP2_RCPPS_VpsWps, (RegisterID)dst, base, offset);
-    }
-    void rcpps_mr(const void* address, XMMRegisterID dst){
-        spew("rcpps      %p, %s",
-             address, nameFPReg(dst));
-        m_formatter.twoByteOp(OP2_RCPPS_VpsWps, (RegisterID)dst, address);
-    }
-
-    void rsqrtps_rr(XMMRegisterID src, XMMRegisterID dst){
-        spew("rsqrtps    %s, %s",
-             nameFPReg(src), nameFPReg(dst));
-        m_formatter.twoByteOp(OP2_RSQRTPS_VpsWps, (RegisterID)dst, (RegisterID)src);
-    }
-    void rsqrtps_mr(int offset, RegisterID base, XMMRegisterID dst){
-        spew("rsqrtps    %s0x%x(%s), %s",
-             PRETTY_PRINT_OFFSET(offset), nameIReg(base), nameFPReg(dst));
-        m_formatter.twoByteOp(OP2_RSQRTPS_VpsWps, (RegisterID)dst, base, offset);
-    }
-    void rsqrtps_mr(const void* address, XMMRegisterID dst){
-        spew("rsqrtps    %p, %s",
-             address, nameFPReg(dst));
-        m_formatter.twoByteOp(OP2_RSQRTPS_VpsWps, (RegisterID)dst, address);
-    }
-
-    void sqrtps_rr(XMMRegisterID src, XMMRegisterID dst){
-        spew("sqrtps    %s, %s",
-             nameFPReg(src), nameFPReg(dst));
-        m_formatter.twoByteOp(OP2_SQRTPS_VpsWps, (RegisterID)dst, (RegisterID)src);
-    }
-
-    void sqrtps_mr(int offset, RegisterID base, XMMRegisterID dst){
-        spew("sqrtps    %s0x%x(%s), %s",
-             PRETTY_PRINT_OFFSET(offset), nameIReg(base), nameFPReg(dst));
-        m_formatter.twoByteOp(OP2_SQRTPS_VpsWps, (RegisterID)dst, base, offset);
-    }
-
-    void sqrtps_mr(const void* address, XMMRegisterID dst){
-        spew("sqrtps    %p, %s",
-             address, nameFPReg(dst));
-        m_formatter.twoByteOp(OP2_SQRTPS_VpsWps, (RegisterID)dst, address);
-    }
-
     void addsd_rr(XMMRegisterID src, XMMRegisterID dst)
     {
         spew("addsd      %s, %s",
              nameFPReg(src), nameFPReg(dst));
         m_formatter.prefix(PRE_SSE_F2);
         m_formatter.twoByteOp(OP2_ADDSD_VsdWsd, (RegisterID)dst, (RegisterID)src);
     }
 
--- a/js/src/jit/shared/CodeGenerator-x86-shared.cpp
+++ b/js/src/jit/shared/CodeGenerator-x86-shared.cpp
@@ -2521,85 +2521,16 @@ CodeGeneratorX86Shared::visitSimdBinaryA
         // See comment above.
         masm.minps(rhs, lhs);
         return true;
     }
     MOZ_CRASH("unexpected SIMD op");
 }
 
 bool
-CodeGeneratorX86Shared::visitSimdUnaryArithIx4(LSimdUnaryArithIx4 *ins)
-{
-    Operand in = ToOperand(ins->input());
-    FloatRegister out = ToFloatRegister(ins->output());
-
-    static const SimdConstant allOnes = SimdConstant::CreateX4(-1, -1, -1, -1);
-
-    switch (ins->operation()) {
-      case MSimdUnaryArith::neg:
-        masm.pxor(out, out);
-        masm.packedSubInt32(in, out);
-        return true;
-      case MSimdUnaryArith::not_:
-        masm.loadConstantInt32x4(allOnes, out);
-        masm.bitwiseXorX4(in, out);
-        return true;
-      case MSimdUnaryArith::abs:
-      case MSimdUnaryArith::reciprocal:
-      case MSimdUnaryArith::reciprocalSqrt:
-      case MSimdUnaryArith::sqrt:
-        break;
-    }
-    MOZ_CRASH("unexpected SIMD op");
-}
-
-bool
-CodeGeneratorX86Shared::visitSimdUnaryArithFx4(LSimdUnaryArithFx4 *ins)
-{
-    Operand in = ToOperand(ins->input());
-    FloatRegister out = ToFloatRegister(ins->output());
-
-    // All ones but the sign bit
-    float signMask = SpecificNaN<float>(0, FloatingPoint<float>::kSignificandBits);
-    static const SimdConstant signMasks = SimdConstant::SplatX4(signMask);
-
-    // All ones including the sign bit
-    float ones = SpecificNaN<float>(1, FloatingPoint<float>::kSignificandBits);
-    static const SimdConstant allOnes = SimdConstant::SplatX4(ones);
-
-    // All zeros but the sign bit
-    static const SimdConstant minusZero = SimdConstant::SplatX4(-0.f);
-
-    switch (ins->operation()) {
-      case MSimdUnaryArith::abs:
-        masm.loadConstantFloat32x4(signMasks, out);
-        masm.bitwiseAndX4(in, out);
-        return true;
-      case MSimdUnaryArith::neg:
-        masm.loadConstantFloat32x4(minusZero, out);
-        masm.bitwiseXorX4(in, out);
-        return true;
-      case MSimdUnaryArith::not_:
-        masm.loadConstantFloat32x4(allOnes, out);
-        masm.bitwiseXorX4(in, out);
-        return true;
-      case MSimdUnaryArith::reciprocal:
-        masm.packedReciprocalFloat32x4(in, out);
-        return true;
-      case MSimdUnaryArith::reciprocalSqrt:
-        masm.packedReciprocalSqrtFloat32x4(in, out);
-        return true;
-      case MSimdUnaryArith::sqrt:
-        masm.packedSqrtFloat32x4(in, out);
-        return true;
-    }
-    MOZ_CRASH("unexpected SIMD op");
-}
-
-bool
 CodeGeneratorX86Shared::visitSimdBinaryBitwiseX4(LSimdBinaryBitwiseX4 *ins)
 {
     FloatRegister lhs = ToFloatRegister(ins->lhs());
     Operand rhs = ToOperand(ins->rhs());
     MOZ_ASSERT(ToFloatRegister(ins->output()) == lhs);
 
     MSimdBinaryBitwise::Operation op = ins->operation();
     switch (op) {
--- a/js/src/jit/shared/CodeGenerator-x86-shared.h
+++ b/js/src/jit/shared/CodeGenerator-x86-shared.h
@@ -214,18 +214,16 @@ class CodeGeneratorX86Shared : public Co
     bool visitFloat32x4(LFloat32x4 *ins);
     bool visitInt32x4ToFloat32x4(LInt32x4ToFloat32x4 *ins);
     bool visitFloat32x4ToInt32x4(LFloat32x4ToInt32x4 *ins);
     bool visitSimdExtractElementI(LSimdExtractElementI *lir);
     bool visitSimdExtractElementF(LSimdExtractElementF *lir);
     bool visitSimdInsertElementI(LSimdInsertElementI *lir);
     bool visitSimdInsertElementF(LSimdInsertElementF *lir);
     bool visitSimdSignMaskX4(LSimdSignMaskX4 *ins);
-    bool visitSimdUnaryArithIx4(LSimdUnaryArithIx4 *lir);
-    bool visitSimdUnaryArithFx4(LSimdUnaryArithFx4 *lir);
     bool visitSimdBinaryCompIx4(LSimdBinaryCompIx4 *lir);
     bool visitSimdBinaryCompFx4(LSimdBinaryCompFx4 *lir);
     bool visitSimdBinaryArithIx4(LSimdBinaryArithIx4 *lir);
     bool visitSimdBinaryArithFx4(LSimdBinaryArithFx4 *lir);
     bool visitSimdBinaryBitwiseX4(LSimdBinaryBitwiseX4 *lir);
     bool visitSimdShift(LSimdShift *lir);
     bool visitSimdSelect(LSimdSelect *ins);
 
--- a/js/src/jit/shared/MacroAssembler-x86-shared.h
+++ b/js/src/jit/shared/MacroAssembler-x86-shared.h
@@ -527,29 +527,16 @@ class MacroAssemblerX86Shared : public A
         pcmpgtd(src, dest);
     }
     void packedAddInt32(const Operand &src, FloatRegister dest) {
         paddd(src, dest);
     }
     void packedSubInt32(const Operand &src, FloatRegister dest) {
         psubd(src, dest);
     }
-    void packedReciprocalFloat32x4(const Operand &src, FloatRegister dest) {
-        // This function is an approximation of the result, this might need
-        // fix up if the spec requires a given precision for this operation.
-        // TODO See also bug 1068028.
-        rcpps(src, dest);
-    }
-    void packedReciprocalSqrtFloat32x4(const Operand &src, FloatRegister dest) {
-        // TODO See comment above. See also bug 1068028.
-        rsqrtps(src, dest);
-    }
-    void packedSqrtFloat32x4(const Operand &src, FloatRegister dest) {
-        sqrtps(src, dest);
-    }
 
     void packedLeftShiftByScalar(FloatRegister src, FloatRegister dest) {
         pslld(src, dest);
     }
     void packedLeftShiftByScalar(Imm32 count, FloatRegister dest) {
         pslld(count, dest);
     }
     void packedRightShiftByScalar(FloatRegister src, FloatRegister dest) {