Bug 1115748 - SpiderMonkey: Use int32_t instead of int for x86 immediates and offsets r=jandem
authorDan Gohman <sunfish@mozilla.com>
Sun, 28 Dec 2014 07:04:12 -0800
changeset 221463 0ea34b180725246de813cc4f9846628980973e81
parent 221462 c7fd289fa6fa0a713e9ceb2e5fe045e4f0c1b42b
child 221464 8623d3a5edbeb63de43c472bc50e930501729807
push id12945
push usercbook@mozilla.com
push dateMon, 29 Dec 2014 15:20:49 +0000
treeherderb2g-inbound@eeea99fa576e [default view] [failures only]
perfherder[talos] [build metrics] [platform microbench] (compared to previous push)
reviewersjandem
bugs1115748
milestone37.0a1
Bug 1115748 - SpiderMonkey: Use int32_t instead of int for x86 immediates and offsets r=jandem
js/src/jit/shared/Assembler-x86-shared.h
js/src/jit/shared/BaseAssembler-x86-shared.h
js/src/jit/x64/Assembler-x64.h
--- a/js/src/jit/shared/Assembler-x86-shared.h
+++ b/js/src/jit/shared/Assembler-x86-shared.h
@@ -675,37 +675,37 @@ class AssemblerX86Shared : public Assemb
           case Operand::MEM_SCALE:
             masm.movb_mr(src.disp(), src.base(), src.index(), src.scale(), dest.code());
             break;
           default:
             MOZ_CRASH("unexpected operand kind");
         }
     }
     void movb(Imm32 src, Register dest) {
-        masm.movb_i8r(src.value & 255, dest.code());
+        masm.movb_ir(src.value & 255, dest.code());
     }
     void movb(Register src, const Operand &dest) {
         switch (dest.kind()) {
           case Operand::MEM_REG_DISP:
             masm.movb_rm(src.code(), dest.disp(), dest.base());
             break;
           case Operand::MEM_SCALE:
             masm.movb_rm(src.code(), dest.disp(), dest.base(), dest.index(), dest.scale());
             break;
           default:
             MOZ_CRASH("unexpected operand kind");
         }
     }
     void movb(Imm32 src, const Operand &dest) {
         switch (dest.kind()) {
           case Operand::MEM_REG_DISP:
-            masm.movb_i8m(src.value, dest.disp(), dest.base());
+            masm.movb_im(src.value, dest.disp(), dest.base());
             break;
           case Operand::MEM_SCALE:
-            masm.movb_i8m(src.value, dest.disp(), dest.base(), dest.index(), dest.scale());
+            masm.movb_im(src.value, dest.disp(), dest.base(), dest.index(), dest.scale());
             break;
           default:
             MOZ_CRASH("unexpected operand kind");
         }
     }
     void movzwl(const Operand &src, Register dest) {
         switch (src.kind()) {
           case Operand::REG:
@@ -742,20 +742,20 @@ class AssemblerX86Shared : public Assemb
             break;
           default:
             MOZ_CRASH("unexpected operand kind");
         }
     }
     void movw(Imm32 src, const Operand &dest) {
         switch (dest.kind()) {
           case Operand::MEM_REG_DISP:
-            masm.movw_i16m(src.value, dest.disp(), dest.base());
+            masm.movw_im(src.value, dest.disp(), dest.base());
             break;
           case Operand::MEM_SCALE:
-            masm.movw_i16m(src.value, dest.disp(), dest.base(), dest.index(), dest.scale());
+            masm.movw_im(src.value, dest.disp(), dest.base(), dest.index(), dest.scale());
             break;
           default:
             MOZ_CRASH("unexpected operand kind");
         }
     }
     void movswl(Register src, Register dest) {
         masm.movswl_rr(src.code(), dest.code());
     }
@@ -937,17 +937,17 @@ class AssemblerX86Shared : public Assemb
         return offset - sizeof(void*);
     }
 
     void ret() {
         masm.ret();
     }
     void retn(Imm32 n) {
         // Remove the size of the return address which is included in the frame.
-        masm.ret(n.value - sizeof(void *));
+        masm.ret_i(n.value - sizeof(void *));
     }
     void call(Label *label) {
         if (label->bound()) {
             masm.linkJump(masm.call(), JmpDst(label->offset()));
         } else {
             JmpSrc j = masm.call();
             JmpSrc prev = JmpSrc(label->use(j.offset()));
             masm.setNextJump(j, prev);
@@ -1303,23 +1303,23 @@ class AssemblerX86Shared : public Assemb
           default:
             MOZ_CRASH("unexpected operand kind");
         }
     }
     void notl(Register reg) {
         masm.notl_r(reg.code());
     }
     void shrl(const Imm32 imm, Register dest) {
-        masm.shrl_i8r(imm.value, dest.code());
+        masm.shrl_ir(imm.value, dest.code());
     }
     void shll(const Imm32 imm, Register dest) {
-        masm.shll_i8r(imm.value, dest.code());
+        masm.shll_ir(imm.value, dest.code());
     }
     void sarl(const Imm32 imm, Register dest) {
-        masm.sarl_i8r(imm.value, dest.code());
+        masm.sarl_ir(imm.value, dest.code());
     }
     void shrl_cl(Register dest) {
         masm.shrl_CLr(dest.code());
     }
     void shll_cl(Register dest) {
         masm.shll_CLr(dest.code());
     }
     void sarl_cl(Register dest) {
--- a/js/src/jit/shared/BaseAssembler-x86-shared.h
+++ b/js/src/jit/shared/BaseAssembler-x86-shared.h
@@ -35,19 +35,21 @@
 
 #include "jit/shared/AssemblerBuffer-x86-shared.h"
 
 #include "js/Vector.h"
 
 namespace js {
 namespace jit {
 
-inline bool CAN_SIGN_EXTEND_8_32(int32_t value) { return value == (int32_t)(signed char)value; }
-inline bool CAN_ZERO_EXTEND_8_32(int32_t value) { return value == (int32_t)(unsigned char)value; }
+inline bool CAN_SIGN_EXTEND_8_32(int32_t value) { return value == (int32_t)(int8_t)value; }
+inline bool CAN_SIGN_EXTEND_16_32(int32_t value) { return value == (int32_t)(int16_t)value; }
+inline bool CAN_ZERO_EXTEND_8_32(int32_t value) { return value == (int32_t)(uint8_t)value; }
 inline bool CAN_ZERO_EXTEND_8H_32(int32_t value) { return value == (value & 0xff00); }
+inline bool CAN_ZERO_EXTEND_16_32(int32_t value) { return value == (int32_t)(uint16_t)value; }
 inline bool CAN_ZERO_EXTEND_32_64(int32_t value) { return value >= 0; }
 
 namespace X86Registers {
     enum RegisterID {
         eax,
         ecx,
         edx,
         ebx,
@@ -509,22 +511,22 @@ public:
         friend class X86Assembler;
         friend class X86InstructionFormatter;
     public:
         JmpSrc()
             : m_offset(-1)
         {
         }
 
-        explicit JmpSrc(int offset)
+        explicit JmpSrc(int32_t offset)
             : m_offset(offset)
         {
         }
 
-        int offset() const {
+        int32_t offset() const {
             return m_offset;
         }
 
         bool isSet() const {
             return m_offset != -1;
         }
 
     private:
@@ -540,23 +542,23 @@ public:
             , m_used(false)
         {
         }
 
         bool isUsed() const { return m_used; }
         void used() { m_used = true; }
         bool isValid() const { return m_offset != -1; }
 
-        explicit JmpDst(int offset)
+        explicit JmpDst(int32_t offset)
             : m_offset(offset)
             , m_used(false)
         {
             MOZ_ASSERT(m_offset == offset);
         }
-        int offset() const {
+        int32_t offset() const {
             return m_offset;
         }
     private:
         signed int m_offset : 31;
         bool m_used : 1;
     };
 
     size_t size() const { return m_formatter.size(); }
@@ -586,42 +588,42 @@ public:
     }
 
     void pop_r(RegisterID reg)
     {
         spew("pop        %s", nameIReg(reg));
         m_formatter.oneByteOp(OP_POP_EAX, reg);
     }
 
-    void push_i(int imm)
+    void push_i(int32_t imm)
     {
         spew("push       $%s0x%x", PRETTYHEX(imm));
         if (CAN_SIGN_EXTEND_8_32(imm)) {
             m_formatter.oneByteOp(OP_PUSH_Ib);
-            m_formatter.immediate8(imm);
+            m_formatter.immediate8s(imm);
         } else {
             m_formatter.oneByteOp(OP_PUSH_Iz);
             m_formatter.immediate32(imm);
         }
     }
 
-    void push_i32(int imm)
+    void push_i32(int32_t imm)
     {
         spew("push       $%s0x%04x", PRETTYHEX(imm));
         m_formatter.oneByteOp(OP_PUSH_Iz);
         m_formatter.immediate32(imm);
     }
 
-    void push_m(int offset, RegisterID base)
+    void push_m(int32_t offset, RegisterID base)
     {
         spew("push       " MEM_ob, ADDR_ob(offset, base));
         m_formatter.oneByteOp(OP_GROUP5_Ev, offset, base, GROUP5_OP_PUSH);
     }
 
-    void pop_m(int offset, RegisterID base)
+    void pop_m(int32_t offset, RegisterID base)
     {
         spew("pop        " MEM_ob, ADDR_ob(offset, base));
         m_formatter.oneByteOp(OP_GROUP1A_Ev, offset, base, GROUP1A_OP_POP);
     }
 
     void push_flags()
     {
         spew("pushf");
@@ -632,507 +634,507 @@ public:
     {
         spew("popf");
         m_formatter.oneByteOp(OP_POPFLAGS);
     }
 
     // Arithmetic operations:
 
 #ifdef JS_CODEGEN_X86
-    void adcl_im(int imm, const void* addr)
+    void adcl_im(int32_t imm, const void* addr)
     {
         FIXME_INSN_PRINTING;
         if (CAN_SIGN_EXTEND_8_32(imm)) {
             m_formatter.oneByteOp(OP_GROUP1_EvIb, addr, GROUP1_OP_ADC);
-            m_formatter.immediate8(imm);
+            m_formatter.immediate8s(imm);
         } else {
             m_formatter.oneByteOp(OP_GROUP1_EvIz, addr, GROUP1_OP_ADC);
             m_formatter.immediate32(imm);
         }
     }
 #endif
 
     void addl_rr(RegisterID src, RegisterID dst)
     {
         spew("addl       %s, %s", nameIReg(4,src), nameIReg(4,dst));
         m_formatter.oneByteOp(OP_ADD_GvEv, src, dst);
     }
 
-    void addl_mr(int offset, RegisterID base, RegisterID dst)
+    void addl_mr(int32_t offset, RegisterID base, RegisterID dst)
     {
         spew("addl       " MEM_ob ", %s", ADDR_ob(offset, base), nameIReg(4,dst));
         m_formatter.oneByteOp(OP_ADD_GvEv, offset, base, dst);
     }
 
-    void addl_rm(RegisterID src, int offset, RegisterID base)
+    void addl_rm(RegisterID src, int32_t offset, RegisterID base)
     {
         spew("addl       %s, " MEM_ob, nameIReg(4,src), ADDR_ob(offset, base));
         m_formatter.oneByteOp(OP_ADD_EvGv, offset, base, src);
     }
 
-    void addl_ir(int imm, RegisterID dst)
+    void addl_ir(int32_t imm, RegisterID dst)
     {
         spew("addl       $%d, %s", imm, nameIReg(4,dst));
         if (CAN_SIGN_EXTEND_8_32(imm)) {
             m_formatter.oneByteOp(OP_GROUP1_EvIb, dst, GROUP1_OP_ADD);
-            m_formatter.immediate8(imm);
+            m_formatter.immediate8s(imm);
         } else {
             if (dst == X86Registers::eax)
                 m_formatter.oneByteOp(OP_ADD_EAXIv);
             else
                 m_formatter.oneByteOp(OP_GROUP1_EvIz, dst, GROUP1_OP_ADD);
             m_formatter.immediate32(imm);
         }
     }
-    void addl_i32r(int imm, RegisterID dst)
+    void addl_i32r(int32_t imm, RegisterID dst)
     {
         // 32-bit immediate always, for patching.
         spew("addl       $0x%04x, %s", imm, nameIReg(4,dst));
         if (dst == X86Registers::eax)
             m_formatter.oneByteOp(OP_ADD_EAXIv);
         else
             m_formatter.oneByteOp(OP_GROUP1_EvIz, dst, GROUP1_OP_ADD);
         m_formatter.immediate32(imm);
     }
 
-    void addl_im(int imm, int offset, RegisterID base)
+    void addl_im(int32_t imm, int32_t offset, RegisterID base)
     {
         spew("addl       $%d, " MEM_ob, imm, ADDR_ob(offset, base));
         if (CAN_SIGN_EXTEND_8_32(imm)) {
             m_formatter.oneByteOp(OP_GROUP1_EvIb, offset, base, GROUP1_OP_ADD);
-            m_formatter.immediate8(imm);
+            m_formatter.immediate8s(imm);
         } else {
             m_formatter.oneByteOp(OP_GROUP1_EvIz, offset, base, GROUP1_OP_ADD);
             m_formatter.immediate32(imm);
         }
     }
 
 #ifdef JS_CODEGEN_X64
     void addq_rr(RegisterID src, RegisterID dst)
     {
         spew("addq       %s, %s", nameIReg(8,src), nameIReg(8,dst));
         m_formatter.oneByteOp64(OP_ADD_GvEv, src, dst);
     }
 
-    void addq_mr(int offset, RegisterID base, RegisterID dst)
+    void addq_mr(int32_t offset, RegisterID base, RegisterID dst)
     {
         spew("addq       " MEM_ob ", %s", ADDR_ob(offset, base), nameIReg(8,dst));
         m_formatter.oneByteOp64(OP_ADD_GvEv, offset, base, dst);
     }
 
     void addq_mr(const void* addr, RegisterID dst)
     {
         spew("addq       %p, %s", addr, nameIReg(8, dst));
         m_formatter.oneByteOp64(OP_ADD_GvEv, addr, dst);
     }
 
-    void addq_ir(int imm, RegisterID dst)
+    void addq_ir(int32_t imm, RegisterID dst)
     {
         spew("addq       $%d, %s", imm, nameIReg(8,dst));
         if (CAN_SIGN_EXTEND_8_32(imm)) {
             m_formatter.oneByteOp64(OP_GROUP1_EvIb, dst, GROUP1_OP_ADD);
-            m_formatter.immediate8(imm);
+            m_formatter.immediate8s(imm);
         } else {
             if (dst == X86Registers::eax)
                 m_formatter.oneByteOp64(OP_ADD_EAXIv);
             else
                 m_formatter.oneByteOp64(OP_GROUP1_EvIz, dst, GROUP1_OP_ADD);
             m_formatter.immediate32(imm);
         }
     }
 
-    void addq_im(int imm, int offset, RegisterID base)
+    void addq_im(int32_t imm, int32_t offset, RegisterID base)
     {
         spew("addq       $%d, " MEM_ob, imm, ADDR_ob(offset, base));
         if (CAN_SIGN_EXTEND_8_32(imm)) {
             m_formatter.oneByteOp64(OP_GROUP1_EvIb, offset, base, GROUP1_OP_ADD);
-            m_formatter.immediate8(imm);
+            m_formatter.immediate8s(imm);
         } else {
             m_formatter.oneByteOp64(OP_GROUP1_EvIz, offset, base, GROUP1_OP_ADD);
             m_formatter.immediate32(imm);
         }
     }
 
-    void addq_im(int imm, const void* addr)
+    void addq_im(int32_t imm, const void* addr)
     {
         spew("addq       $%d, %p", imm, addr);
         if (CAN_SIGN_EXTEND_8_32(imm)) {
             m_formatter.oneByteOp64(OP_GROUP1_EvIb, addr, GROUP1_OP_ADD);
-            m_formatter.immediate8(imm);
+            m_formatter.immediate8s(imm);
         } else {
             m_formatter.oneByteOp64(OP_GROUP1_EvIz, addr, GROUP1_OP_ADD);
             m_formatter.immediate32(imm);
         }
     }
 #endif
-    void addl_im(int imm, const void* addr)
+    void addl_im(int32_t imm, const void* addr)
     {
         spew("addl       $%d, %p", imm, addr);
         if (CAN_SIGN_EXTEND_8_32(imm)) {
             m_formatter.oneByteOp(OP_GROUP1_EvIb, addr, GROUP1_OP_ADD);
-            m_formatter.immediate8(imm);
+            m_formatter.immediate8s(imm);
         } else {
             m_formatter.oneByteOp(OP_GROUP1_EvIz, addr, GROUP1_OP_ADD);
             m_formatter.immediate32(imm);
         }
     }
 
-    void lock_xaddb_rm(RegisterID srcdest, int offset, RegisterID base)
+    void lock_xaddb_rm(RegisterID srcdest, int32_t offset, RegisterID base)
     {
         spew("lock xaddl %s, " MEM_ob, nameIReg(1, srcdest), ADDR_ob(offset, base));
         m_formatter.oneByteOp(PRE_LOCK);
         m_formatter.twoByteOp(OP2_XADD_EbGb, offset, base, srcdest);
     }
 
-    void lock_xaddb_rm(RegisterID srcdest, int offset, RegisterID base, RegisterID index, int scale)
+    void lock_xaddb_rm(RegisterID srcdest, int32_t offset, RegisterID base, RegisterID index, int scale)
     {
         spew("lock xaddl %s, " MEM_obs, nameIReg(1, srcdest), ADDR_obs(offset, base, index, scale));
         m_formatter.oneByteOp(PRE_LOCK);
         m_formatter.twoByteOp(OP2_XADD_EbGb, offset, base, index, scale, srcdest);
     }
 
-    void lock_xaddl_rm(RegisterID srcdest, int offset, RegisterID base)
+    void lock_xaddl_rm(RegisterID srcdest, int32_t offset, RegisterID base)
     {
         spew("lock xaddl %s, " MEM_ob, nameIReg(4,srcdest), ADDR_ob(offset, base));
         m_formatter.oneByteOp(PRE_LOCK);
         m_formatter.twoByteOp(OP2_XADD_EvGv, offset, base, srcdest);
     }
 
-    void lock_xaddl_rm(RegisterID srcdest, int offset, RegisterID base, RegisterID index, int scale)
+    void lock_xaddl_rm(RegisterID srcdest, int32_t offset, RegisterID base, RegisterID index, int scale)
     {
         spew("lock xaddl %s, " MEM_obs, nameIReg(4, srcdest), ADDR_obs(offset, base, index, scale));
         m_formatter.oneByteOp(PRE_LOCK);
         m_formatter.twoByteOp(OP2_XADD_EvGv, offset, base, index, scale, srcdest);
     }
 
     void vpaddd_rr(XMMRegisterID src1, XMMRegisterID src0, XMMRegisterID dst)
     {
         twoByteOpSimd("vpaddd", VEX_PD, OP2_PADDD_VdqWdq, src1, src0, dst);
     }
-    void vpaddd_mr(int offset, RegisterID base, XMMRegisterID src0, XMMRegisterID dst)
+    void vpaddd_mr(int32_t offset, RegisterID base, XMMRegisterID src0, XMMRegisterID dst)
     {
         twoByteOpSimd("vpaddd", VEX_PD, OP2_PADDD_VdqWdq, offset, base, src0, dst);
     }
     void vpaddd_mr(const void* address, XMMRegisterID src0, XMMRegisterID dst)
     {
         twoByteOpSimd("vpaddd", VEX_PD, OP2_PADDD_VdqWdq, address, src0, dst);
     }
 
     void vpsubd_rr(XMMRegisterID src1, XMMRegisterID src0, XMMRegisterID dst)
     {
         twoByteOpSimd("vpsubd", VEX_PD, OP2_PSUBD_VdqWdq, src1, src0, dst);
     }
-    void vpsubd_mr(int offset, RegisterID base, XMMRegisterID src0, XMMRegisterID dst)
+    void vpsubd_mr(int32_t offset, RegisterID base, XMMRegisterID src0, XMMRegisterID dst)
     {
         twoByteOpSimd("vpsubd", VEX_PD, OP2_PSUBD_VdqWdq, offset, base, src0, dst);
     }
     void vpsubd_mr(const void* address, XMMRegisterID src0, XMMRegisterID dst)
     {
         twoByteOpSimd("vpsubd", VEX_PD, OP2_PSUBD_VdqWdq, address, src0, dst);
     }
 
     void vpmuludq_rr(XMMRegisterID src1, XMMRegisterID src0, XMMRegisterID dst)
     {
         twoByteOpSimd("vpmuludq", VEX_PD, OP2_PMULUDQ_VdqWdq, src1, src0, dst);
     }
-    void vpmuludq_mr(int offset, RegisterID base, XMMRegisterID src0, XMMRegisterID dst)
+    void vpmuludq_mr(int32_t offset, RegisterID base, XMMRegisterID src0, XMMRegisterID dst)
     {
         twoByteOpSimd("vpmuludq", VEX_PD, OP2_PMULUDQ_VdqWdq, offset, base, src0, dst);
     }
 
     void vpmulld_rr(XMMRegisterID src1, XMMRegisterID src0, XMMRegisterID dst)
     {
         threeByteOpSimd("vpmulld", VEX_PD, OP3_PMULLD_VdqWdq, ESCAPE_PMULLD, src1, src0, dst);
     }
-    void vpmulld_mr(int offset, RegisterID base, XMMRegisterID src0, XMMRegisterID dst)
+    void vpmulld_mr(int32_t offset, RegisterID base, XMMRegisterID src0, XMMRegisterID dst)
     {
         threeByteOpSimd("vpmulld", VEX_PD, OP3_PMULLD_VdqWdq, ESCAPE_PMULLD, offset, base, src0, dst);
     }
     void vpmulld_mr(const void* address, XMMRegisterID src0, XMMRegisterID dst)
     {
         threeByteOpSimd("vpmulld", VEX_PD, OP3_PMULLD_VdqWdq, ESCAPE_PMULLD, address, src0, dst);
     }
 
     void vaddps_rr(XMMRegisterID src1, XMMRegisterID src0, XMMRegisterID dst)
     {
         twoByteOpSimd("vaddps", VEX_PS, OP2_ADDPS_VpsWps, src1, src0, dst);
     }
-    void vaddps_mr(int offset, RegisterID base, XMMRegisterID src0, XMMRegisterID dst)
+    void vaddps_mr(int32_t offset, RegisterID base, XMMRegisterID src0, XMMRegisterID dst)
     {
         twoByteOpSimd("vaddps", VEX_PS, OP2_ADDPS_VpsWps, offset, base, src0, dst);
     }
     void vaddps_mr(const void* address, XMMRegisterID src0, XMMRegisterID dst)
     {
         twoByteOpSimd("vaddps", VEX_PS, OP2_ADDPS_VpsWps, address, src0, dst);
     }
 
     void vsubps_rr(XMMRegisterID src1, XMMRegisterID src0, XMMRegisterID dst)
     {
         twoByteOpSimd("vsubps", VEX_PS, OP2_SUBPS_VpsWps, src1, src0, dst);
     }
-    void vsubps_mr(int offset, RegisterID base, XMMRegisterID src0, XMMRegisterID dst)
+    void vsubps_mr(int32_t offset, RegisterID base, XMMRegisterID src0, XMMRegisterID dst)
     {
         twoByteOpSimd("vsubps", VEX_PS, OP2_SUBPS_VpsWps, offset, base, src0, dst);
     }
     void vsubps_mr(const void* address, XMMRegisterID src0, XMMRegisterID dst)
     {
         twoByteOpSimd("vsubps", VEX_PS, OP2_SUBPS_VpsWps, address, src0, dst);
     }
 
     void vmulps_rr(XMMRegisterID src1, XMMRegisterID src0, XMMRegisterID dst)
     {
         twoByteOpSimd("vmulps", VEX_PS, OP2_MULPS_VpsWps, src1, src0, dst);
     }
-    void vmulps_mr(int offset, RegisterID base, XMMRegisterID src0, XMMRegisterID dst)
+    void vmulps_mr(int32_t offset, RegisterID base, XMMRegisterID src0, XMMRegisterID dst)
     {
         twoByteOpSimd("vmulps", VEX_PS, OP2_MULPS_VpsWps, offset, base, src0, dst);
     }
     void vmulps_mr(const void* address, XMMRegisterID src0, XMMRegisterID dst)
     {
         twoByteOpSimd("vmulps", VEX_PS, OP2_MULPS_VpsWps, address, src0, dst);
     }
 
     void vdivps_rr(XMMRegisterID src1, XMMRegisterID src0, XMMRegisterID dst)
     {
         twoByteOpSimd("vdivps", VEX_PS, OP2_DIVPS_VpsWps, src1, src0, dst);
     }
-    void vdivps_mr(int offset, RegisterID base, XMMRegisterID src0, XMMRegisterID dst)
+    void vdivps_mr(int32_t offset, RegisterID base, XMMRegisterID src0, XMMRegisterID dst)
     {
         twoByteOpSimd("vdivps", VEX_PS, OP2_DIVPS_VpsWps, offset, base, src0, dst);
     }
     void vdivps_mr(const void* address, XMMRegisterID src0, XMMRegisterID dst)
     {
         twoByteOpSimd("vdivps", VEX_PS, OP2_DIVPS_VpsWps, address, src0, dst);
     }
 
     void vmaxps_rr(XMMRegisterID src1, XMMRegisterID src0, XMMRegisterID dst)
     {
         twoByteOpSimd("vmaxps", VEX_PS, OP2_MAXPS_VpsWps, src1, src0, dst);
     }
-    void vmaxps_mr(int offset, RegisterID base, XMMRegisterID src0, XMMRegisterID dst)
+    void vmaxps_mr(int32_t offset, RegisterID base, XMMRegisterID src0, XMMRegisterID dst)
     {
         twoByteOpSimd("vmaxps", VEX_PS, OP2_MAXPS_VpsWps, offset, base, src0, dst);
     }
     void vmaxps_mr(const void* address, XMMRegisterID src0, XMMRegisterID dst)
     {
         twoByteOpSimd("vmaxps", VEX_PS, OP2_MAXPS_VpsWps, address, src0, dst);
     }
 
     void vminps_rr(XMMRegisterID src1, XMMRegisterID src0, XMMRegisterID dst)
     {
         twoByteOpSimd("vminps", VEX_PS, OP2_MINPS_VpsWps, src1, src0, dst);
     }
-    void vminps_mr(int offset, RegisterID base, XMMRegisterID src0, XMMRegisterID dst)
+    void vminps_mr(int32_t offset, RegisterID base, XMMRegisterID src0, XMMRegisterID dst)
     {
         twoByteOpSimd("vminps", VEX_PS, OP2_MINPS_VpsWps, offset, base, src0, dst);
     }
     void vminps_mr(const void* address, XMMRegisterID src0, XMMRegisterID dst)
     {
         twoByteOpSimd("vminps", VEX_PS, OP2_MINPS_VpsWps, address, src0, dst);
     }
 
     void andl_rr(RegisterID src, RegisterID dst)
     {
         spew("andl       %s, %s", nameIReg(4,src), nameIReg(4,dst));
         m_formatter.oneByteOp(OP_AND_GvEv, src, dst);
     }
 
-    void andl_mr(int offset, RegisterID base, RegisterID dst)
+    void andl_mr(int32_t offset, RegisterID base, RegisterID dst)
     {
         spew("andl       " MEM_ob ", %s", ADDR_ob(offset, base), nameIReg(4,dst));
         m_formatter.oneByteOp(OP_AND_GvEv, offset, base, dst);
     }
 
-    void andl_rm(RegisterID src, int offset, RegisterID base)
+    void andl_rm(RegisterID src, int32_t offset, RegisterID base)
     {
         spew("andl       %s, " MEM_ob, nameIReg(4,src), ADDR_ob(offset, base));
         m_formatter.oneByteOp(OP_AND_EvGv, offset, base, src);
     }
 
-    void andl_ir(int imm, RegisterID dst)
+    void andl_ir(int32_t imm, RegisterID dst)
     {
         spew("andl       $0x%x, %s", imm, nameIReg(4,dst));
         if (CAN_SIGN_EXTEND_8_32(imm)) {
             m_formatter.oneByteOp(OP_GROUP1_EvIb, dst, GROUP1_OP_AND);
-            m_formatter.immediate8(imm);
+            m_formatter.immediate8s(imm);
         } else {
             if (dst == X86Registers::eax)
                 m_formatter.oneByteOp(OP_AND_EAXIv);
             else
                 m_formatter.oneByteOp(OP_GROUP1_EvIz, dst, GROUP1_OP_AND);
             m_formatter.immediate32(imm);
         }
     }
 
-    void andl_im(int imm, int offset, RegisterID base)
+    void andl_im(int32_t imm, int32_t offset, RegisterID base)
     {
         spew("andl       $0x%x, " MEM_ob, imm, ADDR_ob(offset, base));
         if (CAN_SIGN_EXTEND_8_32(imm)) {
             m_formatter.oneByteOp(OP_GROUP1_EvIb, offset, base, GROUP1_OP_AND);
-            m_formatter.immediate8(imm);
+            m_formatter.immediate8s(imm);
         } else {
             m_formatter.oneByteOp(OP_GROUP1_EvIz, offset, base, GROUP1_OP_AND);
             m_formatter.immediate32(imm);
         }
     }
 
 #ifdef JS_CODEGEN_X64
     void andq_rr(RegisterID src, RegisterID dst)
     {
         spew("andq       %s, %s", nameIReg(8,src), nameIReg(8,dst));
         m_formatter.oneByteOp64(OP_AND_GvEv, src, dst);
     }
 
-    void andq_mr(int offset, RegisterID base, RegisterID dst)
+    void andq_mr(int32_t offset, RegisterID base, RegisterID dst)
     {
         spew("andq       " MEM_ob ", %s", ADDR_ob(offset, base), nameIReg(8,dst));
         m_formatter.oneByteOp64(OP_AND_GvEv, offset, base, dst);
     }
 
-    void andq_mr(int offset, RegisterID base, RegisterID index, int scale, RegisterID dst)
+    void andq_mr(int32_t offset, RegisterID base, RegisterID index, int scale, RegisterID dst)
     {
         spew("andq       " MEM_obs ", %s", ADDR_obs(offset, base, index, scale), nameIReg(8,dst));
         m_formatter.oneByteOp64(OP_AND_GvEv, offset, base, index, scale, dst);
     }
 
     void andq_mr(const void *addr, RegisterID dst)
     {
         spew("andq       %p, %s", addr, nameIReg(8,dst));
         m_formatter.oneByteOp64(OP_AND_GvEv, addr, dst);
     }
 
-    void orq_mr(int offset, RegisterID base, RegisterID dst)
+    void orq_mr(int32_t offset, RegisterID base, RegisterID dst)
     {
         spew("orq        " MEM_ob ", %s", ADDR_ob(offset, base), nameIReg(8,dst));
         m_formatter.oneByteOp64(OP_OR_GvEv, offset, base, dst);
     }
 
     void orq_mr(const void* addr, RegisterID dst)
     {
         spew("orq        %p, %s", addr, nameIReg(8, dst));
         m_formatter.oneByteOp64(OP_OR_GvEv, addr, dst);
     }
 
-    void andq_ir(int imm, RegisterID dst)
+    void andq_ir(int32_t imm, RegisterID dst)
     {
         spew("andq       $0x%" PRIx64 ", %s", int64_t(imm), nameIReg(8,dst));
         if (CAN_SIGN_EXTEND_8_32(imm)) {
             m_formatter.oneByteOp64(OP_GROUP1_EvIb, dst, GROUP1_OP_AND);
-            m_formatter.immediate8(imm);
+            m_formatter.immediate8s(imm);
         } else {
             if (dst == X86Registers::eax)
                 m_formatter.oneByteOp64(OP_AND_EAXIv);
             else
                 m_formatter.oneByteOp64(OP_GROUP1_EvIz, dst, GROUP1_OP_AND);
             m_formatter.immediate32(imm);
         }
     }
 #else
-    void andl_im(int imm, const void* addr)
+    void andl_im(int32_t imm, const void* addr)
     {
         spew("andl       $0x%x, %p", imm, addr);
         if (CAN_SIGN_EXTEND_8_32(imm)) {
             m_formatter.oneByteOp(OP_GROUP1_EvIb, addr, GROUP1_OP_AND);
-            m_formatter.immediate8(imm);
+            m_formatter.immediate8s(imm);
         } else {
             m_formatter.oneByteOp(OP_GROUP1_EvIz, addr, GROUP1_OP_AND);
             m_formatter.immediate32(imm);
         }
     }
 #endif
 
-    void fld_m(int offset, RegisterID base)
+    void fld_m(int32_t offset, RegisterID base)
     {
         spew("fld        " MEM_ob, ADDR_ob(offset, base));
         m_formatter.oneByteOp(OP_FPU6, offset, base, FPU6_OP_FLD);
     }
-    void fld32_m(int offset, RegisterID base)
+    void fld32_m(int32_t offset, RegisterID base)
     {
         spew("fld        " MEM_ob, ADDR_ob(offset, base));
         m_formatter.oneByteOp(OP_FPU6_F32, offset, base, FPU6_OP_FLD);
     }
-    void fisttp_m(int offset, RegisterID base)
+    void fisttp_m(int32_t offset, RegisterID base)
     {
         spew("fisttp     " MEM_ob, ADDR_ob(offset, base));
         m_formatter.oneByteOp(OP_FPU6, offset, base, FPU6_OP_FISTTP);
     }
-    void fstp_m(int offset, RegisterID base)
+    void fstp_m(int32_t offset, RegisterID base)
     {
         spew("fstp       " MEM_ob, ADDR_ob(offset, base));
         m_formatter.oneByteOp(OP_FPU6, offset, base, FPU6_OP_FSTP);
     }
-    void fstp32_m(int offset, RegisterID base)
+    void fstp32_m(int32_t offset, RegisterID base)
     {
         spew("fstp32       " MEM_ob, ADDR_ob(offset, base));
         m_formatter.oneByteOp(OP_FPU6_F32, offset, base, FPU6_OP_FSTP);
     }
 
     void negl_r(RegisterID dst)
     {
         spew("negl       %s", nameIReg(4,dst));
         m_formatter.oneByteOp(OP_GROUP3_Ev, dst, GROUP3_OP_NEG);
     }
 
-    void negl_m(int offset, RegisterID base)
+    void negl_m(int32_t offset, RegisterID base)
     {
         FIXME_INSN_PRINTING;
         m_formatter.oneByteOp(OP_GROUP3_Ev, offset, base, GROUP3_OP_NEG);
     }
 
     void notl_r(RegisterID dst)
     {
         spew("notl       %s", nameIReg(4,dst));
         m_formatter.oneByteOp(OP_GROUP3_Ev, dst, GROUP3_OP_NOT);
     }
 
-    void notl_m(int offset, RegisterID base)
+    void notl_m(int32_t offset, RegisterID base)
     {
         FIXME_INSN_PRINTING;
         m_formatter.oneByteOp(OP_GROUP3_Ev, offset, base, GROUP3_OP_NOT);
     }
 
     void orl_rr(RegisterID src, RegisterID dst)
     {
         spew("orl        %s, %s", nameIReg(4,src), nameIReg(4,dst));
         m_formatter.oneByteOp(OP_OR_GvEv, src, dst);
     }
 
-    void orl_mr(int offset, RegisterID base, RegisterID dst)
+    void orl_mr(int32_t offset, RegisterID base, RegisterID dst)
     {
         spew("orl        " MEM_ob ", %s", ADDR_ob(offset, base), nameIReg(4,dst));
         m_formatter.oneByteOp(OP_OR_GvEv, offset, base, dst);
     }
 
-    void orl_rm(RegisterID src, int offset, RegisterID base)
+    void orl_rm(RegisterID src, int32_t offset, RegisterID base)
     {
         spew("orl        %s, " MEM_ob, nameIReg(4,src), ADDR_ob(offset, base));
         m_formatter.oneByteOp(OP_OR_EvGv, offset, base, src);
     }
 
-    void orl_ir(int imm, RegisterID dst)
+    void orl_ir(int32_t imm, RegisterID dst)
     {
         spew("orl        $0x%x, %s", imm, nameIReg(4,dst));
         if (CAN_SIGN_EXTEND_8_32(imm)) {
             m_formatter.oneByteOp(OP_GROUP1_EvIb, dst, GROUP1_OP_OR);
-            m_formatter.immediate8(imm);
+            m_formatter.immediate8s(imm);
         } else {
             if (dst == X86Registers::eax)
                 m_formatter.oneByteOp(OP_OR_EAXIv);
             else
                 m_formatter.oneByteOp(OP_GROUP1_EvIz, dst, GROUP1_OP_OR);
             m_formatter.immediate32(imm);
         }
     }
 
-    void orl_im(int imm, int offset, RegisterID base)
+    void orl_im(int32_t imm, int32_t offset, RegisterID base)
     {
         spew("orl        $0x%x, " MEM_ob, imm, ADDR_ob(offset, base));
         if (CAN_SIGN_EXTEND_8_32(imm)) {
             m_formatter.oneByteOp(OP_GROUP1_EvIb, offset, base, GROUP1_OP_OR);
-            m_formatter.immediate8(imm);
+            m_formatter.immediate8s(imm);
         } else {
             m_formatter.oneByteOp(OP_GROUP1_EvIz, offset, base, GROUP1_OP_OR);
             m_formatter.immediate32(imm);
         }
     }
 
 #ifdef JS_CODEGEN_X64
     void negq_r(RegisterID dst)
@@ -1142,304 +1144,310 @@ public:
     }
 
     void orq_rr(RegisterID src, RegisterID dst)
     {
         spew("orq        %s, %s", nameIReg(8,src), nameIReg(8,dst));
         m_formatter.oneByteOp64(OP_OR_GvEv, src, dst);
     }
 
-    void orq_ir(int imm, RegisterID dst)
+    void orq_ir(int32_t imm, RegisterID dst)
     {
         spew("orq        $0x%" PRIx64 ", %s", int64_t(imm), nameIReg(8,dst));
         if (CAN_SIGN_EXTEND_8_32(imm)) {
             m_formatter.oneByteOp64(OP_GROUP1_EvIb, dst, GROUP1_OP_OR);
-            m_formatter.immediate8(imm);
+            m_formatter.immediate8s(imm);
         } else {
             if (dst == X86Registers::eax)
                 m_formatter.oneByteOp64(OP_OR_EAXIv);
             else
                 m_formatter.oneByteOp64(OP_GROUP1_EvIz, dst, GROUP1_OP_OR);
             m_formatter.immediate32(imm);
         }
     }
 
     void notq_r(RegisterID dst)
     {
         spew("notq       %s", nameIReg(8,dst));
         m_formatter.oneByteOp64(OP_GROUP3_Ev, dst, GROUP3_OP_NOT);
     }
 #else
-    void orl_im(int imm, const void* addr)
+    void orl_im(int32_t imm, const void* addr)
     {
         FIXME_INSN_PRINTING;
         if (CAN_SIGN_EXTEND_8_32(imm)) {
             m_formatter.oneByteOp(OP_GROUP1_EvIb, addr, GROUP1_OP_OR);
-            m_formatter.immediate8(imm);
+            m_formatter.immediate8s(imm);
         } else {
             m_formatter.oneByteOp(OP_GROUP1_EvIz, addr, GROUP1_OP_OR);
             m_formatter.immediate32(imm);
         }
     }
 #endif
 
     void subl_rr(RegisterID src, RegisterID dst)
     {
         spew("subl       %s, %s", nameIReg(4,src), nameIReg(4,dst));
         m_formatter.oneByteOp(OP_SUB_GvEv, src, dst);
     }
 
-    void subl_mr(int offset, RegisterID base, RegisterID dst)
+    void subl_mr(int32_t offset, RegisterID base, RegisterID dst)
     {
         spew("subl       " MEM_ob ", %s", ADDR_ob(offset, base), nameIReg(4,dst));
         m_formatter.oneByteOp(OP_SUB_GvEv, offset, base, dst);
     }
 
-    void subl_rm(RegisterID src, int offset, RegisterID base)
+    void subl_rm(RegisterID src, int32_t offset, RegisterID base)
     {
         spew("subl       %s, " MEM_ob, nameIReg(4,src), ADDR_ob(offset, base));
         m_formatter.oneByteOp(OP_SUB_EvGv, offset, base, src);
     }
 
-    void subl_ir(int imm, RegisterID dst)
+    void subl_ir(int32_t imm, RegisterID dst)
     {
         spew("subl       $%d, %s", imm, nameIReg(4, dst));
         if (CAN_SIGN_EXTEND_8_32(imm)) {
             m_formatter.oneByteOp(OP_GROUP1_EvIb, dst, GROUP1_OP_SUB);
-            m_formatter.immediate8(imm);
+            m_formatter.immediate8s(imm);
         } else {
             if (dst == X86Registers::eax)
                 m_formatter.oneByteOp(OP_SUB_EAXIv);
             else
                 m_formatter.oneByteOp(OP_GROUP1_EvIz, dst, GROUP1_OP_SUB);
             m_formatter.immediate32(imm);
         }
     }
 
-    void subl_im(int imm, int offset, RegisterID base)
+    void subl_im(int32_t imm, int32_t offset, RegisterID base)
     {
         spew("subl       $%d, " MEM_ob, imm, ADDR_ob(offset, base));
         if (CAN_SIGN_EXTEND_8_32(imm)) {
             m_formatter.oneByteOp(OP_GROUP1_EvIb, offset, base, GROUP1_OP_SUB);
-            m_formatter.immediate8(imm);
+            m_formatter.immediate8s(imm);
         } else {
             m_formatter.oneByteOp(OP_GROUP1_EvIz, offset, base, GROUP1_OP_SUB);
             m_formatter.immediate32(imm);
         }
     }
 
 #ifdef JS_CODEGEN_X64
     void subq_rr(RegisterID src, RegisterID dst)
     {
         spew("subq       %s, %s", nameIReg(8,src), nameIReg(8,dst));
         m_formatter.oneByteOp64(OP_SUB_GvEv, src, dst);
     }
 
-    void subq_rm(RegisterID src, int offset, RegisterID base)
+    void subq_rm(RegisterID src, int32_t offset, RegisterID base)
     {
         spew("subq       %s, " MEM_ob, nameIReg(8,src), ADDR_ob(offset, base));
         m_formatter.oneByteOp64(OP_SUB_EvGv, offset, base, src);
     }
 
-    void subq_mr(int offset, RegisterID base, RegisterID dst)
+    void subq_mr(int32_t offset, RegisterID base, RegisterID dst)
     {
         spew("subq       " MEM_ob ", %s", ADDR_ob(offset, base), nameIReg(8,dst));
         m_formatter.oneByteOp64(OP_SUB_GvEv, offset, base, dst);
     }
 
     void subq_mr(const void* addr, RegisterID dst)
     {
         spew("subq       %p, %s", addr, nameIReg(8, dst));
         m_formatter.oneByteOp64(OP_SUB_GvEv, addr, dst);
     }
 
-    void subq_ir(int imm, RegisterID dst)
+    void subq_ir(int32_t imm, RegisterID dst)
     {
         spew("subq       $%d, %s", imm, nameIReg(8,dst));
         if (CAN_SIGN_EXTEND_8_32(imm)) {
             m_formatter.oneByteOp64(OP_GROUP1_EvIb, dst, GROUP1_OP_SUB);
-            m_formatter.immediate8(imm);
+            m_formatter.immediate8s(imm);
         } else {
             if (dst == X86Registers::eax)
                 m_formatter.oneByteOp64(OP_SUB_EAXIv);
             else
                 m_formatter.oneByteOp64(OP_GROUP1_EvIz, dst, GROUP1_OP_SUB);
             m_formatter.immediate32(imm);
         }
     }
 #else
-    void subl_im(int imm, const void* addr)
+    void subl_im(int32_t imm, const void* addr)
     {
         FIXME_INSN_PRINTING;
         if (CAN_SIGN_EXTEND_8_32(imm)) {
             m_formatter.oneByteOp(OP_GROUP1_EvIb, addr, GROUP1_OP_SUB);
-            m_formatter.immediate8(imm);
+            m_formatter.immediate8s(imm);
         } else {
             m_formatter.oneByteOp(OP_GROUP1_EvIz, addr, GROUP1_OP_SUB);
             m_formatter.immediate32(imm);
         }
     }
 #endif
 
     void xorl_rr(RegisterID src, RegisterID dst)
     {
         spew("xorl       %s, %s", nameIReg(4,src), nameIReg(4,dst));
         m_formatter.oneByteOp(OP_XOR_GvEv, src, dst);
     }
 
-    void xorl_mr(int offset, RegisterID base, RegisterID dst)
+    void xorl_mr(int32_t offset, RegisterID base, RegisterID dst)
     {
         spew("xorl       " MEM_ob ", %s", ADDR_ob(offset, base), nameIReg(4,dst));
         m_formatter.oneByteOp(OP_XOR_GvEv, offset, base, dst);
     }
 
-    void xorl_rm(RegisterID src, int offset, RegisterID base)
+    void xorl_rm(RegisterID src, int32_t offset, RegisterID base)
     {
         spew("xorl       %s, " MEM_ob, nameIReg(4,src), ADDR_ob(offset, base));
         m_formatter.oneByteOp(OP_XOR_EvGv, offset, base, src);
     }
 
-    void xorl_im(int imm, int offset, RegisterID base)
+    void xorl_im(int32_t imm, int32_t offset, RegisterID base)
     {
         spew("xorl       $0x%x, " MEM_ob, imm, ADDR_ob(offset, base));
         if (CAN_SIGN_EXTEND_8_32(imm)) {
             m_formatter.oneByteOp(OP_GROUP1_EvIb, offset, base, GROUP1_OP_XOR);
-            m_formatter.immediate8(imm);
+            m_formatter.immediate8s(imm);
         } else {
             m_formatter.oneByteOp(OP_GROUP1_EvIz, offset, base, GROUP1_OP_XOR);
             m_formatter.immediate32(imm);
         }
     }
 
-    void xorl_ir(int imm, RegisterID dst)
+    void xorl_ir(int32_t imm, RegisterID dst)
     {
         spew("xorl       $%d, %s", imm, nameIReg(4,dst));
         if (CAN_SIGN_EXTEND_8_32(imm)) {
             m_formatter.oneByteOp(OP_GROUP1_EvIb, dst, GROUP1_OP_XOR);
-            m_formatter.immediate8(imm);
+            m_formatter.immediate8s(imm);
         } else {
             if (dst == X86Registers::eax)
                 m_formatter.oneByteOp(OP_XOR_EAXIv);
             else
                 m_formatter.oneByteOp(OP_GROUP1_EvIz, dst, GROUP1_OP_XOR);
             m_formatter.immediate32(imm);
         }
     }
 
 #ifdef JS_CODEGEN_X64
     void xorq_rr(RegisterID src, RegisterID dst)
     {
         spew("xorq       %s, %s", nameIReg(8,src), nameIReg(8, dst));
         m_formatter.oneByteOp64(OP_XOR_GvEv, src, dst);
     }
 
-    void xorq_ir(int imm, RegisterID dst)
+    void xorq_ir(int32_t imm, RegisterID dst)
     {
         spew("xorq       $0x%" PRIx64 ", %s", int64_t(imm), nameIReg(8,dst));
         if (CAN_SIGN_EXTEND_8_32(imm)) {
             m_formatter.oneByteOp64(OP_GROUP1_EvIb, dst, GROUP1_OP_XOR);
-            m_formatter.immediate8(imm);
+            m_formatter.immediate8s(imm);
         } else {
             if (dst == X86Registers::eax)
                 m_formatter.oneByteOp64(OP_XOR_EAXIv);
             else
                 m_formatter.oneByteOp64(OP_GROUP1_EvIz, dst, GROUP1_OP_XOR);
             m_formatter.immediate32(imm);
         }
     }
 #endif
 
-    void sarl_i8r(int imm, RegisterID dst)
-    {
+    void sarl_ir(int32_t imm, RegisterID dst)
+    {
+        MOZ_ASSERT(imm < 32);
         spew("sarl       $%d, %s", imm, nameIReg(4, dst));
         if (imm == 1)
             m_formatter.oneByteOp(OP_GROUP2_Ev1, dst, GROUP2_OP_SAR);
         else {
             m_formatter.oneByteOp(OP_GROUP2_EvIb, dst, GROUP2_OP_SAR);
-            m_formatter.immediate8(imm);
+            m_formatter.immediate8u(imm);
         }
     }
 
     void sarl_CLr(RegisterID dst)
     {
         spew("sarl       %%cl, %s", nameIReg(4, dst));
         m_formatter.oneByteOp(OP_GROUP2_EvCL, dst, GROUP2_OP_SAR);
     }
 
-    void shrl_i8r(int imm, RegisterID dst)
-    {
+    void shrl_ir(int32_t imm, RegisterID dst)
+    {
+        MOZ_ASSERT(imm < 32);
         spew("shrl       $%d, %s", imm, nameIReg(4, dst));
         if (imm == 1)
             m_formatter.oneByteOp(OP_GROUP2_Ev1, dst, GROUP2_OP_SHR);
         else {
             m_formatter.oneByteOp(OP_GROUP2_EvIb, dst, GROUP2_OP_SHR);
-            m_formatter.immediate8(imm);
+            m_formatter.immediate8u(imm);
         }
     }
 
     void shrl_CLr(RegisterID dst)
     {
         spew("shrl       %%cl, %s", nameIReg(4, dst));
         m_formatter.oneByteOp(OP_GROUP2_EvCL, dst, GROUP2_OP_SHR);
     }
 
-    void shll_i8r(int imm, RegisterID dst)
-    {
+    void shll_ir(int32_t imm, RegisterID dst)
+    {
+        MOZ_ASSERT(imm < 32);
         spew("shll       $%d, %s", imm, nameIReg(4, dst));
         if (imm == 1)
             m_formatter.oneByteOp(OP_GROUP2_Ev1, dst, GROUP2_OP_SHL);
         else {
             m_formatter.oneByteOp(OP_GROUP2_EvIb, dst, GROUP2_OP_SHL);
-            m_formatter.immediate8(imm);
+            m_formatter.immediate8u(imm);
         }
     }
 
     void shll_CLr(RegisterID dst)
     {
         spew("shll       %%cl, %s", nameIReg(4, dst));
         m_formatter.oneByteOp(OP_GROUP2_EvCL, dst, GROUP2_OP_SHL);
     }
 
 #ifdef JS_CODEGEN_X64
     void sarq_CLr(RegisterID dst)
     {
         FIXME_INSN_PRINTING;
         m_formatter.oneByteOp64(OP_GROUP2_EvCL, dst, GROUP2_OP_SAR);
     }
 
-    void sarq_i8r(int imm, RegisterID dst)
-    {
+    void sarq_ir(int32_t imm, RegisterID dst)
+    {
+        MOZ_ASSERT(imm < 64);
         spew("sarq       $%d, %s", imm, nameIReg(8, dst));
         if (imm == 1)
             m_formatter.oneByteOp64(OP_GROUP2_Ev1, dst, GROUP2_OP_SAR);
         else {
             m_formatter.oneByteOp64(OP_GROUP2_EvIb, dst, GROUP2_OP_SAR);
-            m_formatter.immediate8(imm);
+            m_formatter.immediate8u(imm);
         }
     }
 
-    void shlq_i8r(int imm, RegisterID dst)
-    {
+    void shlq_ir(int32_t imm, RegisterID dst)
+    {
+        MOZ_ASSERT(imm < 64);
         spew("shlq       $%d, %s", imm, nameIReg(8, dst));
         if (imm == 1)
             m_formatter.oneByteOp64(OP_GROUP2_Ev1, dst, GROUP2_OP_SHL);
         else {
             m_formatter.oneByteOp64(OP_GROUP2_EvIb, dst, GROUP2_OP_SHL);
-            m_formatter.immediate8(imm);
+            m_formatter.immediate8u(imm);
         }
     }
 
-    void shrq_i8r(int imm, RegisterID dst)
-    {
+    void shrq_ir(int32_t imm, RegisterID dst)
+    {
+        MOZ_ASSERT(imm < 64);
         spew("shrq       $%d, %s", imm, nameIReg(8, dst));
         if (imm == 1)
             m_formatter.oneByteOp64(OP_GROUP2_Ev1, dst, GROUP2_OP_SHR);
         else {
             m_formatter.oneByteOp64(OP_GROUP2_EvIb, dst, GROUP2_OP_SHR);
-            m_formatter.immediate8(imm);
+            m_formatter.immediate8u(imm);
         }
     }
 #endif
 
     void bsr_rr(RegisterID src, RegisterID dst)
     {
         spew("bsr        %s, %s", nameIReg(4, src), nameIReg(4, dst));
         m_formatter.twoByteOp(OP2_BSR_GvEv, src, dst);
@@ -1452,28 +1460,28 @@ public:
     }
 
     void imull_r(RegisterID multiplier)
     {
         spew("imull      %s", nameIReg(4, multiplier));
         m_formatter.oneByteOp(OP_GROUP3_Ev, multiplier, GROUP3_OP_IMUL);
     }
 
-    void imull_mr(int offset, RegisterID base, RegisterID dst)
+    void imull_mr(int32_t offset, RegisterID base, RegisterID dst)
     {
         spew("imull      " MEM_ob ", %s", ADDR_ob(offset, base), nameIReg(4,dst));
         m_formatter.twoByteOp(OP2_IMUL_GvEv, offset, base, dst);
     }
 
     void imull_ir(int32_t value, RegisterID src, RegisterID dst)
     {
         spew("imull      $%d, %s, %s", value, nameIReg(4, src), nameIReg(4, dst));
         if (CAN_SIGN_EXTEND_8_32(value)) {
             m_formatter.oneByteOp(OP_IMUL_GvEvIb, src, dst);
-            m_formatter.immediate8(value);
+            m_formatter.immediate8s(value);
         } else {
             m_formatter.oneByteOp(OP_IMUL_GvEvIz, src, dst);
             m_formatter.immediate32(value);
         }
     }
 
     void idivl_r(RegisterID divisor)
     {
@@ -1493,82 +1501,82 @@ public:
         m_formatter.oneByteOp(PRE_LOCK);
     }
 
     void prefix_16_for_32()
     {
         m_formatter.prefix(PRE_OPERAND_SIZE);
     }
 
-    void incl_m32(int offset, RegisterID base)
+    void incl_m32(int32_t offset, RegisterID base)
     {
         spew("incl       " MEM_ob, ADDR_ob(offset, base));
         m_formatter.oneByteOp(OP_GROUP5_Ev, offset, base, GROUP5_OP_INC);
     }
 
-    void decl_m32(int offset, RegisterID base)
+    void decl_m32(int32_t offset, RegisterID base)
     {
         spew("decl       " MEM_ob, ADDR_ob(offset, base));
         m_formatter.oneByteOp(OP_GROUP5_Ev, offset, base, GROUP5_OP_DEC);
     }
 
     // Note that CMPXCHG performs comparison against REG = %al/%ax/%eax.
     // If %REG == [%base+offset], then %src -> [%base+offset].
     // Otherwise, [%base+offset] -> %REG.
     // For the 8-bit operations src must also be an 8-bit register.
 
-    void cmpxchg8(RegisterID src, int offset, RegisterID base)
+    void cmpxchg8(RegisterID src, int32_t offset, RegisterID base)
     {
         spew("cmpxchg8   %s, " MEM_ob, nameIReg(src), ADDR_ob(offset, base));
         m_formatter.twoByteOp(OP2_CMPXCHG_GvEb, offset, base, src);
     }
-    void cmpxchg8(RegisterID src, int offset, RegisterID base, RegisterID index, int scale)
+    void cmpxchg8(RegisterID src, int32_t offset, RegisterID base, RegisterID index, int scale)
     {
         spew("cmpxchg8   %s, " MEM_obs, nameIReg(src), ADDR_obs(offset, base, index, scale));
         m_formatter.twoByteOp(OP2_CMPXCHG_GvEb, offset, base, index, scale, src);
     }
-    void cmpxchg16(RegisterID src, int offset, RegisterID base)
+    void cmpxchg16(RegisterID src, int32_t offset, RegisterID base)
     {
         spew("cmpxchg16  %s, " MEM_ob, nameIReg(src), ADDR_ob(offset, base));
         m_formatter.prefix(PRE_OPERAND_SIZE);
         m_formatter.twoByteOp(OP2_CMPXCHG_GvEw, offset, base, src);
     }
-    void cmpxchg16(RegisterID src, int offset, RegisterID base, RegisterID index, int scale)
+    void cmpxchg16(RegisterID src, int32_t offset, RegisterID base, RegisterID index, int scale)
     {
         spew("cmpxchg16  %s, " MEM_obs, nameIReg(src), ADDR_obs(offset, base, index, scale));
         m_formatter.prefix(PRE_OPERAND_SIZE);
         m_formatter.twoByteOp(OP2_CMPXCHG_GvEw, offset, base, index, scale, src);
     }
-    void cmpxchg32(RegisterID src, int offset, RegisterID base)
+    void cmpxchg32(RegisterID src, int32_t offset, RegisterID base)
     {
         spew("cmpxchg32  %s, " MEM_ob, nameIReg(src), ADDR_ob(offset, base));
         m_formatter.twoByteOp(OP2_CMPXCHG_GvEw, offset, base, src);
     }
-    void cmpxchg32(RegisterID src, int offset, RegisterID base, RegisterID index, int scale)
+    void cmpxchg32(RegisterID src, int32_t offset, RegisterID base, RegisterID index, int scale)
     {
         spew("cmpxchg32  %s, " MEM_obs, nameIReg(src), ADDR_obs(offset, base, index, scale));
         m_formatter.twoByteOp(OP2_CMPXCHG_GvEw, offset, base, index, scale, src);
     }
 
 
     // Comparisons:
 
     void cmpl_rr(RegisterID rhs, RegisterID lhs)
     {
         spew("cmpl       %s, %s", nameIReg(4, rhs), nameIReg(4, lhs));
         m_formatter.oneByteOp(OP_CMP_GvEv, rhs, lhs);
     }
 
-    void cmpl_rm(RegisterID rhs, int offset, RegisterID base)
+    void cmpl_rm(RegisterID rhs, int32_t offset, RegisterID base)
     {
         spew("cmpl       %s, " MEM_ob, nameIReg(4, rhs), ADDR_ob(offset, base));
         m_formatter.oneByteOp(OP_CMP_EvGv, offset, base, rhs);
     }
 
-    void cmpl_mr(int offset, RegisterID base, RegisterID lhs)
+    void cmpl_mr(int32_t offset, RegisterID base, RegisterID lhs)
     {
         spew("cmpl       " MEM_ob ", %s", ADDR_ob(offset, base), nameIReg(4, lhs));
         m_formatter.oneByteOp(OP_CMP_GvEv, offset, base, lhs);
     }
 
     void cmpl_mr(const void *address, RegisterID lhs)
     {
         spew("cmpl       %p, %s", address, nameIReg(4, lhs));
@@ -1580,17 +1588,17 @@ public:
         if (rhs == 0) {
             testl_rr(lhs, lhs);
             return;
         }
 
         spew("cmpl       $0x%x, %s", rhs, nameIReg(4, lhs));
         if (CAN_SIGN_EXTEND_8_32(rhs)) {
             m_formatter.oneByteOp(OP_GROUP1_EvIb, lhs, GROUP1_OP_CMP);
-            m_formatter.immediate8(rhs);
+            m_formatter.immediate8s(rhs);
         } else {
             if (lhs == X86Registers::eax)
                 m_formatter.oneByteOp(OP_CMP_EAXIv);
             else
                 m_formatter.oneByteOp(OP_GROUP1_EvIz, lhs, GROUP1_OP_CMP);
             m_formatter.immediate32(rhs);
         }
     }
@@ -1600,89 +1608,89 @@ public:
         spew("cmpl       $0x%04x, %s", rhs, nameIReg(4, lhs));
         if (lhs == X86Registers::eax)
             m_formatter.oneByteOp(OP_CMP_EAXIv);
         else
             m_formatter.oneByteOp(OP_GROUP1_EvIz, lhs, GROUP1_OP_CMP);
         m_formatter.immediate32(rhs);
     }
 
-    void cmpl_im(int rhs, int offset, RegisterID base)
+    void cmpl_im(int rhs, int32_t offset, RegisterID base)
     {
         spew("cmpl       $0x%x, " MEM_ob, rhs, ADDR_ob(offset, base));
         if (CAN_SIGN_EXTEND_8_32(rhs)) {
             m_formatter.oneByteOp(OP_GROUP1_EvIb, offset, base, GROUP1_OP_CMP);
-            m_formatter.immediate8(rhs);
+            m_formatter.immediate8s(rhs);
         } else {
             m_formatter.oneByteOp(OP_GROUP1_EvIz, offset, base, GROUP1_OP_CMP);
             m_formatter.immediate32(rhs);
         }
     }
 
-    void cmpb_im(int rhs, int offset, RegisterID base)
+    void cmpb_im(int rhs, int32_t offset, RegisterID base)
     {
         spew("cmpb       $0x%x, " MEM_ob, rhs, ADDR_ob(offset, base));
         m_formatter.oneByteOp(OP_GROUP1_EbIb, offset, base, GROUP1_OP_CMP);
         m_formatter.immediate8(rhs);
     }
 
-    void cmpb_im(int rhs, int offset, RegisterID base, RegisterID index, int scale)
+    void cmpb_im(int rhs, int32_t offset, RegisterID base, RegisterID index, int scale)
     {
         spew("cmpb       $0x%x, " MEM_obs, rhs, ADDR_obs(offset, base, index, scale));
         m_formatter.oneByteOp(OP_GROUP1_EbIb, offset, base, index, scale, GROUP1_OP_CMP);
         m_formatter.immediate8(rhs);
     }
 
-    void cmpl_im(int rhs, int offset, RegisterID base, RegisterID index, int scale)
+    void cmpl_im(int rhs, int32_t offset, RegisterID base, RegisterID index, int scale)
     {
         spew("cmpl       $0x%x, " MEM_o32b, rhs, ADDR_o32b(offset, base));
         if (CAN_SIGN_EXTEND_8_32(rhs)) {
             m_formatter.oneByteOp(OP_GROUP1_EvIb, offset, base, index, scale, GROUP1_OP_CMP);
-            m_formatter.immediate8(rhs);
+            m_formatter.immediate8s(rhs);
         } else {
             m_formatter.oneByteOp(OP_GROUP1_EvIz, offset, base, index, scale, GROUP1_OP_CMP);
             m_formatter.immediate32(rhs);
         }
     }
 
     MOZ_WARN_UNUSED_RESULT JmpSrc
-    cmpl_im_disp32(int rhs, int offset, RegisterID base)
+    cmpl_im_disp32(int rhs, int32_t offset, RegisterID base)
     {
         spew("cmpl       $0x%x, " MEM_o32b, rhs, ADDR_o32b(offset, base));
         JmpSrc r;
         if (CAN_SIGN_EXTEND_8_32(rhs)) {
             m_formatter.oneByteOp_disp32(OP_GROUP1_EvIb, offset, base, GROUP1_OP_CMP);
             r = JmpSrc(m_formatter.size());
-            m_formatter.immediate8(rhs);
+            m_formatter.immediate8s(rhs);
         } else {
             m_formatter.oneByteOp_disp32(OP_GROUP1_EvIz, offset, base, GROUP1_OP_CMP);
             r = JmpSrc(m_formatter.size());
             m_formatter.immediate32(rhs);
         }
         return r;
     }
 
     MOZ_WARN_UNUSED_RESULT JmpSrc
     cmpl_im_disp32(int rhs, const void *addr)
     {
         spew("cmpl       $0x%x, %p", rhs, addr);
         JmpSrc r;
         if (CAN_SIGN_EXTEND_8_32(rhs)) {
             m_formatter.oneByteOp_disp32(OP_GROUP1_EvIb, addr, GROUP1_OP_CMP);
             r = JmpSrc(m_formatter.size());
-            m_formatter.immediate8(rhs);
+            m_formatter.immediate8s(rhs);
         } else {
             m_formatter.oneByteOp_disp32(OP_GROUP1_EvIz, addr, GROUP1_OP_CMP);
             r = JmpSrc(m_formatter.size());
             m_formatter.immediate32(rhs);
         }
         return r;
     }
 
-    void cmpl_i32m(int rhs, int offset, RegisterID base)
+    void cmpl_i32m(int rhs, int32_t offset, RegisterID base)
     {
         spew("cmpl       $0x%04x, " MEM_ob, rhs, ADDR_ob(offset, base));
         m_formatter.oneByteOp(OP_GROUP1_EvIz, offset, base, GROUP1_OP_CMP);
         m_formatter.immediate32(rhs);
     }
 
     void cmpl_i32m(int rhs, const void *addr)
     {
@@ -1693,77 +1701,77 @@ public:
 
 #ifdef JS_CODEGEN_X64
     void cmpq_rr(RegisterID rhs, RegisterID lhs)
     {
         spew("cmpq       %s, %s", nameIReg(8, rhs), nameIReg(8, lhs));
         m_formatter.oneByteOp64(OP_CMP_GvEv, rhs, lhs);
     }
 
-    void cmpq_rm(RegisterID rhs, int offset, RegisterID base)
+    void cmpq_rm(RegisterID rhs, int32_t offset, RegisterID base)
     {
         spew("cmpq       %s, " MEM_ob, nameIReg(8, rhs), ADDR_ob(offset, base));
         m_formatter.oneByteOp64(OP_CMP_EvGv, offset, base, rhs);
     }
 
-    void cmpq_mr(int offset, RegisterID base, RegisterID lhs)
+    void cmpq_mr(int32_t offset, RegisterID base, RegisterID lhs)
     {
         spew("cmpq       " MEM_ob ", %s", ADDR_ob(offset, base), nameIReg(8, lhs));
         m_formatter.oneByteOp64(OP_CMP_GvEv, offset, base, lhs);
     }
 
     void cmpq_ir(int rhs, RegisterID lhs)
     {
         if (rhs == 0) {
             testq_rr(lhs, lhs);
             return;
         }
 
         spew("cmpq       $0x%" PRIx64 ", %s", int64_t(rhs), nameIReg(8, lhs));
         if (CAN_SIGN_EXTEND_8_32(rhs)) {
             m_formatter.oneByteOp64(OP_GROUP1_EvIb, lhs, GROUP1_OP_CMP);
-            m_formatter.immediate8(rhs);
+            m_formatter.immediate8s(rhs);
         } else {
             if (lhs == X86Registers::eax)
                 m_formatter.oneByteOp64(OP_CMP_EAXIv);
             else
                 m_formatter.oneByteOp64(OP_GROUP1_EvIz, lhs, GROUP1_OP_CMP);
             m_formatter.immediate32(rhs);
         }
     }
 
-    void cmpq_im(int rhs, int offset, RegisterID base)
+    void cmpq_im(int rhs, int32_t offset, RegisterID base)
     {
         spew("cmpq       $0x%" PRIx64 ", " MEM_ob, int64_t(rhs), ADDR_ob(offset, base));
         if (CAN_SIGN_EXTEND_8_32(rhs)) {
             m_formatter.oneByteOp64(OP_GROUP1_EvIb, offset, base, GROUP1_OP_CMP);
-            m_formatter.immediate8(rhs);
+            m_formatter.immediate8s(rhs);
         } else {
             m_formatter.oneByteOp64(OP_GROUP1_EvIz, offset, base, GROUP1_OP_CMP);
             m_formatter.immediate32(rhs);
         }
     }
 
-    void cmpq_im(int rhs, int offset, RegisterID base, RegisterID index, int scale)
+    void cmpq_im(int rhs, int32_t offset, RegisterID base, RegisterID index, int scale)
     {
         FIXME_INSN_PRINTING;
         if (CAN_SIGN_EXTEND_8_32(rhs)) {
             m_formatter.oneByteOp64(OP_GROUP1_EvIb, offset, base, index, scale, GROUP1_OP_CMP);
-            m_formatter.immediate8(rhs);
+            m_formatter.immediate8s(rhs);
         } else {
             m_formatter.oneByteOp64(OP_GROUP1_EvIz, offset, base, index, scale, GROUP1_OP_CMP);
             m_formatter.immediate32(rhs);
         }
     }
     void cmpq_im(int rhs, const void* addr)
     {
         spew("cmpq       $0x%" PRIx64 ", %p", int64_t(rhs), addr);
         if (CAN_SIGN_EXTEND_8_32(rhs)) {
             m_formatter.oneByteOp64(OP_GROUP1_EvIb, addr, GROUP1_OP_CMP);
-            m_formatter.immediate8(rhs);
+            m_formatter.immediate8s(rhs);
         } else {
             m_formatter.oneByteOp64(OP_GROUP1_EvIz, addr, GROUP1_OP_CMP);
             m_formatter.immediate32(rhs);
         }
     }
     void cmpq_rm(RegisterID rhs, const void* addr)
     {
         spew("cmpq       %s, %p", nameIReg(8, rhs), addr);
@@ -1782,44 +1790,44 @@ public:
         m_formatter.oneByteOp_disp32(OP_CMP_EvGv, addr, rhs);
     }
 
     void cmpl_im(int rhs, const void* addr)
     {
         spew("cmpl       $0x%x, %p", rhs, addr);
         if (CAN_SIGN_EXTEND_8_32(rhs)) {
             m_formatter.oneByteOp(OP_GROUP1_EvIb, addr, GROUP1_OP_CMP);
-            m_formatter.immediate8(rhs);
+            m_formatter.immediate8s(rhs);
         } else {
             m_formatter.oneByteOp(OP_GROUP1_EvIz, addr, GROUP1_OP_CMP);
             m_formatter.immediate32(rhs);
         }
     }
 
     void cmpw_rr(RegisterID rhs, RegisterID lhs)
     {
         spew("cmpw       %s, %s", nameIReg(2, rhs), nameIReg(2, lhs));
         m_formatter.prefix(PRE_OPERAND_SIZE);
         m_formatter.oneByteOp(OP_CMP_GvEv, rhs, lhs);
     }
 
-    void cmpw_rm(RegisterID rhs, int offset, RegisterID base, RegisterID index, int scale)
+    void cmpw_rm(RegisterID rhs, int32_t offset, RegisterID base, RegisterID index, int scale)
     {
         FIXME_INSN_PRINTING;
         m_formatter.prefix(PRE_OPERAND_SIZE);
         m_formatter.oneByteOp(OP_CMP_EvGv, offset, base, index, scale, rhs);
     }
 
-    void cmpw_im(int imm, int offset, RegisterID base, RegisterID index, int scale)
+    void cmpw_im(int32_t imm, int32_t offset, RegisterID base, RegisterID index, int scale)
     {
         FIXME_INSN_PRINTING;
         if (CAN_SIGN_EXTEND_8_32(imm)) {
             m_formatter.prefix(PRE_OPERAND_SIZE);
             m_formatter.oneByteOp(OP_GROUP1_EvIb, offset, base, index, scale, GROUP1_OP_CMP);
-            m_formatter.immediate8(imm);
+            m_formatter.immediate8s(imm);
         } else {
             m_formatter.prefix(PRE_OPERAND_SIZE);
             m_formatter.oneByteOp(OP_GROUP1_EvIz, offset, base, index, scale, GROUP1_OP_CMP);
             m_formatter.immediate16(imm);
         }
     }
 
     void testl_rr(RegisterID rhs, RegisterID lhs)
@@ -1834,62 +1842,62 @@ public:
         m_formatter.oneByteOp(OP_TEST_EbGb, lhs, rhs);
     }
 
     void testl_ir(int rhs, RegisterID lhs)
     {
         // If the mask fits in an 8-bit immediate, we can use testb with an
         // 8-bit subreg.
         if (CAN_ZERO_EXTEND_8_32(rhs) && X86Registers::hasSubregL(lhs)) {
-            testb_i8r(rhs, lhs);
+            testb_ir(rhs, lhs);
             return;
         }
         // If the mask is a subset of 0xff00, we can use testb with an h reg, if
         // one happens to be available.
         if (CAN_ZERO_EXTEND_8H_32(rhs) && X86Registers::hasSubregH(lhs)) {
-            testb_i8r_norex(rhs >> 8, X86Registers::getSubregH(lhs));
+            testb_ir_norex(rhs >> 8, X86Registers::getSubregH(lhs));
             return;
         }
         spew("testl      $0x%x, %s", rhs, nameIReg(4, lhs));
         if (lhs == X86Registers::eax)
             m_formatter.oneByteOp(OP_TEST_EAXIv);
         else
             m_formatter.oneByteOp(OP_GROUP3_EvIz, lhs, GROUP3_OP_TEST);
         m_formatter.immediate32(rhs);
     }
 
-    void testl_i32m(int rhs, int offset, RegisterID base)
+    void testl_i32m(int rhs, int32_t offset, RegisterID base)
     {
         spew("testl      $0x%x, " MEM_ob, rhs, ADDR_ob(offset, base));
         m_formatter.oneByteOp(OP_GROUP3_EvIz, offset, base, GROUP3_OP_TEST);
         m_formatter.immediate32(rhs);
     }
 
     void testl_i32m(int rhs, const void *addr)
     {
         spew("testl      $0x%x, %p", rhs, addr);
         m_formatter.oneByteOp(OP_GROUP3_EvIz, addr, GROUP3_OP_TEST);
         m_formatter.immediate32(rhs);
     }
 
-    void testb_im(int rhs, int offset, RegisterID base)
+    void testb_im(int rhs, int32_t offset, RegisterID base)
     {
         FIXME_INSN_PRINTING;
         m_formatter.oneByteOp(OP_GROUP3_EbIb, offset, base, GROUP3_OP_TEST);
         m_formatter.immediate8(rhs);
     }
 
-    void testb_im(int rhs, int offset, RegisterID base, RegisterID index, int scale)
+    void testb_im(int rhs, int32_t offset, RegisterID base, RegisterID index, int scale)
     {
         FIXME_INSN_PRINTING;
         m_formatter.oneByteOp(OP_GROUP3_EbIb, offset, base, index, scale, GROUP3_OP_TEST);
         m_formatter.immediate8(rhs);
     }
 
-    void testl_i32m(int rhs, int offset, RegisterID base, RegisterID index, int scale)
+    void testl_i32m(int rhs, int32_t offset, RegisterID base, RegisterID index, int scale)
     {
         FIXME_INSN_PRINTING;
         m_formatter.oneByteOp(OP_GROUP3_EvIz, offset, base, index, scale, GROUP3_OP_TEST);
         m_formatter.immediate32(rhs);
     }
 
 #ifdef JS_CODEGEN_X64
     void testq_rr(RegisterID rhs, RegisterID lhs)
@@ -1909,51 +1917,51 @@ public:
         spew("testq      $0x%" PRIx64 ", %s", int64_t(rhs), nameIReg(8, lhs));
         if (lhs == X86Registers::eax)
             m_formatter.oneByteOp64(OP_TEST_EAXIv);
         else
             m_formatter.oneByteOp64(OP_GROUP3_EvIz, lhs, GROUP3_OP_TEST);
         m_formatter.immediate32(rhs);
     }
 
-    void testq_i32m(int rhs, int offset, RegisterID base)
+    void testq_i32m(int rhs, int32_t offset, RegisterID base)
     {
         spew("testq      $0x%" PRIx64 ", " MEM_ob, int64_t(rhs), ADDR_ob(offset, base));
         m_formatter.oneByteOp64(OP_GROUP3_EvIz, offset, base, GROUP3_OP_TEST);
         m_formatter.immediate32(rhs);
     }
 
-    void testq_i32m(int rhs, int offset, RegisterID base, RegisterID index, int scale)
+    void testq_i32m(int rhs, int32_t offset, RegisterID base, RegisterID index, int scale)
     {
         FIXME_INSN_PRINTING;
         m_formatter.oneByteOp64(OP_GROUP3_EvIz, offset, base, index, scale, GROUP3_OP_TEST);
         m_formatter.immediate32(rhs);
     }
 #endif
 
     void testw_rr(RegisterID rhs, RegisterID lhs)
     {
         FIXME_INSN_PRINTING;
         m_formatter.prefix(PRE_OPERAND_SIZE);
         m_formatter.oneByteOp(OP_TEST_EvGv, lhs, rhs);
     }
 
-    void testb_i8r(int rhs, RegisterID lhs)
+    void testb_ir(int rhs, RegisterID lhs)
     {
         spew("testb      $0x%x, %s", rhs, nameIReg(1, lhs));
         if (lhs == X86Registers::eax)
             m_formatter.oneByteOp8(OP_TEST_EAXIb);
         else
             m_formatter.oneByteOp8(OP_GROUP3_EbIb, lhs, GROUP3_OP_TEST);
         m_formatter.immediate8(rhs);
     }
 
-    // Like testb_i8r, but never emits a REX prefix. This may be used to
+    // Like testb_ir, but never emits a REX prefix. This may be used to
     // reference ah..bh.
-    void testb_i8r_norex(int rhs, RegisterID lhs)
+    void testb_ir_norex(int rhs, RegisterID lhs)
     {
         spew("testb      $0x%x, %s", rhs, nameI8Reg_norex(lhs));
         m_formatter.oneByteOp8_norex(OP_GROUP3_EbIb, lhs, GROUP3_OP_TEST);
         m_formatter.immediate8(rhs);
     }
 
     void setCC_r(Condition cond, RegisterID lhs)
     {
@@ -2004,177 +2012,177 @@ public:
 #endif
 
     void movl_rr(RegisterID src, RegisterID dst)
     {
         spew("movl       %s, %s", nameIReg(4,src), nameIReg(4,dst));
         m_formatter.oneByteOp(OP_MOV_GvEv, src, dst);
     }
 
-    void movw_rm(RegisterID src, int offset, RegisterID base)
+    void movw_rm(RegisterID src, int32_t offset, RegisterID base)
     {
         spew("movw       %s, " MEM_ob, nameIReg(2,src), ADDR_ob(offset, base));
         m_formatter.prefix(PRE_OPERAND_SIZE);
         m_formatter.oneByteOp(OP_MOV_EvGv, offset, base, src);
     }
 
-    void movw_rm_disp32(RegisterID src, int offset, RegisterID base)
+    void movw_rm_disp32(RegisterID src, int32_t offset, RegisterID base)
     {
         spew("movw       %s, " MEM_o32b, nameIReg(2,src), ADDR_o32b(offset, base));
         m_formatter.prefix(PRE_OPERAND_SIZE);
         m_formatter.oneByteOp_disp32(OP_MOV_EvGv, offset, base, src);
     }
 
-    void movw_rm(RegisterID src, int offset, RegisterID base, RegisterID index, int scale)
+    void movw_rm(RegisterID src, int32_t offset, RegisterID base, RegisterID index, int scale)
     {
         spew("movw       %s, " MEM_obs, nameIReg(2, src), ADDR_obs(offset, base, index, scale));
         m_formatter.prefix(PRE_OPERAND_SIZE);
         m_formatter.oneByteOp(OP_MOV_EvGv, offset, base, index, scale, src);
     }
 
     void movw_rm(RegisterID src, const void* addr)
     {
         spew("movw       %s, %p", nameIReg(2, src), addr);
         m_formatter.prefix(PRE_OPERAND_SIZE);
         m_formatter.oneByteOp_disp32(OP_MOV_EvGv, addr, src);
     }
 
-    void movl_rm(RegisterID src, int offset, RegisterID base)
+    void movl_rm(RegisterID src, int32_t offset, RegisterID base)
     {
         spew("movl       %s, " MEM_ob, nameIReg(4,src), ADDR_ob(offset, base));
         m_formatter.oneByteOp(OP_MOV_EvGv, offset, base, src);
     }
 
-    void movl_rm_disp32(RegisterID src, int offset, RegisterID base)
+    void movl_rm_disp32(RegisterID src, int32_t offset, RegisterID base)
     {
         spew("movl       %s, " MEM_o32b, nameIReg(4,src), ADDR_o32b(offset, base));
         m_formatter.oneByteOp_disp32(OP_MOV_EvGv, offset, base, src);
     }
 
-    void movl_rm(RegisterID src, int offset, RegisterID base, RegisterID index, int scale)
+    void movl_rm(RegisterID src, int32_t offset, RegisterID base, RegisterID index, int scale)
     {
         spew("movl       %s, " MEM_obs, nameIReg(4, src), ADDR_obs(offset, base, index, scale));
         m_formatter.oneByteOp(OP_MOV_EvGv, offset, base, index, scale, src);
     }
 
     void movl_mEAX(const void* addr)
     {
         spew("movl       %p, %%eax", addr);
         m_formatter.oneByteOp(OP_MOV_EAXOv);
 #ifdef JS_CODEGEN_X64
         m_formatter.immediate64(reinterpret_cast<int64_t>(addr));
 #else
         m_formatter.immediate32(reinterpret_cast<int>(addr));
 #endif
     }
 
-    void movl_mr(int offset, RegisterID base, RegisterID dst)
+    void movl_mr(int32_t offset, RegisterID base, RegisterID dst)
     {
         spew("movl       " MEM_ob ", %s", ADDR_ob(offset, base), nameIReg(4, dst));
         m_formatter.oneByteOp(OP_MOV_GvEv, offset, base, dst);
     }
 
-    void movl_mr_disp32(int offset, RegisterID base, RegisterID dst)
+    void movl_mr_disp32(int32_t offset, RegisterID base, RegisterID dst)
     {
         spew("movl       " MEM_o32b ", %s", ADDR_o32b(offset, base), nameIReg(4,dst));
         m_formatter.oneByteOp_disp32(OP_MOV_GvEv, offset, base, dst);
     }
 
     void movl_mr(const void* base, RegisterID index, int scale, RegisterID dst)
     {
         int32_t disp = addressImmediate(base);
 
         spew("movl       " MEM_os ", %s", ADDR_os(disp, index, scale), nameIReg(4, dst));
         m_formatter.oneByteOp_disp32(OP_MOV_GvEv, disp, index, scale, dst);
     }
 
-    void movl_mr(int offset, RegisterID base, RegisterID index, int scale, RegisterID dst)
+    void movl_mr(int32_t offset, RegisterID base, RegisterID index, int scale, RegisterID dst)
     {
         spew("movl       " MEM_obs ", %s", ADDR_obs(offset, base, index, scale), nameIReg(4, dst));
         m_formatter.oneByteOp(OP_MOV_GvEv, offset, base, index, scale, dst);
     }
 
     void movl_mr(const void* addr, RegisterID dst)
     {
         if (dst == X86Registers::eax) {
             movl_mEAX(addr);
             return;
         }
 
         spew("movl       %p, %s", addr, nameIReg(4, dst));
         m_formatter.oneByteOp(OP_MOV_GvEv, addr, dst);
     }
 
-    void movl_i32r(int imm, RegisterID dst)
+    void movl_i32r(int32_t imm, RegisterID dst)
     {
         spew("movl       $0x%x, %s", imm, nameIReg(4, dst));
         m_formatter.oneByteOp(OP_MOV_EAXIv, dst);
         m_formatter.immediate32(imm);
     }
 
-    void movb_i8r(int imm, RegisterID reg)
+    void movb_ir(int32_t imm, RegisterID reg)
     {
         spew("movb       $0x%x, %s", imm, nameIReg(1, reg));
         m_formatter.oneByteOp(OP_MOV_EbGv, reg);
         m_formatter.immediate8(imm);
     }
 
-    void movb_i8m(int imm, int offset, RegisterID base)
+    void movb_im(int32_t imm, int32_t offset, RegisterID base)
     {
         spew("movb       $0x%x, " MEM_ob, imm, ADDR_ob(offset, base));
         m_formatter.oneByteOp(OP_GROUP11_EvIb, offset, base, GROUP11_MOV);
         m_formatter.immediate8(imm);
     }
 
-    void movb_i8m(int imm, int offset, RegisterID base, RegisterID index, int scale)
+    void movb_im(int32_t imm, int32_t offset, RegisterID base, RegisterID index, int scale)
     {
         spew("movb       $0x%x, " MEM_obs, imm, ADDR_obs(offset, base, index, scale));
         m_formatter.oneByteOp(OP_GROUP11_EvIb, offset, base, index, scale, GROUP11_MOV);
         m_formatter.immediate8(imm);
     }
 
-    void movb_i8m(int imm, const void* addr)
+    void movb_im(int32_t imm, const void* addr)
     {
         spew("movb       $%d, %p", imm, addr);
         m_formatter.oneByteOp_disp32(OP_GROUP11_EvIb, addr, GROUP11_MOV);
         m_formatter.immediate8(imm);
     }
 
-    void movw_i16m(int imm, int offset, RegisterID base)
+    void movw_im(int32_t imm, int32_t offset, RegisterID base)
     {
         spew("movw       $0x%x, " MEM_ob, imm, ADDR_ob(offset, base));
         m_formatter.prefix(PRE_OPERAND_SIZE);
         m_formatter.oneByteOp(OP_GROUP11_EvIz, offset, base, GROUP11_MOV);
         m_formatter.immediate16(imm);
     }
 
-    void movw_i16m(int imm, const void* addr)
+    void movw_im(int32_t imm, const void* addr)
     {
         spew("movw       $%d, %p", imm, addr);
         m_formatter.prefix(PRE_OPERAND_SIZE);
         m_formatter.oneByteOp_disp32(OP_GROUP11_EvIz, addr, GROUP11_MOV);
         m_formatter.immediate16(imm);
     }
 
-    void movl_i32m(int imm, int offset, RegisterID base)
+    void movl_i32m(int32_t imm, int32_t offset, RegisterID base)
     {
         spew("movl       $0x%x, " MEM_ob, imm, ADDR_ob(offset, base));
         m_formatter.oneByteOp(OP_GROUP11_EvIz, offset, base, GROUP11_MOV);
         m_formatter.immediate32(imm);
     }
 
-    void movw_i16m(int imm, int offset, RegisterID base, RegisterID index, int scale)
+    void movw_im(int32_t imm, int32_t offset, RegisterID base, RegisterID index, int scale)
     {
         spew("movw       $0x%x, " MEM_obs, imm, ADDR_obs(offset, base, index, scale));
         m_formatter.prefix(PRE_OPERAND_SIZE);
         m_formatter.oneByteOp(OP_GROUP11_EvIz, offset, base, index, scale, GROUP11_MOV);
         m_formatter.immediate16(imm);
     }
 
-    void movl_i32m(int imm, int offset, RegisterID base, RegisterID index, int scale)
+    void movl_i32m(int32_t imm, int32_t offset, RegisterID base, RegisterID index, int scale)
     {
         spew("movl       $0x%x, " MEM_obs, imm, ADDR_obs(offset, base, index, scale));
         m_formatter.oneByteOp(OP_GROUP11_EvIz, offset, base, index, scale, GROUP11_MOV);
         m_formatter.immediate32(imm);
     }
 
     void movl_EAXm(const void* addr)
     {
@@ -2189,29 +2197,29 @@ public:
 
 #ifdef JS_CODEGEN_X64
     void movq_rr(RegisterID src, RegisterID dst)
     {
         spew("movq       %s, %s", nameIReg(8,src), nameIReg(8,dst));
         m_formatter.oneByteOp64(OP_MOV_GvEv, src, dst);
     }
 
-    void movq_rm(RegisterID src, int offset, RegisterID base)
+    void movq_rm(RegisterID src, int32_t offset, RegisterID base)
     {
         spew("movq       %s, " MEM_ob, nameIReg(8,src), ADDR_ob(offset, base));
         m_formatter.oneByteOp64(OP_MOV_EvGv, offset, base, src);
     }
 
-    void movq_rm_disp32(RegisterID src, int offset, RegisterID base)
+    void movq_rm_disp32(RegisterID src, int32_t offset, RegisterID base)
     {
         FIXME_INSN_PRINTING;
         m_formatter.oneByteOp64_disp32(OP_MOV_EvGv, offset, base, src);
     }
 
-    void movq_rm(RegisterID src, int offset, RegisterID base, RegisterID index, int scale)
+    void movq_rm(RegisterID src, int32_t offset, RegisterID base, RegisterID index, int scale)
     {
         spew("movq       %s, " MEM_obs, nameIReg(8,src), ADDR_obs(offset, base, index, scale));
         m_formatter.oneByteOp64(OP_MOV_EvGv, offset, base, index, scale, src);
     }
 
     void movq_rm(RegisterID src, const void* addr)
     {
         if (src == X86Registers::eax) {
@@ -2232,78 +2240,78 @@ public:
 
     void movq_EAXm(const void* addr)
     {
         spew("movq       %%rax, %p", addr);
         m_formatter.oneByteOp64(OP_MOV_OvEAX);
         m_formatter.immediate64(reinterpret_cast<int64_t>(addr));
     }
 
-    void movq_mr(int offset, RegisterID base, RegisterID dst)
+    void movq_mr(int32_t offset, RegisterID base, RegisterID dst)
     {
         spew("movq       " MEM_ob ", %s", ADDR_ob(offset, base), nameIReg(8,dst));
         m_formatter.oneByteOp64(OP_MOV_GvEv, offset, base, dst);
     }
 
-    void movq_mr_disp32(int offset, RegisterID base, RegisterID dst)
+    void movq_mr_disp32(int32_t offset, RegisterID base, RegisterID dst)
     {
         FIXME_INSN_PRINTING;
         m_formatter.oneByteOp64_disp32(OP_MOV_GvEv, offset, base, dst);
     }
 
-    void movq_mr(int offset, RegisterID base, RegisterID index, int scale, RegisterID dst)
+    void movq_mr(int32_t offset, RegisterID base, RegisterID index, int scale, RegisterID dst)
     {
         spew("movq       " MEM_obs ", %s", ADDR_obs(offset, base, index, scale), nameIReg(8,dst));
         m_formatter.oneByteOp64(OP_MOV_GvEv, offset, base, index, scale, dst);
     }
 
     void movq_mr(const void* addr, RegisterID dst)
     {
         if (dst == X86Registers::eax) {
             movq_mEAX(addr);
             return;
         }
 
         spew("movq       %p, %s", addr, nameIReg(8, dst));
         m_formatter.oneByteOp64(OP_MOV_GvEv, addr, dst);
     }
 
-    void leaq_mr(int offset, RegisterID base, RegisterID index, int scale, RegisterID dst)
+    void leaq_mr(int32_t offset, RegisterID base, RegisterID index, int scale, RegisterID dst)
     {
         spew("leaq       " MEM_obs ", %s", ADDR_obs(offset, base, index, scale), nameIReg(8,dst)),
         m_formatter.oneByteOp64(OP_LEA, offset, base, index, scale, dst);
     }
 
-    void movq_i32m(int imm, int offset, RegisterID base)
+    void movq_i32m(int32_t imm, int32_t offset, RegisterID base)
     {
         spew("movq       $%d, " MEM_ob, imm, ADDR_ob(offset, base));
         m_formatter.oneByteOp64(OP_GROUP11_EvIz, offset, base, GROUP11_MOV);
         m_formatter.immediate32(imm);
     }
 
-    void movq_i32m(int imm, int offset, RegisterID base, RegisterID index, int scale)
+    void movq_i32m(int32_t imm, int32_t offset, RegisterID base, RegisterID index, int scale)
     {
         spew("movq       $%d, " MEM_obs, imm, ADDR_obs(offset, base, index, scale));
         m_formatter.oneByteOp64(OP_GROUP11_EvIz, offset, base, index, scale, GROUP11_MOV);
         m_formatter.immediate32(imm);
     }
-    void movq_i32m(int imm, const void* addr)
+    void movq_i32m(int32_t imm, const void* addr)
     {
         spew("movq       $%d, %p", imm, addr);
         m_formatter.oneByteOp64(OP_GROUP11_EvIz, addr, GROUP11_MOV);
         m_formatter.immediate32(imm);
     }
 
     // Note that this instruction sign-extends its 32-bit immediate field to 64
     // bits and loads the 64-bit value into a 64-bit register.
     //
     // Note also that this is similar to the movl_i32r instruction, except that
     // movl_i32r *zero*-extends its 32-bit immediate, and it has smaller code
     // size, so it's preferred for values which could use either.
-    void movq_i32r(int imm, RegisterID dst) {
+    void movq_i32r(int32_t imm, RegisterID dst) {
         spew("movq       $%d, %s", imm, nameIReg(dst));
         m_formatter.oneByteOp64(OP_GROUP11_EvIz, dst, GROUP11_MOV);
         m_formatter.immediate32(imm);
     }
 
     void movq_i64r(int64_t imm, RegisterID dst)
     {
         spew("movabsq    $0x%" PRIx64 ", %s", imm, nameIReg(8, dst));
@@ -2344,72 +2352,72 @@ public:
             movl_EAXm(addr);
             return;
         }
 
         spew("movl       %s, %p", nameIReg(4, src), addr);
         m_formatter.oneByteOp(OP_MOV_EvGv, addr, src);
     }
 
-    void movl_i32m(int imm, const void* addr)
+    void movl_i32m(int32_t imm, const void* addr)
     {
         spew("movl       $%d, %p", imm, addr);
         m_formatter.oneByteOp(OP_GROUP11_EvIz, addr, GROUP11_MOV);
         m_formatter.immediate32(imm);
     }
 
-    void movb_rm(RegisterID src, int offset, RegisterID base)
+    void movb_rm(RegisterID src, int32_t offset, RegisterID base)
     {
         spew("movb       %s, " MEM_ob, nameIReg(1, src), ADDR_ob(offset, base));
         m_formatter.oneByteOp8(OP_MOV_EbGv, offset, base, src);
     }
 
-    void movb_rm_disp32(RegisterID src, int offset, RegisterID base)
+    void movb_rm_disp32(RegisterID src, int32_t offset, RegisterID base)
     {
         spew("movb       %s, " MEM_o32b, nameIReg(1, src), ADDR_o32b(offset, base));
         m_formatter.oneByteOp8_disp32(OP_MOV_EbGv, offset, base, src);
     }
 
-    void movb_rm(RegisterID src, int offset, RegisterID base, RegisterID index, int scale)
+    void movb_rm(RegisterID src, int32_t offset, RegisterID base, RegisterID index, int scale)
     {
         spew("movb       %s, " MEM_obs, nameIReg(1, src), ADDR_obs(offset, base, index, scale));
         m_formatter.oneByteOp8(OP_MOV_EbGv, offset, base, index, scale, src);
     }
 
     void movb_rm(RegisterID src, const void* addr)
     {
         spew("movb       %s, %p", nameIReg(1, src), addr);
         m_formatter.oneByteOp8(OP_MOV_EbGv, addr, src);
     }
 
-    void movb_mr(int offset, RegisterID base, RegisterID dst)
+    void movb_mr(int32_t offset, RegisterID base, RegisterID dst)
     {
         spew("movb       " MEM_ob ", %s", ADDR_ob(offset, base), nameIReg(1, dst));
         m_formatter.oneByteOp(OP_MOV_GvEb, offset, base, dst);
     }
 
-    void movb_mr(int offset, RegisterID base, RegisterID index, int scale, RegisterID dst)
+    void movb_mr(int32_t offset, RegisterID base, RegisterID index, int scale, RegisterID dst)
     {
         spew("movb       " MEM_obs ", %s", ADDR_obs(offset, base, index, scale), nameIReg(1, dst));
         m_formatter.oneByteOp(OP_MOV_GvEb, offset, base, index, scale, dst);
     }
 
-    void movzbl_mr(int offset, RegisterID base, RegisterID dst)
+    void movzbl_mr(int32_t offset, RegisterID base, RegisterID dst)
     {
         spew("movzbl     " MEM_ob ", %s", ADDR_ob(offset, base), nameIReg(4, dst));
         m_formatter.twoByteOp(OP2_MOVZX_GvEb, offset, base, dst);
     }
 
-    void movzbl_mr_disp32(int offset, RegisterID base, RegisterID dst)
+    void movzbl_mr_disp32(int32_t offset, RegisterID base, RegisterID dst)
     {
         spew("movzbl     " MEM_o32b ", %s", ADDR_o32b(offset, base), nameIReg(4, dst));
         m_formatter.twoByteOp_disp32(OP2_MOVZX_GvEb, offset, base, dst);
     }
 
-    void movzbl_mr(int offset, RegisterID base, RegisterID index, int scale, RegisterID dst)
+    void movzbl_mr(int32_t offset, RegisterID base, RegisterID index, int scale, RegisterID dst)
     {
         spew("movzbl     " MEM_obs ", %s", ADDR_obs(offset, base, index, scale), nameIReg(4, dst));
         m_formatter.twoByteOp(OP2_MOVZX_GvEb, offset, base, index, scale, dst);
     }
 
     void movzbl_mr(const void* addr, RegisterID dst)
     {
         spew("movzbl     %p, %s", addr, nameIReg(4, dst));
@@ -2417,29 +2425,29 @@ public:
     }
 
     void movsbl_rr(RegisterID src, RegisterID dst)
     {
         spew("movsbl     %s, %s", nameIReg(1,src), nameIReg(4,dst));
         m_formatter.twoByteOp8_movx(OP2_MOVSX_GvEb, src, dst);
     }
 
-    void movsbl_mr(int offset, RegisterID base, RegisterID dst)
+    void movsbl_mr(int32_t offset, RegisterID base, RegisterID dst)
     {
         spew("movsbl     " MEM_ob ", %s", ADDR_ob(offset, base), nameIReg(4, dst));
         m_formatter.twoByteOp(OP2_MOVSX_GvEb, offset, base, dst);
     }
 
-    void movsbl_mr_disp32(int offset, RegisterID base, RegisterID dst)
+    void movsbl_mr_disp32(int32_t offset, RegisterID base, RegisterID dst)
     {
         spew("movsbl     " MEM_o32b ", %s", ADDR_o32b(offset, base), nameIReg(4, dst));
         m_formatter.twoByteOp_disp32(OP2_MOVSX_GvEb, offset, base, dst);
     }
 
-    void movsbl_mr(int offset, RegisterID base, RegisterID index, int scale, RegisterID dst)
+    void movsbl_mr(int32_t offset, RegisterID base, RegisterID index, int scale, RegisterID dst)
     {
         spew("movsbl     " MEM_obs ", %s", ADDR_obs(offset, base, index, scale), nameIReg(4, dst));
         m_formatter.twoByteOp(OP2_MOVSX_GvEb, offset, base, index, scale, dst);
     }
 
     void movsbl_mr(const void* addr, RegisterID dst)
     {
         spew("movsbl     %p, %s", addr, nameIReg(4, dst));
@@ -2447,29 +2455,29 @@ public:
     }
 
     void movzwl_rr(RegisterID src, RegisterID dst)
     {
         spew("movzwl     %s, %s", nameIReg(2, src), nameIReg(4, dst));
         m_formatter.twoByteOp(OP2_MOVZX_GvEw, src, dst);
     }
 
-    void movzwl_mr(int offset, RegisterID base, RegisterID dst)
+    void movzwl_mr(int32_t offset, RegisterID base, RegisterID dst)
     {
         spew("movzwl     " MEM_ob ", %s", ADDR_ob(offset, base), nameIReg(4, dst));
         m_formatter.twoByteOp(OP2_MOVZX_GvEw, offset, base, dst);
     }
 
-    void movzwl_mr_disp32(int offset, RegisterID base, RegisterID dst)
+    void movzwl_mr_disp32(int32_t offset, RegisterID base, RegisterID dst)
     {
         spew("movzwl     " MEM_o32b ", %s", ADDR_o32b(offset, base), nameIReg(4, dst));
         m_formatter.twoByteOp_disp32(OP2_MOVZX_GvEw, offset, base, dst);
     }
 
-    void movzwl_mr(int offset, RegisterID base, RegisterID index, int scale, RegisterID dst)
+    void movzwl_mr(int32_t offset, RegisterID base, RegisterID index, int scale, RegisterID dst)
     {
         spew("movzwl     " MEM_obs ", %s", ADDR_obs(offset, base, index, scale), nameIReg(4, dst));
         m_formatter.twoByteOp(OP2_MOVZX_GvEw, offset, base, index, scale, dst);
     }
 
     void movzwl_mr(const void* addr, RegisterID dst)
     {
         spew("movzwl     %p, %s", addr, nameIReg(4, dst));
@@ -2477,29 +2485,29 @@ public:
     }
 
     void movswl_rr(RegisterID src, RegisterID dst)
     {
         spew("movswl     %s, %s", nameIReg(2, src), nameIReg(4, dst));
         m_formatter.twoByteOp(OP2_MOVSX_GvEw, src, dst);
     }
 
-    void movswl_mr(int offset, RegisterID base, RegisterID dst)
+    void movswl_mr(int32_t offset, RegisterID base, RegisterID dst)
     {
         spew("movswl     " MEM_ob ", %s", ADDR_ob(offset, base), nameIReg(4, dst));
         m_formatter.twoByteOp(OP2_MOVSX_GvEw, offset, base, dst);
     }
 
-    void movswl_mr_disp32(int offset, RegisterID base, RegisterID dst)
+    void movswl_mr_disp32(int32_t offset, RegisterID base, RegisterID dst)
     {
         spew("movswl     " MEM_o32b ", %s", ADDR_o32b(offset, base), nameIReg(4, dst));
         m_formatter.twoByteOp_disp32(OP2_MOVSX_GvEw, offset, base, dst);
     }
 
-    void movswl_mr(int offset, RegisterID base, RegisterID index, int scale, RegisterID dst)
+    void movswl_mr(int32_t offset, RegisterID base, RegisterID index, int scale, RegisterID dst)
     {
         spew("movswl     " MEM_obs ", %s", ADDR_obs(offset, base, index, scale), nameIReg(4, dst));
         m_formatter.twoByteOp(OP2_MOVSX_GvEw, offset, base, index, scale, dst);
     }
 
     void movswl_mr(const void* addr, RegisterID dst)
     {
         spew("movswl     %p, %s", addr, nameIReg(4, dst));
@@ -2507,29 +2515,29 @@ public:
     }
 
     void movzbl_rr(RegisterID src, RegisterID dst)
     {
         spew("movzbl     %s, %s", nameIReg(1,src), nameIReg(4,dst));
         m_formatter.twoByteOp8_movx(OP2_MOVZX_GvEb, src, dst);
     }
 
-    void leal_mr(int offset, RegisterID base, RegisterID index, int scale, RegisterID dst)
+    void leal_mr(int32_t offset, RegisterID base, RegisterID index, int scale, RegisterID dst)
     {
         spew("leal       " MEM_obs ", %s", ADDR_obs(offset, base, index, scale), nameIReg(4, dst));
         m_formatter.oneByteOp(OP_LEA, offset, base, index, scale, dst);
     }
 
-    void leal_mr(int offset, RegisterID base, RegisterID dst)
+    void leal_mr(int32_t offset, RegisterID base, RegisterID dst)
     {
         spew("leal       " MEM_ob ", %s", ADDR_ob(offset, base), nameIReg(4,dst));
         m_formatter.oneByteOp(OP_LEA, offset, base, dst);
     }
 #ifdef JS_CODEGEN_X64
-    void leaq_mr(int offset, RegisterID base, RegisterID dst)
+    void leaq_mr(int32_t offset, RegisterID base, RegisterID dst)
     {
         spew("leaq       " MEM_ob ", %s", ADDR_ob(offset, base), nameIReg(8,dst));
         m_formatter.oneByteOp64(OP_LEA, offset, base, dst);
     }
 
     JmpSrc leaq_rip(RegisterID dst)
     {
         spew("leaq       ?(%%rip), %s", nameIReg(dst));
@@ -2551,17 +2559,17 @@ public:
     JmpSrc call(RegisterID dst)
     {
         m_formatter.oneByteOp(OP_GROUP5_Ev, dst, GROUP5_OP_CALLN);
         JmpSrc r = JmpSrc(m_formatter.size());
         spew("call       *%s", nameIReg(dst));
         return r;
     }
 
-    void call_m(int offset, RegisterID base)
+    void call_m(int32_t offset, RegisterID base)
     {
         spew("call       *" MEM_ob, ADDR_ob(offset, base));
         m_formatter.oneByteOp(OP_GROUP5_Ev, offset, base, GROUP5_OP_CALLN);
     }
 
     // Comparison of EAX against a 32-bit immediate. The immediate is patched
     // in as if it were a jump target. The intention is to toggle the first
     // byte of the instruction between a CMP and a JMP to produce a pseudo-NOP.
@@ -2586,23 +2594,23 @@ public:
     // really shouldn't wrap this as a Jump, since it can't be linked. :-/
     JmpSrc jmp_r(RegisterID dst)
     {
         spew("jmp        *%s", nameIReg(dst));
         m_formatter.oneByteOp(OP_GROUP5_Ev, dst, GROUP5_OP_JMPN);
         return JmpSrc(m_formatter.size());
     }
 
-    void jmp_m(int offset, RegisterID base)
+    void jmp_m(int32_t offset, RegisterID base)
     {
         spew("jmp        *" MEM_ob, ADDR_ob(offset, base));
         m_formatter.oneByteOp(OP_GROUP5_Ev, offset, base, GROUP5_OP_JMPN);
     }
 
-    void jmp_m(int offset, RegisterID base, RegisterID index, int scale) {
+    void jmp_m(int32_t offset, RegisterID base, RegisterID index, int scale) {
         spew("jmp        *" MEM_obs, ADDR_obs(offset, base, index, scale));
         m_formatter.oneByteOp(OP_GROUP5_Ev, offset, base, index, scale, GROUP5_OP_JMPN);
     }
 
 #ifdef JS_CODEGEN_X64
     void jmp_rip(int ripOffset) {
         // rip-relative addressing.
         spew("jmp        *%d(%%rip)", ripOffset);
@@ -2705,100 +2713,100 @@ public:
     {
         twoByteOpSimd("vpcmpeqw", VEX_PD, OP2_PCMPEQW, src1, src0, dst);
     }
 
     void vpcmpeqd_rr(XMMRegisterID src1, XMMRegisterID src0, XMMRegisterID dst)
     {
         twoByteOpSimd("vpcmpeqd", VEX_PD, OP2_PCMPEQD_VdqWdq, src1, src0, dst);
     }
-    void vpcmpeqd_mr(int offset, RegisterID base, XMMRegisterID src0, XMMRegisterID dst)
+    void vpcmpeqd_mr(int32_t offset, RegisterID base, XMMRegisterID src0, XMMRegisterID dst)
     {
         twoByteOpSimd("vpcmpeqd", VEX_PD, OP2_PCMPEQD_VdqWdq, offset, base, src0, dst);
     }
     void vpcmpeqd_mr(const void* address, XMMRegisterID src0, XMMRegisterID dst)
     {
         twoByteOpSimd("vpcmpeqd", VEX_PD, OP2_PCMPEQD_VdqWdq, address, src0, dst);
     }
 
     void vpcmpgtd_rr(XMMRegisterID src1, XMMRegisterID src0, XMMRegisterID dst)
     {
         twoByteOpSimd("vpcmpgtd", VEX_PD, OP2_PCMPGTD_VdqWdq, src1, src0, dst);
     }
-    void vpcmpgtd_mr(int offset, RegisterID base, XMMRegisterID src0, XMMRegisterID dst)
+    void vpcmpgtd_mr(int32_t offset, RegisterID base, XMMRegisterID src0, XMMRegisterID dst)
     {
         twoByteOpSimd("vpcmpgtd", VEX_PD, OP2_PCMPGTD_VdqWdq, offset, base, src0, dst);
     }
     void vpcmpgtd_mr(const void* address, XMMRegisterID src0, XMMRegisterID dst)
     {
         twoByteOpSimd("vpcmpgtd", VEX_PD, OP2_PCMPGTD_VdqWdq, address, src0, dst);
     }
 
     void vcmpps_rr(uint8_t order, XMMRegisterID src1, XMMRegisterID src0, XMMRegisterID dst)
     {
         twoByteOpSimd("vcmpps", VEX_PS, OP2_CMPPS_VpsWps, src1, src0, dst);
-        m_formatter.immediate8(order);
-    }
-    void vcmpps_mr(uint8_t order, int offset, RegisterID base, XMMRegisterID src0, XMMRegisterID dst)
+        m_formatter.immediate8s(order);
+    }
+    void vcmpps_mr(uint8_t order, int32_t offset, RegisterID base, XMMRegisterID src0, XMMRegisterID dst)
     {
         twoByteOpSimd("vcmpps", VEX_PS, OP2_CMPPS_VpsWps, offset, base, src0, dst);
-        m_formatter.immediate8(order);
+        m_formatter.immediate8s(order);
     }
     void vcmpps_mr(uint8_t order, const void* address, XMMRegisterID src0, XMMRegisterID dst)
     {
         twoByteOpSimd("vcmpps", VEX_PS, OP2_CMPPS_VpsWps, address, src0, dst);
-        m_formatter.immediate8(order);
+        m_formatter.immediate8s(order);
     }
 
     void vrcpps_rr(XMMRegisterID src, XMMRegisterID dst) {
         twoByteOpSimd("vrcpps", VEX_PS, OP2_RCPPS_VpsWps, src, X86Registers::invalid_xmm, dst);
     }
-    void vrcpps_mr(int offset, RegisterID base, XMMRegisterID dst) {
+    void vrcpps_mr(int32_t offset, RegisterID base, XMMRegisterID dst) {
         twoByteOpSimd("vrcpps", VEX_PS, OP2_RCPPS_VpsWps, offset, base, X86Registers::invalid_xmm, dst);
     }
     void vrcpps_mr(const void* address, XMMRegisterID dst) {
         twoByteOpSimd("vrcpps", VEX_PS, OP2_RCPPS_VpsWps, address, X86Registers::invalid_xmm, dst);
     }
 
     void vrsqrtps_rr(XMMRegisterID src, XMMRegisterID dst) {
         twoByteOpSimd("vrsqrtps", VEX_PS, OP2_RSQRTPS_VpsWps, src, X86Registers::invalid_xmm, dst);
     }
-    void vrsqrtps_mr(int offset, RegisterID base, XMMRegisterID dst) {
+    void vrsqrtps_mr(int32_t offset, RegisterID base, XMMRegisterID dst) {
         twoByteOpSimd("vrsqrtps", VEX_PS, OP2_RSQRTPS_VpsWps, offset, base, X86Registers::invalid_xmm, dst);
     }
     void vrsqrtps_mr(const void* address, XMMRegisterID dst) {
         twoByteOpSimd("vrsqrtps", VEX_PS, OP2_RSQRTPS_VpsWps, address, X86Registers::invalid_xmm, dst);
     }
 
     void vsqrtps_rr(XMMRegisterID src, XMMRegisterID dst) {
         twoByteOpSimd("vsqrtps", VEX_PS, OP2_SQRTPS_VpsWps, src, X86Registers::invalid_xmm, dst);
     }
-    void vsqrtps_mr(int offset, RegisterID base, XMMRegisterID dst) {
+    void vsqrtps_mr(int32_t offset, RegisterID base, XMMRegisterID dst) {
         twoByteOpSimd("vsqrtps", VEX_PS, OP2_SQRTPS_VpsWps, offset, base, X86Registers::invalid_xmm, dst);
     }
     void vsqrtps_mr(const void* address, XMMRegisterID dst) {
         twoByteOpSimd("vsqrtps", VEX_PS, OP2_SQRTPS_VpsWps, address, X86Registers::invalid_xmm, dst);
     }
 
     void vaddsd_rr(XMMRegisterID src1, XMMRegisterID src0, XMMRegisterID dst)
     {
         twoByteOpSimd("vaddsd", VEX_SD, OP2_ADDSD_VsdWsd, src1, src0, dst);
     }
 
     void vaddss_rr(XMMRegisterID src1, XMMRegisterID src0, XMMRegisterID dst)
     {
         twoByteOpSimd("vaddss", VEX_SS, OP2_ADDSD_VsdWsd, src1, src0, dst);
     }
 
-    void vaddsd_mr(int offset, RegisterID base, XMMRegisterID src0, XMMRegisterID dst)
+    void vaddsd_mr(int32_t offset, RegisterID base, XMMRegisterID src0, XMMRegisterID dst)
     {
         twoByteOpSimd("vaddsd", VEX_SD, OP2_ADDSD_VsdWsd, offset, base, src0, dst);
     }
 
-    void vaddss_mr(int offset, RegisterID base, XMMRegisterID src0, XMMRegisterID dst)
+    void vaddss_mr(int32_t offset, RegisterID base, XMMRegisterID src0, XMMRegisterID dst)
     {
         twoByteOpSimd("vaddss", VEX_SS, OP2_ADDSD_VsdWsd, offset, base, src0, dst);
     }
 
     void vaddsd_mr(const void* address, XMMRegisterID src0, XMMRegisterID dst)
     {
         twoByteOpSimd("vaddsd", VEX_SD, OP2_ADDSD_VsdWsd, address, src0, dst);
     }
@@ -2843,32 +2851,32 @@ public:
         twoByteOpInt64Simd("vcvtsi2sd", VEX_SD, OP2_CVTSI2SD_VsdEd, src1, src0, dst);
     }
     void vcvtsq2ss_rr(RegisterID src1, XMMRegisterID src0, XMMRegisterID dst)
     {
         twoByteOpInt64Simd("vcvtsi2ss", VEX_SS, OP2_CVTSI2SD_VsdEd, src1, src0, dst);
     }
 #endif
 
-    void vcvtsi2sd_mr(int offset, RegisterID base, XMMRegisterID src0, XMMRegisterID dst)
+    void vcvtsi2sd_mr(int32_t offset, RegisterID base, XMMRegisterID src0, XMMRegisterID dst)
     {
         twoByteOpSimd("vcvtsi2sd", VEX_SD, OP2_CVTSI2SD_VsdEd, offset, base, src0, dst);
     }
 
-    void vcvtsi2sd_mr(int offset, RegisterID base, RegisterID index, int scale, XMMRegisterID src0, XMMRegisterID dst)
+    void vcvtsi2sd_mr(int32_t offset, RegisterID base, RegisterID index, int scale, XMMRegisterID src0, XMMRegisterID dst)
     {
         twoByteOpSimd("vcvtsi2sd", VEX_SD, OP2_CVTSI2SD_VsdEd, offset, base, index, scale, src0, dst);
     }
 
-    void vcvtsi2ss_mr(int offset, RegisterID base, XMMRegisterID src0, XMMRegisterID dst)
+    void vcvtsi2ss_mr(int32_t offset, RegisterID base, XMMRegisterID src0, XMMRegisterID dst)
     {
         twoByteOpSimd("vcvtsi2ss", VEX_SS, OP2_CVTSI2SD_VsdEd, offset, base, src0, dst);
     }
 
-    void vcvtsi2ss_mr(int offset, RegisterID base, RegisterID index, int scale, XMMRegisterID src0, XMMRegisterID dst)
+    void vcvtsi2ss_mr(int32_t offset, RegisterID base, RegisterID index, int scale, XMMRegisterID src0, XMMRegisterID dst)
     {
         twoByteOpSimd("vcvtsi2ss", VEX_SS, OP2_CVTSI2SD_VsdEd, offset, base, index, scale, src0, dst);
     }
 
 #ifdef JS_CODEGEN_X86
     void vcvtsi2sd_mr(const void* address, XMMRegisterID src0, XMMRegisterID dst)
     {
         twoByteOpSimd("vcvtsi2sd", VEX_SD, OP2_CVTSI2SD_VsdEd, address, src0, dst);
@@ -2906,108 +2914,105 @@ public:
     {
         twoByteOpSimd("vunpckhps", VEX_PS, OP2_UNPCKHPS_VsdWsd, src1, src0, dst);
     }
 
     void vpand_rr(XMMRegisterID src1, XMMRegisterID src0, XMMRegisterID dst)
     {
         twoByteOpSimd("vpand", VEX_PD, OP2_PANDDQ_VdqWdq, src1, src0, dst);
     }
-    void vpand_mr(int offset, RegisterID base, XMMRegisterID src0, XMMRegisterID dst)
+    void vpand_mr(int32_t offset, RegisterID base, XMMRegisterID src0, XMMRegisterID dst)
     {
         twoByteOpSimd("vpand", VEX_PD, OP2_PANDDQ_VdqWdq, offset, base, src0, dst);
     }
     void vpand_mr(const void *address, XMMRegisterID src0, XMMRegisterID dst)
     {
         twoByteOpSimd("vpand", VEX_PD, OP2_PANDDQ_VdqWdq, address, src0, dst);
     }
     void vpor_rr(XMMRegisterID src1, XMMRegisterID src0, XMMRegisterID dst)
     {
         twoByteOpSimd("vpor", VEX_PD, OP2_PORDQ_VdqWdq, src1, src0, dst);
     }
-    void vpor_mr(int offset, RegisterID base, XMMRegisterID src0, XMMRegisterID dst)
+    void vpor_mr(int32_t offset, RegisterID base, XMMRegisterID src0, XMMRegisterID dst)
     {
         twoByteOpSimd("vpor", VEX_PD, OP2_PORDQ_VdqWdq, offset, base, src0, dst);
     }
     void vpor_mr(const void *address, XMMRegisterID src0, XMMRegisterID dst)
     {
         twoByteOpSimd("vpor", VEX_PD, OP2_PORDQ_VdqWdq, address, src0, dst);
     }
     void vpxor_rr(XMMRegisterID src1, XMMRegisterID src0, XMMRegisterID dst)
     {
         twoByteOpSimd("vpxor", VEX_PD, OP2_PXORDQ_VdqWdq, src1, src0, dst);
     }
-    void vpxor_mr(int offset, RegisterID base, XMMRegisterID src0, XMMRegisterID dst)
+    void vpxor_mr(int32_t offset, RegisterID base, XMMRegisterID src0, XMMRegisterID dst)
     {
         twoByteOpSimd("vpxor", VEX_PD, OP2_PXORDQ_VdqWdq, offset, base, src0, dst);
     }
     void vpxor_mr(const void *address, XMMRegisterID src0, XMMRegisterID dst)
     {
         twoByteOpSimd("vpxor", VEX_PD, OP2_PXORDQ_VdqWdq, address, src0, dst);
     }
     void vpandn_rr(XMMRegisterID src1, XMMRegisterID src0, XMMRegisterID dst)
     {
         twoByteOpSimd("vpandn", VEX_PD, OP2_PANDNDQ_VdqWdq, src1, src0, dst);
     }
-    void vpandn_mr(int offset, RegisterID base, XMMRegisterID src0, XMMRegisterID dst)
+    void vpandn_mr(int32_t offset, RegisterID base, XMMRegisterID src0, XMMRegisterID dst)
     {
         twoByteOpSimd("vpandn", VEX_PD, OP2_PANDNDQ_VdqWdq, offset, base, src0, dst);
     }
     void vpandn_mr(const void *address, XMMRegisterID src0, XMMRegisterID dst)
     {
         twoByteOpSimd("vpandn", VEX_PD, OP2_PANDNDQ_VdqWdq, address, src0, dst);
     }
 
     void pshufd_irr(uint32_t mask, XMMRegisterID src, XMMRegisterID dst)
     {
-        MOZ_ASSERT(mask < 256);
         spew("pshufd     $0x%x, %s, %s", mask, nameFPReg(src), nameFPReg(dst));
         m_formatter.prefix(PRE_SSE_66);
         m_formatter.twoByteOp(OP2_PSHUFD_VdqWdqIb, (RegisterID)src, (RegisterID)dst);
-        m_formatter.immediate8(uint8_t(mask));
-    }
-
-    void pshufd_imr(uint32_t mask, int offset, RegisterID base, XMMRegisterID dst)
+        m_formatter.immediate8u(mask);
+    }
+
+    void pshufd_imr(uint32_t mask, int32_t offset, RegisterID base, XMMRegisterID dst)
     {
         MOZ_ASSERT(mask < 256);
         spew("pshufd     $0x%x, " MEM_ob ", %s", mask, ADDR_ob(offset, base), nameFPReg(dst));
         m_formatter.prefix(PRE_SSE_66);
         m_formatter.twoByteOp(OP2_PSHUFD_VdqWdqIb, offset, base, (RegisterID)dst);
-        m_formatter.immediate8(uint8_t(mask));
+        m_formatter.immediate8u(mask);
     }
 
     void pshufd_imr(uint32_t mask, const void* address, XMMRegisterID dst)
     {
         spew("pshufd     $0x%x, %p, %s", mask, address, nameFPReg(dst));
         m_formatter.prefix(PRE_SSE_66);
         m_formatter.twoByteOp(OP2_PSHUFD_VdqWdqIb, address, (RegisterID)dst);
-        m_formatter.immediate8(uint8_t(mask));
+        m_formatter.immediate8u(mask);
     }
 
     void shufps_irr(uint32_t mask, XMMRegisterID src, XMMRegisterID dst)
     {
-        MOZ_ASSERT(mask < 256);
         spew("shufps     $0x%x, %s, %s", mask, nameFPReg(src), nameFPReg(dst));
         m_formatter.twoByteOp(OP2_SHUFPS_VpsWpsIb, (RegisterID)src, (RegisterID)dst);
-        m_formatter.immediate8(uint8_t(mask));
-    }
-
-    void shufps_imr(uint32_t mask, int offset, RegisterID base, XMMRegisterID dst)
-    {
-        MOZ_ASSERT(mask < 256);
+        m_formatter.immediate8u(mask);
+    }
+
+    void shufps_imr(uint32_t mask, int32_t offset, RegisterID base, XMMRegisterID dst)
+    {
         spew("shufps     $0x%x, " MEM_ob ", %s", mask, ADDR_ob(offset, base), nameFPReg(dst));
         m_formatter.twoByteOp(OP2_SHUFPS_VpsWpsIb, offset, base, (RegisterID)dst);
-        m_formatter.immediate8(uint8_t(mask));
+        m_formatter.immediate8u(mask);
     }
 
     void shufps_imr(uint32_t mask, const void* address, XMMRegisterID dst)
     {
         spew("shufps     $0x%x, %p, %s", mask, address, nameFPReg(dst));
         m_formatter.twoByteOp(OP2_SHUFPS_VpsWpsIb, address, (RegisterID)dst);
-        m_formatter.immediate8(uint8_t(mask));
+        m_formatter.immediate8u(mask);
     }
 
     void vmovhlps_rr(XMMRegisterID src1, XMMRegisterID src0, XMMRegisterID dst)
     {
         twoByteOpSimd("vmovhlps", VEX_PS, OP2_MOVHLPS_VqUq, src1, src0, dst);
     }
 
     void vmovlhps_rr(XMMRegisterID src1, XMMRegisterID src0, XMMRegisterID dst)
@@ -3015,72 +3020,72 @@ public:
         twoByteOpSimd("vmovlhps", VEX_PS, OP2_MOVLHPS_VqUq, src1, src0, dst);
     }
 
     void psrldq_ir(int shift, XMMRegisterID dest)
     {
         spew("psrldq     $%d, %s", shift, nameFPReg(dest));
         m_formatter.prefix(PRE_SSE_66);
         m_formatter.twoByteOp(OP2_PSRLDQ_Vd, (RegisterID)dest, (RegisterID)3);
-        m_formatter.immediate8(shift);
+        m_formatter.immediate8s(shift);
     }
 
     void psllq_ir(int shift, XMMRegisterID dest)
     {
         spew("psllq      $%d, %s", shift, nameFPReg(dest));
         m_formatter.prefix(PRE_SSE_66);
         m_formatter.twoByteOp(OP2_PSRLDQ_Vd, (RegisterID)dest, (RegisterID)6);
-        m_formatter.immediate8(shift);
+        m_formatter.immediate8s(shift);
     }
 
     void psrlq_ir(int shift, XMMRegisterID dest)
     {
         spew("psrlq      $%d, %s", shift, nameFPReg(dest));
         m_formatter.prefix(PRE_SSE_66);
         m_formatter.twoByteOp(OP2_PSRLDQ_Vd, (RegisterID)dest, (RegisterID)2);
-        m_formatter.immediate8(shift);
+        m_formatter.immediate8s(shift);
     }
 
     void vpslld_rr(XMMRegisterID src1, XMMRegisterID src0, XMMRegisterID dst)
     {
         twoByteOpSimd("vpslld", VEX_PD, OP2_PSLLD_VdqWdq, src1, src0, dst);
     }
 
     void pslld_ir(int32_t count, XMMRegisterID dst)
     {
         spew("pslld      $%d, %s", count, nameFPReg(dst));
         m_formatter.prefix(PRE_SSE_66);
         m_formatter.twoByteOp(OP2_PSLLD_UdqIb, (RegisterID)dst, (RegisterID)6);
-        m_formatter.immediate8(int8_t(count));
+        m_formatter.immediate8s(int8_t(count));
     }
 
     void vpsrad_rr(XMMRegisterID src1, XMMRegisterID src0, XMMRegisterID dst)
     {
         twoByteOpSimd("vpsrad", VEX_PD, OP2_PSRAD_VdqWdq, src1, src0, dst);
     }
 
     void psrad_ir(int32_t count, XMMRegisterID dst)
     {
         spew("psrad      $%d, %s", count, nameFPReg(dst));
         m_formatter.prefix(PRE_SSE_66);
         m_formatter.twoByteOp(OP2_PSRAD_UdqIb, (RegisterID)dst, (RegisterID)4);
-        m_formatter.immediate8(int8_t(count));
+        m_formatter.immediate8s(int8_t(count));
     }
 
     void vpsrld_rr(XMMRegisterID src1, XMMRegisterID src0, XMMRegisterID dst)
     {
         twoByteOpSimd("vpsrld", VEX_PD, OP2_PSRLD_VdqWdq, src1, src0, dst);
     }
 
     void psrld_ir(int32_t count, XMMRegisterID dst)
     {
         spew("psrld      $%d, %s", count, nameFPReg(dst));
         m_formatter.prefix(PRE_SSE_66);
         m_formatter.twoByteOp(OP2_PSRLD_UdqIb, (RegisterID)dst, (RegisterID)2);
-        m_formatter.immediate8(int8_t(count));
+        m_formatter.immediate8s(int8_t(count));
     }
 
     void vmovmskpd_rr(XMMRegisterID src, RegisterID dst)
     {
         twoByteOpSimdInt32("vmovmskpd", VEX_PD, OP2_MOVMSKPD_EdVd, src, dst);
     }
 
     void vmovmskps_rr(XMMRegisterID src, RegisterID dst)
@@ -3109,84 +3114,84 @@ public:
     }
 
     void vmovq_rr(RegisterID src, XMMRegisterID dst)
     {
         twoByteOpInt64Simd("vmovq", VEX_PD, OP2_MOVD_VdEd, src, X86Registers::invalid_xmm, dst);
     }
 #endif
 
-    void movsd_rm(XMMRegisterID src, int offset, RegisterID base)
+    void movsd_rm(XMMRegisterID src, int32_t offset, RegisterID base)
     {
         spew("movsd      %s, " MEM_ob, nameFPReg(src), ADDR_ob(offset, base));
         m_formatter.prefix(PRE_SSE_F2);
         m_formatter.twoByteOp(OP2_MOVSD_WsdVsd, offset, base, (RegisterID)src);
     }
 
-    void movsd_rm_disp32(XMMRegisterID src, int offset, RegisterID base)
+    void movsd_rm_disp32(XMMRegisterID src, int32_t offset, RegisterID base)
     {
         spew("movsd      %s, " MEM_o32b, nameFPReg(src), ADDR_o32b(offset, base));
         m_formatter.prefix(PRE_SSE_F2);
         m_formatter.twoByteOp_disp32(OP2_MOVSD_WsdVsd, offset, base, (RegisterID)src);
     }
 
-    void movss_rm(XMMRegisterID src, int offset, RegisterID base)
+    void movss_rm(XMMRegisterID src, int32_t offset, RegisterID base)
     {
         spew("movss      %s, " MEM_ob, nameFPReg(src), ADDR_ob(offset, base));
         m_formatter.prefix(PRE_SSE_F3);
         m_formatter.twoByteOp(OP2_MOVSD_WsdVsd, offset, base, (RegisterID)src);
     }
 
-    void movss_rm_disp32(XMMRegisterID src, int offset, RegisterID base)
+    void movss_rm_disp32(XMMRegisterID src, int32_t offset, RegisterID base)
     {
         spew("movss      %s, " MEM_o32b, nameFPReg(src), ADDR_o32b(offset, base));
         m_formatter.prefix(PRE_SSE_F3);
         m_formatter.twoByteOp_disp32(OP2_MOVSD_WsdVsd, offset, base, (RegisterID)src);
     }
 
-    void vmovss_mr(int offset, RegisterID base, XMMRegisterID dst)
+    void vmovss_mr(int32_t offset, RegisterID base, XMMRegisterID dst)
     {
         twoByteOpSimd("vmovss", VEX_SS, OP2_MOVSD_VsdWsd, offset, base, X86Registers::invalid_xmm, dst);
     }
 
-    void vmovss_mr_disp32(int offset, RegisterID base, XMMRegisterID dst)
+    void vmovss_mr_disp32(int32_t offset, RegisterID base, XMMRegisterID dst)
     {
         twoByteOpSimd_disp32("vmovss", VEX_SS, OP2_MOVSD_VsdWsd, offset, base, X86Registers::invalid_xmm, dst);
     }
 
-    void movsd_rm(XMMRegisterID src, int offset, RegisterID base, RegisterID index, int scale)
+    void movsd_rm(XMMRegisterID src, int32_t offset, RegisterID base, RegisterID index, int scale)
     {
         spew("movsd      %s, " MEM_obs, nameFPReg(src), ADDR_obs(offset, base, index, scale));
         m_formatter.prefix(PRE_SSE_F2);
         m_formatter.twoByteOp(OP2_MOVSD_WsdVsd, offset, base, index, scale, (RegisterID)src);
     }
 
-    void movss_rm(XMMRegisterID src, int offset, RegisterID base, RegisterID index, int scale)
+    void movss_rm(XMMRegisterID src, int32_t offset, RegisterID base, RegisterID index, int scale)
     {
         spew("movss      %s, " MEM_obs, nameFPReg(src), ADDR_obs(offset, base, index, scale));
         m_formatter.prefix(PRE_SSE_F3);
         m_formatter.twoByteOp(OP2_MOVSD_WsdVsd, offset, base, index, scale, (RegisterID)src);
     }
 
-    void vmovss_mr(int offset, RegisterID base, RegisterID index, int scale, XMMRegisterID dst)
+    void vmovss_mr(int32_t offset, RegisterID base, RegisterID index, int scale, XMMRegisterID dst)
     {
         twoByteOpSimd("vmovss", VEX_SS, OP2_MOVSD_VsdWsd, offset, base, index, scale, X86Registers::invalid_xmm, dst);
     }
 
-    void vmovsd_mr(int offset, RegisterID base, XMMRegisterID dst)
+    void vmovsd_mr(int32_t offset, RegisterID base, XMMRegisterID dst)
     {
         twoByteOpSimd("vmovsd", VEX_SD, OP2_MOVSD_VsdWsd, offset, base, X86Registers::invalid_xmm, dst);
     }
 
-    void vmovsd_mr_disp32(int offset, RegisterID base, XMMRegisterID dst)
+    void vmovsd_mr_disp32(int32_t offset, RegisterID base, XMMRegisterID dst)
     {
         twoByteOpSimd_disp32("vmovsd", VEX_SD, OP2_MOVSD_VsdWsd, offset, base, X86Registers::invalid_xmm, dst);
     }
 
-    void vmovsd_mr(int offset, RegisterID base, RegisterID index, int scale, XMMRegisterID dst)
+    void vmovsd_mr(int32_t offset, RegisterID base, RegisterID index, int scale, XMMRegisterID dst)
     {
         twoByteOpSimd("vmovsd", VEX_SD, OP2_MOVSD_VsdWsd, offset, base, index, scale, X86Registers::invalid_xmm, dst);
     }
 
     // Note that the register-to-register form of movsd does not write to the
     // entire output register. For general-purpose register-to-register moves,
     // use movapd instead.
     void vmovsd_rr(XMMRegisterID src1, XMMRegisterID src0, XMMRegisterID dst)
@@ -3303,59 +3308,59 @@ public:
         return JmpSrc(m_formatter.size());
     }
 #endif
 
     void vmovaps_rr(XMMRegisterID src, XMMRegisterID dst)
     {
         twoByteOpSimd("vmovaps", VEX_PS, OP2_MOVAPS_VsdWsd, src, X86Registers::invalid_xmm, dst);
     }
-    void movaps_rm(XMMRegisterID src, int offset, RegisterID base)
+    void movaps_rm(XMMRegisterID src, int32_t offset, RegisterID base)
     {
         spew("movaps     %s, " MEM_ob, nameFPReg(src), ADDR_ob(offset, base));
         m_formatter.twoByteOp(OP2_MOVAPS_WsdVsd, offset, base, (RegisterID)src);
     }
-    void movaps_rm(XMMRegisterID src, int offset, RegisterID base, RegisterID index, int scale)
+    void movaps_rm(XMMRegisterID src, int32_t offset, RegisterID base, RegisterID index, int scale)
     {
         spew("movaps     %s, " MEM_obs, nameFPReg(src), ADDR_obs(offset, base, index, scale));
         m_formatter.twoByteOp(OP2_MOVAPS_WsdVsd, offset, base, index, scale, (RegisterID)src);
     }
-    void vmovaps_mr(int offset, RegisterID base, XMMRegisterID dst)
+    void vmovaps_mr(int32_t offset, RegisterID base, XMMRegisterID dst)
     {
         twoByteOpSimd("vmovaps", VEX_PS, OP2_MOVAPS_VsdWsd, offset, base, X86Registers::invalid_xmm, dst);
     }
-    void vmovaps_mr(int offset, RegisterID base, RegisterID index, int scale, XMMRegisterID dst)
+    void vmovaps_mr(int32_t offset, RegisterID base, RegisterID index, int scale, XMMRegisterID dst)
     {
         twoByteOpSimd("vmovaps", VEX_PS, OP2_MOVAPS_VsdWsd, offset, base, index, scale, X86Registers::invalid_xmm, dst);
     }
 
-    void movups_rm(XMMRegisterID src, int offset, RegisterID base)
+    void movups_rm(XMMRegisterID src, int32_t offset, RegisterID base)
     {
         spew("movups     %s, " MEM_ob, nameFPReg(src), ADDR_ob(offset, base));
         m_formatter.twoByteOp(OP2_MOVPS_WpsVps, offset, base, (RegisterID)src);
     }
-    void movups_rm_disp32(XMMRegisterID src, int offset, RegisterID base)
+    void movups_rm_disp32(XMMRegisterID src, int32_t offset, RegisterID base)
     {
         spew("movups     %s, " MEM_o32b, nameFPReg(src), ADDR_o32b(offset, base));
         m_formatter.twoByteOp_disp32(OP2_MOVPS_WpsVps, offset, base, (RegisterID)src);
     }
-    void movups_rm(XMMRegisterID src, int offset, RegisterID base, RegisterID index, int scale)
+    void movups_rm(XMMRegisterID src, int32_t offset, RegisterID base, RegisterID index, int scale)
     {
         spew("movups     %s, " MEM_obs, nameFPReg(src), ADDR_obs(offset, base, index, scale));
         m_formatter.twoByteOp(OP2_MOVPS_WpsVps, offset, base, index, scale, (RegisterID)src);
     }
-    void vmovups_mr(int offset, RegisterID base, XMMRegisterID dst)
+    void vmovups_mr(int32_t offset, RegisterID base, XMMRegisterID dst)
     {
         twoByteOpSimd("vmovups", VEX_PS, OP2_MOVPS_VpsWps, offset, base, X86Registers::invalid_xmm, dst);
     }
-    void vmovups_mr_disp32(int offset, RegisterID base, XMMRegisterID dst)
+    void vmovups_mr_disp32(int32_t offset, RegisterID base, XMMRegisterID dst)
     {
         twoByteOpSimd_disp32("vmovups", VEX_PS, OP2_MOVPS_VpsWps, offset, base, X86Registers::invalid_xmm, dst);
     }
-    void vmovups_mr(int offset, RegisterID base, RegisterID index, int scale, XMMRegisterID dst)
+    void vmovups_mr(int32_t offset, RegisterID base, RegisterID index, int scale, XMMRegisterID dst)
     {
         twoByteOpSimd("vmovups", VEX_PS, OP2_MOVPS_VpsWps, offset, base, index, scale, X86Registers::invalid_xmm, dst);
     }
 
     void vmovapd_rr(XMMRegisterID src, XMMRegisterID dst)
     {
         twoByteOpSimd("vmovapd", VEX_PD, OP2_MOVAPD_VsdWsd, src, X86Registers::invalid_xmm, dst);
     }
@@ -3382,98 +3387,98 @@ public:
     }
 
     void vmovdqa_mr(const void* address, XMMRegisterID dst)
     {
         twoByteOpSimd("vmovdqa", VEX_PD, OP2_MOVDQ_VdqWdq, address, X86Registers::invalid_xmm, dst);
     }
 #endif // JS_CODEGEN_X64
 
-    void movdqu_rm(XMMRegisterID src, int offset, RegisterID base)
+    void movdqu_rm(XMMRegisterID src, int32_t offset, RegisterID base)
     {
         spew("movdqu     %s, " MEM_ob, nameFPReg(src), ADDR_ob(offset, base));
         m_formatter.prefix(PRE_SSE_F3);
         m_formatter.twoByteOp(OP2_MOVDQ_WdqVdq, offset, base, (RegisterID)src);
     }
 
-    void movdqu_rm_disp32(XMMRegisterID src, int offset, RegisterID base)
+    void movdqu_rm_disp32(XMMRegisterID src, int32_t offset, RegisterID base)
     {
         spew("movdqu     %s, " MEM_o32b, nameFPReg(src), ADDR_o32b(offset, base));
         m_formatter.prefix(PRE_SSE_F3);
         m_formatter.twoByteOp_disp32(OP2_MOVDQ_WdqVdq, offset, base, (RegisterID)src);
     }
 
-    void movdqu_rm(XMMRegisterID src, int offset, RegisterID base, RegisterID index, int scale)
+    void movdqu_rm(XMMRegisterID src, int32_t offset, RegisterID base, RegisterID index, int scale)
     {
         spew("movdqu     %s, " MEM_obs, nameFPReg(src), ADDR_obs(offset, base, index, scale));
         m_formatter.prefix(PRE_SSE_F3);
         m_formatter.twoByteOp(OP2_MOVDQ_WdqVdq, offset, base, index, scale, (RegisterID)src);
     }
 
-    void vmovdqu_mr(int offset, RegisterID base, XMMRegisterID dst)
+    void vmovdqu_mr(int32_t offset, RegisterID base, XMMRegisterID dst)
     {
         twoByteOpSimd("vmovdqu", VEX_SS, OP2_MOVDQ_VdqWdq, offset, base, X86Registers::invalid_xmm, dst);
     }
 
-    void vmovdqu_mr_disp32(int offset, RegisterID base, XMMRegisterID dst)
+    void vmovdqu_mr_disp32(int32_t offset, RegisterID base, XMMRegisterID dst)
     {
         twoByteOpSimd_disp32("vmovdqu", VEX_SS, OP2_MOVDQ_VdqWdq, offset, base, X86Registers::invalid_xmm, dst);
     }
 
-    void vmovdqu_mr(int offset, RegisterID base, RegisterID index, int scale, XMMRegisterID dst)
+    void vmovdqu_mr(int32_t offset, RegisterID base, RegisterID index, int scale, XMMRegisterID dst)
     {
         twoByteOpSimd("vmovdqu", VEX_SS, OP2_MOVDQ_VdqWdq, offset, base, index, scale, X86Registers::invalid_xmm, dst);
     }
 
     void vmovdqa_rr(XMMRegisterID src, XMMRegisterID dst)
     {
         twoByteOpSimd("vmovdqa", VEX_PD, OP2_MOVDQ_VdqWdq, src, X86Registers::invalid_xmm, dst);
     }
 
-    void movdqa_rm(XMMRegisterID src, int offset, RegisterID base)
+    void movdqa_rm(XMMRegisterID src, int32_t offset, RegisterID base)
     {
         spew("movdqa     %s, " MEM_ob, nameFPReg(src), ADDR_ob(offset, base));
         m_formatter.prefix(PRE_SSE_66);
         m_formatter.twoByteOp(OP2_MOVDQ_WdqVdq, offset, base, (RegisterID)src);
     }
 
-    void movdqa_rm(XMMRegisterID src, int offset, RegisterID base, RegisterID index, int scale)
+    void movdqa_rm(XMMRegisterID src, int32_t offset, RegisterID base, RegisterID index, int scale)
     {
         spew("movdqa     %s, " MEM_obs, nameFPReg(src), ADDR_obs(offset, base, index, scale));
         m_formatter.prefix(PRE_SSE_66);
         m_formatter.twoByteOp(OP2_MOVDQ_WdqVdq, offset, base, index, scale, (RegisterID)src);
     }
 
-    void vmovdqa_mr(int offset, RegisterID base, XMMRegisterID dst)
+    void vmovdqa_mr(int32_t offset, RegisterID base, XMMRegisterID dst)
     {
 
         twoByteOpSimd("vmovdqa", VEX_PD, OP2_MOVDQ_VdqWdq, offset, base, X86Registers::invalid_xmm, dst);
     }
 
-    void vmovdqa_mr(int offset, RegisterID base, RegisterID index, int scale, XMMRegisterID dst)
+    void vmovdqa_mr(int32_t offset, RegisterID base, RegisterID index, int scale, XMMRegisterID dst)
     {
         twoByteOpSimd("vmovdqa", VEX_PD, OP2_MOVDQ_VdqWdq, offset, base, index, scale, X86Registers::invalid_xmm, dst);
     }
 
     void vmulsd_rr(XMMRegisterID src1, XMMRegisterID src0, XMMRegisterID dst)
     {
         twoByteOpSimd("vmulsd", VEX_SD, OP2_MULSD_VsdWsd, src1, src0, dst);
     }
 
     void vmulss_rr(XMMRegisterID src1, XMMRegisterID src0, XMMRegisterID dst)
     {
         twoByteOpSimd("vmulss", VEX_SS, OP2_MULSD_VsdWsd, src1, src0, dst);
     }
 
-    void vmulsd_mr(int offset, RegisterID base, XMMRegisterID src0, XMMRegisterID dst)
+    void vmulsd_mr(int32_t offset, RegisterID base, XMMRegisterID src0, XMMRegisterID dst)
     {
         twoByteOpSimd("vmulsd", VEX_SD, OP2_MULSD_VsdWsd, offset, base, src0, dst);
     }
 
-    void vmulss_mr(int offset, RegisterID base, XMMRegisterID src0, XMMRegisterID dst)
+    void vmulss_mr(int32_t offset, RegisterID base, XMMRegisterID src0, XMMRegisterID dst)
     {
         twoByteOpSimd("vmulss", VEX_SS, OP2_MULSD_VsdWsd, offset, base, src0, dst);
     }
 
     void pextrw_irr(int whichWord, XMMRegisterID src, RegisterID dst)
     {
         FIXME_INSN_PRINTING;
         m_formatter.prefix(PRE_SSE_66);
@@ -3486,57 +3491,57 @@ public:
         twoByteOpSimd("vsubsd", VEX_SD, OP2_SUBSD_VsdWsd, src1, src0, dst);
     }
 
     void vsubss_rr(XMMRegisterID src1, XMMRegisterID src0, XMMRegisterID dst)
     {
         twoByteOpSimd("vsubss", VEX_SS, OP2_SUBSD_VsdWsd, src1, src0, dst);
     }
 
-    void vsubsd_mr(int offset, RegisterID base, XMMRegisterID src0, XMMRegisterID dst)
+    void vsubsd_mr(int32_t offset, RegisterID base, XMMRegisterID src0, XMMRegisterID dst)
     {
         twoByteOpSimd("vsubsd", VEX_SD, OP2_SUBSD_VsdWsd, offset, base, src0, dst);
     }
 
-    void vsubss_mr(int offset, RegisterID base, XMMRegisterID src0, XMMRegisterID dst)
+    void vsubss_mr(int32_t offset, RegisterID base, XMMRegisterID src0, XMMRegisterID dst)
     {
         twoByteOpSimd("vsubss", VEX_SS, OP2_SUBSD_VsdWsd, offset, base, src0, dst);
     }
 
     void vucomiss_rr(XMMRegisterID rhs, XMMRegisterID lhs)
     {
         twoByteOpSimdFlags("vucomiss", VEX_PS, OP2_UCOMISD_VsdWsd, rhs, lhs);
     }
 
     void vucomisd_rr(XMMRegisterID rhs, XMMRegisterID lhs)
     {
         twoByteOpSimdFlags("vucomisd", VEX_PD, OP2_UCOMISD_VsdWsd, rhs, lhs);
     }
 
-    void vucomisd_mr(int offset, RegisterID base, XMMRegisterID lhs)
+    void vucomisd_mr(int32_t offset, RegisterID base, XMMRegisterID lhs)
     {
         twoByteOpSimdFlags("vucomisd", VEX_PD, OP2_UCOMISD_VsdWsd, offset, base, lhs);
     }
 
     void vdivsd_rr(XMMRegisterID src1, XMMRegisterID src0, XMMRegisterID dst)
     {
         twoByteOpSimd("vdivsd", VEX_SD, OP2_DIVSD_VsdWsd, src1, src0, dst);
     }
 
     void vdivss_rr(XMMRegisterID src1, XMMRegisterID src0, XMMRegisterID dst)
     {
         twoByteOpSimd("vdivss", VEX_SS, OP2_DIVSD_VsdWsd, src1, src0, dst);
     }
 
-    void vdivsd_mr(int offset, RegisterID base, XMMRegisterID src0, XMMRegisterID dst)
+    void vdivsd_mr(int32_t offset, RegisterID base, XMMRegisterID src0, XMMRegisterID dst)
     {
         twoByteOpSimd("vdivsd", VEX_SD, OP2_DIVSD_VsdWsd, offset, base, src0, dst);
     }
 
-    void vdivss_mr(int offset, RegisterID base, XMMRegisterID src0, XMMRegisterID dst)
+    void vdivss_mr(int32_t offset, RegisterID base, XMMRegisterID src0, XMMRegisterID dst)
     {
         twoByteOpSimd("vdivss", VEX_SS, OP2_DIVSD_VsdWsd, offset, base, src0, dst);
     }
 
     void vxorpd_rr(XMMRegisterID src1, XMMRegisterID src0, XMMRegisterID dst)
     {
         twoByteOpSimd("vxorpd", VEX_PD, OP2_XORPD_VpdWpd, src1, src0, dst);
     }
@@ -3551,62 +3556,62 @@ public:
         twoByteOpSimd("vandpd", VEX_PD, OP2_ANDPD_VpdWpd, src1, src0, dst);
     }
 
     void vandps_rr(XMMRegisterID src1, XMMRegisterID src0, XMMRegisterID dst)
     {
         twoByteOpSimd("vandps", VEX_PS, OP2_ANDPS_VpsWps, src1, src0, dst);
     }
 
-    void vandps_mr(int offset, RegisterID base, XMMRegisterID src0, XMMRegisterID dst)
+    void vandps_mr(int32_t offset, RegisterID base, XMMRegisterID src0, XMMRegisterID dst)
     {
         twoByteOpSimd("vandps", VEX_PS, OP2_ANDPS_VpsWps, offset, base, src0, dst);
     }
 
     void vandps_mr(const void* address, XMMRegisterID src0, XMMRegisterID dst)
     {
         twoByteOpSimd("vandps", VEX_PS, OP2_ANDPS_VpsWps, address, src0, dst);
     }
 
     void vandnps_rr(XMMRegisterID src1, XMMRegisterID src0, XMMRegisterID dst)
     {
         twoByteOpSimd("vandnps", VEX_PS, OP2_ANDNPS_VpsWps, src1, src0, dst);
     }
 
-    void vandnps_mr(int offset, RegisterID base, XMMRegisterID src0, XMMRegisterID dst)
+    void vandnps_mr(int32_t offset, RegisterID base, XMMRegisterID src0, XMMRegisterID dst)
     {
         twoByteOpSimd("vandnps", VEX_PS, OP2_ANDNPS_VpsWps, offset, base, src0, dst);
     }
 
     void vandnps_mr(const void* address, XMMRegisterID src0, XMMRegisterID dst)
     {
         twoByteOpSimd("vandnps", VEX_PS, OP2_ANDNPS_VpsWps, address, src0, dst);
     }
 
     void vorps_rr(XMMRegisterID src1, XMMRegisterID src0, XMMRegisterID dst)
     {
         twoByteOpSimd("vorps", VEX_PS, OP2_ORPS_VpsWps, src1, src0, dst);
     }
 
-    void vorps_mr(int offset, RegisterID base, XMMRegisterID src0, XMMRegisterID dst)
+    void vorps_mr(int32_t offset, RegisterID base, XMMRegisterID src0, XMMRegisterID dst)
     {
         twoByteOpSimd("vorps", VEX_PS, OP2_ORPS_VpsWps, offset, base, src0, dst);
     }
 
     void vorps_mr(const void* address, XMMRegisterID src0, XMMRegisterID dst)
     {
         twoByteOpSimd("vorps", VEX_PS, OP2_ORPS_VpsWps, address, src0, dst);
     }
 
     void vxorps_rr(XMMRegisterID src1, XMMRegisterID src0, XMMRegisterID dst)
     {
         twoByteOpSimd("vxorps", VEX_PS, OP2_XORPS_VpsWps, src1, src0, dst);
     }
 
-    void vxorps_mr(int offset, RegisterID base, XMMRegisterID src0, XMMRegisterID dst)
+    void vxorps_mr(int32_t offset, RegisterID base, XMMRegisterID src0, XMMRegisterID dst)
     {
         twoByteOpSimd("vxorps", VEX_PS, OP2_XORPS_VpsWps, offset, base, src0, dst);
     }
 
     void vxorps_mr(const void* address, XMMRegisterID src0, XMMRegisterID dst)
     {
         twoByteOpSimd("vxorps", VEX_PS, OP2_XORPS_VpsWps, address, src0, dst);
     }
@@ -3621,132 +3626,131 @@ public:
         twoByteOpSimd("vsqrtss", VEX_SS, OP2_SQRTSS_VssWss, src1, src0, dst);
     }
 
     void roundsd_rr(RoundingMode mode, XMMRegisterID src, XMMRegisterID dst)
     {
         spew("roundsd    $%d, %s, %s", (int)mode, nameFPReg(src), nameFPReg(dst));
         m_formatter.prefix(PRE_SSE_66);
         m_formatter.threeByteOp(OP3_ROUNDSD_VsdWsd, ESCAPE_ROUNDSD, (RegisterID)src, (RegisterID)dst);
-        m_formatter.immediate8(mode);
+        m_formatter.immediate8u(mode);
     }
 
     void roundss_rr(RoundingMode mode, XMMRegisterID src, XMMRegisterID dst)
     {
         spew("roundss    $%d, %s, %s", (int)mode, nameFPReg(src), nameFPReg(dst));
         m_formatter.prefix(PRE_SSE_66);
         m_formatter.threeByteOp(OP3_ROUNDSS_VsdWsd, ESCAPE_ROUNDSD, (RegisterID)src, (RegisterID)dst);
         m_formatter.immediate8(mode); // modes are the same for roundsd and roundss
     }
 
     void insertps_irr(unsigned mask, XMMRegisterID src, XMMRegisterID dst)
     {
-        MOZ_ASSERT(mask < 256);
         spew("insertps   $0x%x, %s, %s", mask, nameFPReg(src), nameFPReg(dst));
         m_formatter.prefix(PRE_SSE_66);
         m_formatter.threeByteOp(OP3_INSERTPS_VpsUps, ESCAPE_INSERTPS, (RegisterID)src, (RegisterID)dst);
-        m_formatter.immediate8(uint8_t(mask));
+        m_formatter.immediate8u(mask);
     }
 
     void pinsrd_irr(unsigned lane, RegisterID src, XMMRegisterID dst)
     {
         MOZ_ASSERT(lane < 4);
         spew("pinsrd     $0x%x, %s, %s", lane, nameIReg(4, src), nameFPReg(dst));
         m_formatter.prefix(PRE_SSE_66);
         m_formatter.threeByteOp(OP3_PINSRD_VdqEdIb, ESCAPE_PINSRD, (RegisterID)src, (RegisterID)dst);
-        m_formatter.immediate8(uint8_t(lane));
-    }
-
-    void pinsrd_imr(unsigned lane, int offset, RegisterID base, XMMRegisterID dst)
+        m_formatter.immediate8u(lane);
+    }
+
+    void pinsrd_imr(unsigned lane, int32_t offset, RegisterID base, XMMRegisterID dst)
     {
         MOZ_ASSERT(lane < 4);
         spew("pinsrd     $0x%x, " MEM_ob ", %s", lane, ADDR_ob(offset, base), nameFPReg(dst));
         m_formatter.prefix(PRE_SSE_66);
         m_formatter.threeByteOp(OP3_PINSRD_VdqEdIb, ESCAPE_PINSRD, offset, base, (RegisterID)dst);
-        m_formatter.immediate8(uint8_t(lane));
+        m_formatter.immediate8u(lane);
     }
 
     void pextrd_irr(unsigned lane, XMMRegisterID src, RegisterID dst)
     {
         MOZ_ASSERT(lane < 4);
         spew("pextrd     $0x%x, %s, %s", lane, nameFPReg(src), nameIReg(4, dst));
         m_formatter.prefix(PRE_SSE_66);
         m_formatter.threeByteOp(OP3_PEXTRD_EdVdqIb, ESCAPE_PEXTRD, (RegisterID)dst, (RegisterID)src);
-        m_formatter.immediate8(uint8_t(lane));
-    }
-
-    void pextrd_imr(unsigned lane, XMMRegisterID src, int offset, RegisterID base)
+        m_formatter.immediate8u(lane);
+    }
+
+    void pextrd_imr(unsigned lane, XMMRegisterID src, int32_t offset, RegisterID base)
     {
         MOZ_ASSERT(lane < 4);
         spew("pextrd     $0x%x, %s, " MEM_ob, lane, nameFPReg(src), ADDR_ob(offset, base));
         m_formatter.prefix(PRE_SSE_66);
         m_formatter.threeByteOp(OP3_PEXTRD_EdVdqIb, ESCAPE_PEXTRD, offset, base, (RegisterID)src);
-        m_formatter.immediate8(uint8_t(lane));
+        m_formatter.immediate8u(lane);
     }
 
     void vblendps_irr(unsigned imm, XMMRegisterID src1, XMMRegisterID src0, XMMRegisterID dst)
     {
         MOZ_ASSERT(imm < 16);
         // Despite being a "ps" instruction, vblendps is encoded with the "pd" prefix.
         threeByteOpSimd("vblendps", VEX_PD, OP3_BLENDPS_VpsWpsIb, ESCAPE_BLENDPS, src1, src0, dst);
-        m_formatter.immediate8(uint8_t(imm));
-    }
-
-    void vblendps_imr(unsigned imm, int offset, RegisterID base, XMMRegisterID src0, XMMRegisterID dst)
+        m_formatter.immediate8u(imm);
+    }
+
+    void vblendps_imr(unsigned imm, int32_t offset, RegisterID base, XMMRegisterID src0, XMMRegisterID dst)
     {
         MOZ_ASSERT(imm < 16);
         // Despite being a "ps" instruction, vblendps is encoded with the "pd" prefix.
         threeByteOpSimd("vblendps", VEX_PD, OP3_BLENDPS_VpsWpsIb, ESCAPE_BLENDPS, offset, base, src0, dst);
-        m_formatter.immediate8(uint8_t(imm));
+        m_formatter.immediate8u(imm);
     }
 
     void vblendvps_rr(XMMRegisterID mask, XMMRegisterID src1, XMMRegisterID src0, XMMRegisterID dst) {
         vblendvOpSimd(mask, src1, src0, dst);
     }
-    void vblendvps_mr(XMMRegisterID mask, int offset, RegisterID base, XMMRegisterID src0, XMMRegisterID dst) {
+    void vblendvps_mr(XMMRegisterID mask, int32_t offset, RegisterID base, XMMRegisterID src0, XMMRegisterID dst) {
         vblendvOpSimd(mask, offset, base, src0, dst);
     }
 
     void vmovsldup_rr(XMMRegisterID src, XMMRegisterID dst)
     {
         twoByteOpSimd("vmovsldup", VEX_SS, OP2_MOVSLDUP_VpsWps, src, X86Registers::invalid_xmm, dst);
     }
-    void vmovsldup_mr(int offset, RegisterID base, XMMRegisterID dst)
+    void vmovsldup_mr(int32_t offset, RegisterID base, XMMRegisterID dst)
     {
         twoByteOpSimd("vmovsldup", VEX_SS, OP2_MOVSLDUP_VpsWps, offset, base, X86Registers::invalid_xmm, dst);
     }
 
     void vmovshdup_rr(XMMRegisterID src, XMMRegisterID dst)
     {
         twoByteOpSimd("vmovshdup", VEX_SS, OP2_MOVSHDUP_VpsWps, src, X86Registers::invalid_xmm, dst);
     }
-    void vmovshdup_mr(int offset, RegisterID base, XMMRegisterID dst)
+    void vmovshdup_mr(int32_t offset, RegisterID base, XMMRegisterID dst)
     {
         twoByteOpSimd("vmovshdup", VEX_SS, OP2_MOVSHDUP_VpsWps, offset, base, X86Registers::invalid_xmm, dst);
     }
 
     void vminsd_rr(XMMRegisterID src1, XMMRegisterID src0, XMMRegisterID dst)
     {
         twoByteOpSimd("vminsd", VEX_SD, OP2_MINSD_VsdWsd, src1, src0, dst);
     }
-    void vminsd_mr(int offset, RegisterID base, XMMRegisterID src0, XMMRegisterID dst)
+    void vminsd_mr(int32_t offset, RegisterID base, XMMRegisterID src0, XMMRegisterID dst)
     {
         twoByteOpSimd("vminsd", VEX_SD, OP2_MINSD_VsdWsd, offset, base, src0, dst);
     }
 
     void vminss_rr(XMMRegisterID src1, XMMRegisterID src0, XMMRegisterID dst)
     {
         twoByteOpSimd("vminss", VEX_SS, OP2_MINSS_VssWss, src1, src0, dst);
     }
 
     void vmaxsd_rr(XMMRegisterID src1, XMMRegisterID src0, XMMRegisterID dst)
     {
         twoByteOpSimd("vmaxsd", VEX_SD, OP2_MAXSD_VsdWsd, src1, src0, dst);
     }
-    void vmaxsd_mr(int offset, RegisterID base, XMMRegisterID src0, XMMRegisterID dst)
+    void vmaxsd_mr(int32_t offset, RegisterID base, XMMRegisterID src0, XMMRegisterID dst)
     {
         twoByteOpSimd("vmaxsd", VEX_SD, OP2_MAXSD_VsdWsd, offset, base, src0, dst);
     }
 
     void vmaxss_rr(XMMRegisterID src1, XMMRegisterID src0, XMMRegisterID dst)
     {
         twoByteOpSimd("vmaxss", VEX_SS, OP2_MAXSS_VssWss, src1, src0, dst);
     }
@@ -3766,21 +3770,21 @@ public:
     }
 
     void ret()
     {
         spew("ret");
         m_formatter.oneByteOp(OP_RET);
     }
 
-    void ret(int imm)
+    void ret_i(int32_t imm)
     {
         spew("ret        $%d", imm);
         m_formatter.oneByteOp(OP_RET_Iz);
-        m_formatter.immediate16(imm);
+        m_formatter.immediate16u(imm);
     }
 
     void predictNotTaken()
     {
         FIXME_INSN_PRINTING;
         m_formatter.prefix(PRE_PREDICT_BRANCH_NOT_TAKEN);
     }
 
@@ -4175,17 +4179,17 @@ private:
             return;
         }
 
         spew("%-11s%s, %s, %s", name, nameFPReg(rm), nameFPReg(src0), nameFPReg(dst));
         m_formatter.twoByteOpVex(ty, opcode, (RegisterID)rm, src0, dst);
     }
 
     void twoByteOpSimd(const char *name, VexOperandType ty, TwoByteOpcodeID opcode,
-                       int offset, RegisterID base, XMMRegisterID src0, XMMRegisterID dst)
+                       int32_t offset, RegisterID base, XMMRegisterID src0, XMMRegisterID dst)
     {
         if (useLegacySSEEncoding(src0, dst)) {
             spew("%-11s" MEM_ob ", %s", legacySSEOpName(name),
                  ADDR_ob(offset, base), nameFPReg(dst));
             m_formatter.legacySSEPrefix(ty);
             m_formatter.twoByteOp(opcode, offset, base, dst);
             return;
         }
@@ -4195,17 +4199,17 @@ private:
         } else {
             spew("%-11s" MEM_ob ", %s, %s", name,
                  ADDR_ob(offset, base), nameFPReg(src0), nameFPReg(dst));
         }
         m_formatter.twoByteOpVex(ty, opcode, offset, base, src0, dst);
     }
 
     void twoByteOpSimd_disp32(const char *name, VexOperandType ty, TwoByteOpcodeID opcode,
-                              int offset, RegisterID base, XMMRegisterID src0, XMMRegisterID dst)
+                              int32_t offset, RegisterID base, XMMRegisterID src0, XMMRegisterID dst)
     {
         if (useLegacySSEEncoding(src0, dst)) {
             spew("%-11s" MEM_o32b ", %s", legacySSEOpName(name), ADDR_o32b(offset, base), nameFPReg(dst));
             m_formatter.legacySSEPrefix(ty);
             m_formatter.twoByteOp_disp32(opcode, offset, base, dst);
             return;
         }
 
@@ -4214,17 +4218,17 @@ private:
         } else {
             spew("%-11s" MEM_o32b ", %s, %s", name,
                  ADDR_o32b(offset, base), nameFPReg(src0), nameFPReg(dst));
         }
         m_formatter.twoByteOpVex_disp32(ty, opcode, offset, base, src0, dst);
     }
 
     void twoByteOpSimd(const char *name, VexOperandType ty, TwoByteOpcodeID opcode,
-                       int offset, RegisterID base, RegisterID index, int scale,
+                       int32_t offset, RegisterID base, RegisterID index, int scale,
                        XMMRegisterID src0, XMMRegisterID dst)
     {
         if (useLegacySSEEncoding(src0, dst)) {
             spew("%-11s" MEM_obs ", %s", legacySSEOpName(name),
                  ADDR_obs(offset, base, index, scale), nameFPReg(dst));
             m_formatter.legacySSEPrefix(ty);
             m_formatter.twoByteOp(opcode, offset, base, index, scale, dst);
             return;
@@ -4339,17 +4343,17 @@ private:
             return;
         }
 
         spew("%-11s%s, %s", name, nameFPReg(rm), nameFPReg(reg));
         m_formatter.twoByteOpVex(ty, opcode, (RegisterID)rm, X86Registers::invalid_xmm, (XMMRegisterID)reg);
     }
 
     void twoByteOpSimdFlags(const char *name, VexOperandType ty, TwoByteOpcodeID opcode,
-                            int offset, RegisterID base, XMMRegisterID reg)
+                            int32_t offset, RegisterID base, XMMRegisterID reg)
     {
         if (useLegacySSEEncodingForOtherOutput()) {
             spew("%-11s" MEM_ob ", %s", legacySSEOpName(name),
                  ADDR_ob(offset, base), nameFPReg(reg));
             m_formatter.legacySSEPrefix(ty);
             m_formatter.twoByteOp(opcode, offset, base, reg);
             return;
         }
@@ -4371,17 +4375,17 @@ private:
         }
 
         spew("%-11s%s, %s, %s", name, nameFPReg(rm), nameFPReg(src0), nameFPReg(dst));
         m_formatter.threeByteOpVex(ty, opcode, escape, (RegisterID)rm, src0, dst);
     }
 
     void threeByteOpSimd(const char *name, VexOperandType ty, ThreeByteOpcodeID opcode,
                          ThreeByteEscape escape,
-                         int offset, RegisterID base, XMMRegisterID src0, XMMRegisterID dst)
+                         int32_t offset, RegisterID base, XMMRegisterID src0, XMMRegisterID dst)
     {
         if (useLegacySSEEncoding(src0, dst)) {
             spew("%-11s" MEM_ob ", %s", legacySSEOpName(name),
                  ADDR_ob(offset, base), nameFPReg(dst));
             m_formatter.legacySSEPrefix(ty);
             m_formatter.threeByteOp(opcode, escape, offset, base, dst);
             return;
         }
@@ -4420,17 +4424,17 @@ private:
 
         spew("vblendvps  %s, %s, %s, %s",
              nameFPReg(mask), nameFPReg(rm), nameFPReg(src0), nameFPReg(dst));
         // Even though a "ps" instruction, vblendv is encoded with the "pd" prefix.
         m_formatter.vblendvOpVex(VEX_PD, OP3_VBLENDVPS_VdqWdq, ESCAPE_VBLENDVPS,
                                  mask, (RegisterID)rm, src0, dst);
     }
 
-    void vblendvOpSimd(XMMRegisterID mask, int offset, RegisterID base, XMMRegisterID src0, XMMRegisterID dst)
+    void vblendvOpSimd(XMMRegisterID mask, int32_t offset, RegisterID base, XMMRegisterID src0, XMMRegisterID dst)
     {
         if (useLegacySSEEncodingForVblendv(mask, src0, dst)) {
             spew("blendvps   " MEM_ob ", %s", ADDR_ob(offset, base), nameFPReg(dst));
             // Even though a "ps" instruction, vblendv is encoded with the "pd" prefix.
             m_formatter.legacySSEPrefix(VEX_PD);
             m_formatter.threeByteOp(OP3_BLENDVPS_VdqWdq, ESCAPE_BLENDVPS, offset, base, dst);
             return;
         }
@@ -4503,41 +4507,41 @@ private:
         void oneByteOp(OneByteOpcodeID opcode, RegisterID rm, int reg)
         {
             m_buffer.ensureSpace(maxInstructionSize);
             emitRexIfNeeded(reg, 0, rm);
             m_buffer.putByteUnchecked(opcode);
             registerModRM(rm, reg);
         }
 
-        void oneByteOp(OneByteOpcodeID opcode, int offset, RegisterID base, int reg)
+        void oneByteOp(OneByteOpcodeID opcode, int32_t offset, RegisterID base, int reg)
         {
             m_buffer.ensureSpace(maxInstructionSize);
             emitRexIfNeeded(reg, 0, base);
             m_buffer.putByteUnchecked(opcode);
             memoryModRM(offset, base, reg);
         }
 
-        void oneByteOp_disp32(OneByteOpcodeID opcode, int offset, RegisterID base, int reg)
+        void oneByteOp_disp32(OneByteOpcodeID opcode, int32_t offset, RegisterID base, int reg)
         {
             m_buffer.ensureSpace(maxInstructionSize);
             emitRexIfNeeded(reg, 0, base);
             m_buffer.putByteUnchecked(opcode);
             memoryModRM_disp32(offset, base, reg);
         }
 
-        void oneByteOp(OneByteOpcodeID opcode, int offset, RegisterID base, RegisterID index, int scale, int reg)
+        void oneByteOp(OneByteOpcodeID opcode, int32_t offset, RegisterID base, RegisterID index, int scale, int reg)
         {
             m_buffer.ensureSpace(maxInstructionSize);
             emitRexIfNeeded(reg, index, base);
             m_buffer.putByteUnchecked(opcode);
             memoryModRM(offset, base, index, scale, reg);
         }
 
-        void oneByteOp_disp32(OneByteOpcodeID opcode, int offset, RegisterID index, int scale, int reg)
+        void oneByteOp_disp32(OneByteOpcodeID opcode, int32_t offset, RegisterID index, int scale, int reg)
         {
             m_buffer.ensureSpace(maxInstructionSize);
             emitRexIfNeeded(reg, index, 0);
             m_buffer.putByteUnchecked(opcode);
             memoryModRM_disp32(offset, index, scale, reg);
         }
 
         void oneByteOp(OneByteOpcodeID opcode, const void* address, int reg)
@@ -4617,65 +4621,65 @@ private:
         {
             int r = (reg >> 3), x = 0, b = (rm >> 3);
             int m = 1; // 0x0F
             int w = 0, v = src0, l = 0;
             threeOpVex(ty, r, x, b, m, w, v, l, opcode);
             registerModRM(rm, reg);
         }
 
-        void twoByteOp(TwoByteOpcodeID opcode, int offset, RegisterID base, int reg)
+        void twoByteOp(TwoByteOpcodeID opcode, int32_t offset, RegisterID base, int reg)
         {
             m_buffer.ensureSpace(maxInstructionSize);
             emitRexIfNeeded(reg, 0, base);
             m_buffer.putByteUnchecked(OP_2BYTE_ESCAPE);
             m_buffer.putByteUnchecked(opcode);
             memoryModRM(offset, base, reg);
         }
 
         void twoByteOpVex(VexOperandType ty, TwoByteOpcodeID opcode,
-                          int offset, RegisterID base, XMMRegisterID src0, int reg)
+                          int32_t offset, RegisterID base, XMMRegisterID src0, int reg)
         {
             int r = (reg >> 3), x = 0, b = (base >> 3);
             int m = 1; // 0x0F
             int w = 0, v = src0, l = 0;
             threeOpVex(ty, r, x, b, m, w, v, l, opcode);
             memoryModRM(offset, base, reg);
         }
 
-        void twoByteOp_disp32(TwoByteOpcodeID opcode, int offset, RegisterID base, int reg)
+        void twoByteOp_disp32(TwoByteOpcodeID opcode, int32_t offset, RegisterID base, int reg)
         {
             m_buffer.ensureSpace(maxInstructionSize);
             emitRexIfNeeded(reg, 0, base);
             m_buffer.putByteUnchecked(OP_2BYTE_ESCAPE);
             m_buffer.putByteUnchecked(opcode);
             memoryModRM_disp32(offset, base, reg);
         }
 
         void twoByteOpVex_disp32(VexOperandType ty, TwoByteOpcodeID opcode,
-                                 int offset, RegisterID base, XMMRegisterID src0, int reg)
+                                 int32_t offset, RegisterID base, XMMRegisterID src0, int reg)
         {
             int r = (reg >> 3), x = 0, b = (base >> 3);
             int m = 1; // 0x0F
             int w = 0, v = src0, l = 0;
             threeOpVex(ty, r, x, b, m, w, v, l, opcode);
             memoryModRM_disp32(offset, base, reg);
         }
 
-        void twoByteOp(TwoByteOpcodeID opcode, int offset, RegisterID base, RegisterID index, int scale, int reg)
+        void twoByteOp(TwoByteOpcodeID opcode, int32_t offset, RegisterID base, RegisterID index, int scale, int reg)
         {
             m_buffer.ensureSpace(maxInstructionSize);
             emitRexIfNeeded(reg, index, base);
             m_buffer.putByteUnchecked(OP_2BYTE_ESCAPE);
             m_buffer.putByteUnchecked(opcode);
             memoryModRM(offset, base, index, scale, reg);
         }
 
         void twoByteOpVex(VexOperandType ty, TwoByteOpcodeID opcode,
-                          int offset, RegisterID base, RegisterID index, int scale,
+                          int32_t offset, RegisterID base, RegisterID index, int scale,
                           XMMRegisterID src0, int reg)
         {
             int r = (reg >> 3), x = (index >> 3), b = (base >> 3);
             int m = 1; // 0x0F
             int w = 0, v = src0, l = 0;
             threeOpVex(ty, r, x, b, m, w, v, l, opcode);
             memoryModRM(offset, base, index, scale, reg);
         }
@@ -4718,28 +4722,28 @@ private:
               case 0x38: m = 2; break; // 0x0F 0x38
               case 0x3A: m = 3; break; // 0x0F 0x3A
               default: MOZ_CRASH("unexpected escape");
             }
             threeOpVex(ty, r, x, b, m, w, v, l, opcode);
             registerModRM(rm, reg);
         }
 
-        void threeByteOp(ThreeByteOpcodeID opcode, ThreeByteEscape escape, int offset, RegisterID base, int reg)
+        void threeByteOp(ThreeByteOpcodeID opcode, ThreeByteEscape escape, int32_t offset, RegisterID base, int reg)
         {
             m_buffer.ensureSpace(maxInstructionSize);
             emitRexIfNeeded(reg, 0, base);
             m_buffer.putByteUnchecked(OP_2BYTE_ESCAPE);
             m_buffer.putByteUnchecked(escape);
             m_buffer.putByteUnchecked(opcode);
             memoryModRM(offset, base, reg);
         }
 
         void threeByteOpVex(VexOperandType ty, ThreeByteOpcodeID opcode, ThreeByteEscape escape,
-                            int offset, RegisterID base, XMMRegisterID src0, int reg)
+                            int32_t offset, RegisterID base, XMMRegisterID src0, int reg)
         {
             int r = (reg >> 3), x = 0, b = (base >> 3);
             int m = 0, w = 0, v = src0, l = 0;
             switch (escape) {
               case 0x38: m = 2; break; // 0x0F 0x38
               case 0x3A: m = 3; break; // 0x0F 0x3A
               default: MOZ_CRASH("unexpected escape");
             }
@@ -4778,32 +4782,32 @@ private:
             int m = 0, w = 0, v = src0, l = 0;
             switch (escape) {
               case 0x38: m = 2; break; // 0x0F 0x38
               case 0x3A: m = 3; break; // 0x0F 0x3A
               default: MOZ_CRASH("unexpected escape");
             }
             threeOpVex(ty, r, x, b, m, w, v, l, opcode);
             registerModRM(rm, reg);
-            immediate8(mask << 4);
+            immediate8u(mask << 4);
         }
 
         void vblendvOpVex(VexOperandType ty, ThreeByteOpcodeID opcode, ThreeByteEscape escape,
-                          XMMRegisterID mask, int offset, RegisterID base, XMMRegisterID src0, int reg)
+                          XMMRegisterID mask, int32_t offset, RegisterID base, XMMRegisterID src0, int reg)
         {
             int r = (reg >> 3), x = 0, b = (base >> 3);
             int m = 0, w = 0, v = src0, l = 0;
             switch (escape) {
               case 0x38: m = 2; break; // 0x0F 0x38
               case 0x3A: m = 3; break; // 0x0F 0x3A
               default: MOZ_CRASH("unexpected escape");
             }
             threeOpVex(ty, r, x, b, m, w, v, l, opcode);
             memoryModRM(offset, base, reg);
-            immediate8(mask << 4);
+            immediate8u(mask << 4);
         }
 
 #ifdef JS_CODEGEN_X64
         // Quad-word-sized operands:
         //
         // Used to format 64-bit operantions, planting a REX.w prefix.  When
         // planting d64 or f64 instructions, not requiring a REX.w prefix, the
         // normal (non-'64'-postfixed) formatters should be used.
@@ -4825,33 +4829,33 @@ private:
         void oneByteOp64(OneByteOpcodeID opcode, RegisterID rm, int reg)
         {
             m_buffer.ensureSpace(maxInstructionSize);
             emitRexW(reg, 0, rm);
             m_buffer.putByteUnchecked(opcode);
             registerModRM(rm, reg);
         }
 
-        void oneByteOp64(OneByteOpcodeID opcode, int offset, RegisterID base, int reg)
+        void oneByteOp64(OneByteOpcodeID opcode, int32_t offset, RegisterID base, int reg)
         {
             m_buffer.ensureSpace(maxInstructionSize);
             emitRexW(reg, 0, base);
             m_buffer.putByteUnchecked(opcode);
             memoryModRM(offset, base, reg);
         }
 
-        void oneByteOp64_disp32(OneByteOpcodeID opcode, int offset, RegisterID base, int reg)
+        void oneByteOp64_disp32(OneByteOpcodeID opcode, int32_t offset, RegisterID base, int reg)
         {
             m_buffer.ensureSpace(maxInstructionSize);
             emitRexW(reg, 0, base);
             m_buffer.putByteUnchecked(opcode);
             memoryModRM_disp32(offset, base, reg);
         }
 
-        void oneByteOp64(OneByteOpcodeID opcode, int offset, RegisterID base, RegisterID index, int scale, int reg)
+        void oneByteOp64(OneByteOpcodeID opcode, int32_t offset, RegisterID base, RegisterID index, int scale, int reg)
         {
             m_buffer.ensureSpace(maxInstructionSize);
             emitRexW(reg, index, base);
             m_buffer.putByteUnchecked(opcode);
             memoryModRM(offset, base, index, scale, reg);
         }
 
         void oneByteOp64(OneByteOpcodeID opcode, const void* address, int reg)
@@ -4919,39 +4923,39 @@ private:
         void oneByteOp8_norex(OneByteOpcodeID opcode, RegisterID rm, GroupOpcodeID groupOp)
         {
             MOZ_ASSERT(!regRequiresRex(rm));
             m_buffer.ensureSpace(maxInstructionSize);
             m_buffer.putByteUnchecked(opcode);
             registerModRM(rm, groupOp);
         }
 
-        void oneByteOp8(OneByteOpcodeID opcode, int offset, RegisterID base, int reg)
+        void oneByteOp8(OneByteOpcodeID opcode, int32_t offset, RegisterID base, int reg)
         {
 #ifdef JS_CODEGEN_X86
             MOZ_ASSERT(!ByteRegRequiresRex(reg));
 #endif
             m_buffer.ensureSpace(maxInstructionSize);
             emitRexIf(ByteRegRequiresRex(reg), reg, 0, base);
             m_buffer.putByteUnchecked(opcode);
             memoryModRM(offset, base, reg);
         }
 
-        void oneByteOp8_disp32(OneByteOpcodeID opcode, int offset, RegisterID base, int reg)
+        void oneByteOp8_disp32(OneByteOpcodeID opcode, int32_t offset, RegisterID base, int reg)
         {
 #ifdef JS_CODEGEN_X86
             MOZ_ASSERT(!ByteRegRequiresRex(reg));
 #endif
             m_buffer.ensureSpace(maxInstructionSize);
             emitRexIf(ByteRegRequiresRex(reg), reg, 0, base);
             m_buffer.putByteUnchecked(opcode);
             memoryModRM_disp32(offset, base, reg);
         }
 
-        void oneByteOp8(OneByteOpcodeID opcode, int offset, RegisterID base, RegisterID index, int scale, int reg)
+        void oneByteOp8(OneByteOpcodeID opcode, int32_t offset, RegisterID base, RegisterID index, int scale, int reg)
         {
 #ifdef JS_CODEGEN_X86
             MOZ_ASSERT(!ByteRegRequiresRex(reg));
 #endif
             m_buffer.ensureSpace(maxInstructionSize);
             emitRexIf(ByteRegRequiresRex(reg), reg, index, base);
             m_buffer.putByteUnchecked(opcode);
             memoryModRM(offset, base, index, scale, reg);
@@ -5000,27 +5004,59 @@ private:
         }
 
         // Immediates:
         //
         // An immedaite should be appended where appropriate after an op has
         // been emitted.  The writes are unchecked since the opcode formatters
         // above will have ensured space.
 
-        void immediate8(int imm)
+        // A signed 8-bit immediate.
+        void immediate8s(int32_t imm)
+        {
+            MOZ_ASSERT(CAN_SIGN_EXTEND_8_32(imm));
+            m_buffer.putByteUnchecked(imm);
+        }
+
+        // An unsigned 8-bit immediate.
+        void immediate8u(uint32_t imm)
+        {
+            MOZ_ASSERT(CAN_ZERO_EXTEND_8_32(imm));
+            m_buffer.putByteUnchecked(int32_t(imm));
+        }
+
+        // An 8-bit immediate with is either signed or unsigned, for use in
+        // instructions which actually only operate on 8 bits.
+        void immediate8(int32_t imm)
         {
             m_buffer.putByteUnchecked(imm);
         }
 
-        void immediate16(int imm)
+        // A signed 16-bit immediate.
+        void immediate16s(int32_t imm)
+        {
+            MOZ_ASSERT(CAN_SIGN_EXTEND_16_32(imm));
+            m_buffer.putShortUnchecked(imm);
+        }
+
+        // An unsigned 16-bit immediate.
+        void immediate16u(int32_t imm)
+        {
+            MOZ_ASSERT(CAN_ZERO_EXTEND_16_32(imm));
+            m_buffer.putShortUnchecked(imm);
+        }
+
+        // A 16-bit immediate with is either signed or unsigned, for use in
+        // instructions which actually only operate on 16 bits.
+        void immediate16(int32_t imm)
         {
             m_buffer.putShortUnchecked(imm);
         }
 
-        void immediate32(int imm)
+        void immediate32(int32_t imm)
         {
             m_buffer.putIntUnchecked(imm);
         }
 
         void immediate64(int64_t imm)
         {
             m_buffer.putInt64Unchecked(imm);
         }
@@ -5177,17 +5213,17 @@ private:
             m_buffer.putByteUnchecked((scale << 6) | ((index & 7) << 3) | (base & 7));
         }
 
         void registerModRM(RegisterID rm, int reg)
         {
             putModRm(ModRmRegister, rm, reg);
         }
 
-        void memoryModRM(int offset, RegisterID base, int reg)
+        void memoryModRM(int32_t offset, RegisterID base, int reg)
         {
             // A base of esp or r12 would be interpreted as a sib, so force a
             // sib with no index & put the base in there.
 #ifdef JS_CODEGEN_X64
             if ((base == hasSib) || (base == hasSib2))
 #else
             if (base == hasSib)
 #endif
@@ -5213,17 +5249,17 @@ private:
                     m_buffer.putByteUnchecked(offset);
                 } else {
                     putModRm(ModRmMemoryDisp32, base, reg);
                     m_buffer.putIntUnchecked(offset);
                 }
             }
         }
 
-        void memoryModRM_disp32(int offset, RegisterID base, int reg)
+        void memoryModRM_disp32(int32_t offset, RegisterID base, int reg)
         {
             // A base of esp or r12 would be interpreted as a sib, so force a
             // sib with no index & put the base in there.
 #ifdef JS_CODEGEN_X64
             if ((base == hasSib) || (base == hasSib2))
 #else
             if (base == hasSib)
 #endif
@@ -5231,17 +5267,17 @@ private:
                 putModRmSib(ModRmMemoryDisp32, base, noIndex, 0, reg);
                 m_buffer.putIntUnchecked(offset);
             } else {
                 putModRm(ModRmMemoryDisp32, base, reg);
                 m_buffer.putIntUnchecked(offset);
             }
         }
 
-        void memoryModRM(int offset, RegisterID base, RegisterID index, int scale, int reg)
+        void memoryModRM(int32_t offset, RegisterID base, RegisterID index, int scale, int reg)
         {
             MOZ_ASSERT(index != noIndex);
 
 #ifdef JS_CODEGEN_X64
             if (!offset && (base != noBase) && (base != noBase2))
 #else
             if (!offset && (base != noBase))
 #endif
@@ -5250,17 +5286,17 @@ private:
                 putModRmSib(ModRmMemoryDisp8, base, index, scale, reg);
                 m_buffer.putByteUnchecked(offset);
             } else {
                 putModRmSib(ModRmMemoryDisp32, base, index, scale, reg);
                 m_buffer.putIntUnchecked(offset);
             }
         }
 
-        void memoryModRM_disp32(int offset, RegisterID index, int scale, int reg)
+        void memoryModRM_disp32(int32_t offset, RegisterID index, int scale, int reg)
         {
             MOZ_ASSERT(index != noIndex);
 
             // NB: the base-less memoryModRM overloads generate different code
             // then the base-full memoryModRM overloads in the base == noBase
             // case. The base-less overloads assume that the desired effective
             // address is:
             //
--- a/js/src/jit/x64/Assembler-x64.h
+++ b/js/src/jit/x64/Assembler-x64.h
@@ -499,23 +499,23 @@ class Assembler : public AssemblerX86Sha
           case Operand::MEM_REG_DISP:
             masm.subq_rm(src.code(), dest.disp(), dest.base());
             break;
           default:
             MOZ_CRASH("unexpected operand kind");
         }
     }
     void shlq(Imm32 imm, Register dest) {
-        masm.shlq_i8r(imm.value, dest.code());
+        masm.shlq_ir(imm.value, dest.code());
     }
     void shrq(Imm32 imm, Register dest) {
-        masm.shrq_i8r(imm.value, dest.code());
+        masm.shrq_ir(imm.value, dest.code());
     }
     void sarq(Imm32 imm, Register dest) {
-        masm.sarq_i8r(imm.value, dest.code());
+        masm.sarq_ir(imm.value, dest.code());
     }
     void orq(Imm32 imm, Register dest) {
         masm.orq_ir(imm.value, dest.code());
     }
     void orq(Register src, Register dest) {
         masm.orq_rr(src.code(), dest.code());
     }
     void orq(const Operand &src, Register dest) {