[arm] Use preindexed STR instruction instead of separate STR and SUB in asm_pusharg
[arm] Use preindexed STR instruction instead of separate STR and SUB in asm_pusharg
--- a/js/src/nanojit/NativeARM.cpp
+++ b/js/src/nanojit/NativeARM.cpp
@@ -655,38 +655,37 @@ Assembler::asm_mmq(Register rd, int dd,
LDR(t, rs, ds);
}
void
Assembler::asm_pusharg(LInsp arg)
{
Reservation* argRes = getresv(arg);
bool quad = arg->isQuad();
- intptr_t stack_growth = quad ? 8 : 4;
-
- int d = 0;
if (argRes && argRes->reg != UnknownReg) {
if (!quad) {
- STR(argRes->reg, SP, 0);
+ STR_preindex(argRes->reg, SP, -4);
} else {
FSTD(argRes->reg, SP, 0);
+ SUBi(SP, 8);
}
} else {
int d = findMemFor(arg);
if (!quad) {
- STR(Scratch, SP, 0);
+ STR_preindex(Scratch, SP, -4);
LDR(Scratch, FP, d);
} else {
- asm_mmq(SP, 0, FP, disp(argRes));
+ STR_preindex(Scratch, SP, -4);
+ LDR(Scratch, FP, d+4);
+ STR_preindex(Scratch, SP, -4);
+ LDR(Scratch, FP, d);
}
}
-
- SUBi(SP, stack_growth);
}
void
Assembler::nativePageReset()
{
_nSlot = 0;
_nExitSlot = 0;
}
--- a/js/src/nanojit/NativeARM.h
+++ b/js/src/nanojit/NativeARM.h
@@ -500,17 +500,17 @@ typedef enum {
NanoAssert((_off)<4096); \
*(--_nIns) = (NIns)( COND_AL | (0x59<<20) | ((_b)<<16) | ((_d)<<12) | ((_off)&0xFFF) ); \
} else { \
if (_chk) underrunProtect(4+LD32_size); \
*(--_nIns) = (NIns)( COND_AL | (0x79<<20) | ((_b)<<16) | ((_d)<<12) | Scratch ); \
LD32_nochk(Scratch, _off); \
} \
} \
- asm_output3("ldr %s,%d(%s)",gpn((_d)),(_off),gpn((_b))); \
+ asm_output3("ldr %s, [%s, #%d]",gpn(_d),gpn(_b),(_off)); \
} while(0)
#define LDR(_d,_b,_off) LDR_chk(_d,_b,_off,0)
#define LDR_nochk(_d,_b,_off) LDR_chk(_d,_b,_off,1)
// i386 compat, for Assembler.cpp
#define LD(reg,offset,base) LDR_chk(reg,base,offset,1)
#define ST(base,offset,reg) STR(reg,base,offset)
@@ -542,17 +542,35 @@ typedef enum {
asm_output3("ldrb %s,%d(%s)", gpn(_d),(_off),gpn(_b)); \
} while(0)
#define STR(_d,_n,_off) do { \
NanoAssert(!IsFpReg(_d) && isS12(_off)); \
underrunProtect(4); \
if ((_off)<0) *(--_nIns) = (NIns)( COND_AL | (0x50<<20) | ((_n)<<16) | ((_d)<<12) | ((-(_off))&0xFFF) ); \
else *(--_nIns) = (NIns)( COND_AL | (0x58<<20) | ((_n)<<16) | ((_d)<<12) | ((_off)&0xFFF) ); \
- asm_output3("str %s, %d(%s)",gpn(_d), (_off), gpn(_n)); \
+ asm_output3("str %s, [%s, #%d]", gpn(_d), gpn(_n), (_off)); \
+ } while(0)
+
+// Rd += _off; [Rd] = Rn
+#define STR_preindex(_d,_n,_off) do { \
+ NanoAssert(!IsFpReg(_d) && isS12(_off)); \
+ underrunProtect(4); \
+ if ((_off)<0) *(--_nIns) = (NIns)( COND_AL | (0x52<<20) | ((_n)<<16) | ((_d)<<12) | ((-(_off))&0xFFF) ); \
+ else *(--_nIns) = (NIns)( COND_AL | (0x5A<<20) | ((_n)<<16) | ((_d)<<12) | ((_off)&0xFFF) ); \
+ asm_output3("str %s, [%s, #%d]", gpn(_d), gpn(_n), (_off)); \
+ } while(0)
+
+// [Rd] = Rn ; Rd += _off
+#define STR_postindex(_d,_n,_off) do { \
+ NanoAssert(!IsFpReg(_d) && isS12(_off)); \
+ underrunProtect(4); \
+ if ((_off)<0) *(--_nIns) = (NIns)( COND_AL | (0x40<<20) | ((_n)<<16) | ((_d)<<12) | ((-(_off))&0xFFF) ); \
+ else *(--_nIns) = (NIns)( COND_AL | (0x48<<20) | ((_n)<<16) | ((_d)<<12) | ((_off)&0xFFF) ); \
+ asm_output3("str %s, [%s], %d", gpn(_d), gpn(_n), (_off)); \
} while(0)
#define LEA(_r,_d,_b) do { \
NanoAssert((_d)<=1020); \
NanoAssert(((_d)&3)==0); \
if (_b!=SP) NanoAssert(0); \
if ((_d)<256) { \