Bug 1626967: bump Cranelift to 6a68130d5b0296379fae0b8de5fbb8a1499b67a5; r=jseward
authorBenjamin Bouvier <benj@benj.me>
Fri, 10 Apr 2020 09:52:55 +0000
changeset 523385 ef939dda0a03ff2f8a908768ca972b7a0c42160d
parent 523384 2ea41c3546d3f529bb4a87c31862cdf048cc8284
child 523386 fb80ccae7376ec82a7a058de97c33f5c7b47f6cd
push id112619
push userbbouvier@mozilla.com
push dateFri, 10 Apr 2020 09:56:41 +0000
treeherderautoland@09c016706d3f [default view] [failures only]
perfherder[talos] [build metrics] [platform microbench] (compared to previous push)
reviewersjseward
bugs1626967
milestone77.0a1
first release with
nightly linux32
nightly linux64
nightly mac
nightly win32
nightly win64
last release without
nightly linux32
nightly linux64
nightly mac
nightly win32
nightly win64
Bug 1626967: bump Cranelift to 6a68130d5b0296379fae0b8de5fbb8a1499b67a5; r=jseward Differential Revision: https://phabricator.services.mozilla.com/D69977
.cargo/config.in
Cargo.lock
Cargo.toml
js/src/wasm/cranelift/Cargo.toml
third_party/rust/cranelift-bforest/.cargo-checksum.json
third_party/rust/cranelift-bforest/Cargo.toml
third_party/rust/cranelift-codegen-meta/.cargo-checksum.json
third_party/rust/cranelift-codegen-meta/Cargo.toml
third_party/rust/cranelift-codegen-meta/src/isa/riscv/recipes.rs
third_party/rust/cranelift-codegen-meta/src/isa/x86/encodings.rs
third_party/rust/cranelift-codegen-meta/src/isa/x86/opcodes.rs
third_party/rust/cranelift-codegen-meta/src/isa/x86/recipes.rs
third_party/rust/cranelift-codegen-meta/src/shared/instructions.rs
third_party/rust/cranelift-codegen-shared/.cargo-checksum.json
third_party/rust/cranelift-codegen-shared/Cargo.toml
third_party/rust/cranelift-codegen/.cargo-checksum.json
third_party/rust/cranelift-codegen/Cargo.toml
third_party/rust/cranelift-codegen/src/binemit/memorysink.rs
third_party/rust/cranelift-codegen/src/binemit/mod.rs
third_party/rust/cranelift-codegen/src/isa/mod.rs
third_party/rust/cranelift-codegen/src/isa/x86/binemit.rs
third_party/rust/cranelift-codegen/src/isa/x86/enc_tables.rs
third_party/rust/cranelift-codegen/src/isa/x86/fde.rs
third_party/rust/cranelift-codegen/src/isa/x86/mod.rs
third_party/rust/cranelift-codegen/src/simple_preopt.rs
third_party/rust/cranelift-entity/.cargo-checksum.json
third_party/rust/cranelift-entity/Cargo.toml
third_party/rust/cranelift-frontend/.cargo-checksum.json
third_party/rust/cranelift-frontend/Cargo.toml
third_party/rust/cranelift-frontend/src/frontend.rs
third_party/rust/cranelift-frontend/src/ssa.rs
third_party/rust/cranelift-wasm/.cargo-checksum.json
third_party/rust/cranelift-wasm/Cargo.toml
third_party/rust/cranelift-wasm/src/code_translator.rs
--- a/.cargo/config.in
+++ b/.cargo/config.in
@@ -50,17 +50,17 @@ rev = "3541e3818fdc7c2a24f87e3459151a4ce
 [source."https://github.com/djg/cubeb-pulse-rs"]
 git = "https://github.com/djg/cubeb-pulse-rs"
 replace-with = "vendored-sources"
 rev = "72f813a03cefbdf8e2c58c7410f3556c79429a06"
 
 [source."https://github.com/bytecodealliance/wasmtime"]
 git = "https://github.com/bytecodealliance/wasmtime"
 replace-with = "vendored-sources"
-rev = "5cfcbeb59d477e028c6fb312f1cf63aa711fcc3c"
+rev = "6a68130d5b0296379fae0b8de5fbb8a1499b67a5"
 
 [source."https://github.com/badboy/failure"]
 git = "https://github.com/badboy/failure"
 replace-with = "vendored-sources"
 rev = "64af847bc5fdcb6d2438bec8a6030812a80519a5"
 
 [source."https://github.com/PLSysSec/rlbox_lucet_sandbox/"]
 git = "https://github.com/PLSysSec/rlbox_lucet_sandbox/"
--- a/Cargo.lock
+++ b/Cargo.lock
@@ -710,80 +710,80 @@ version = "0.1.5"
 source = "registry+https://github.com/rust-lang/crates.io-index"
 checksum = "49726015ab0ca765144fcca61e4a7a543a16b795a777fa53f554da2fffff9a94"
 dependencies = [
  "cose",
 ]
 
 [[package]]
 name = "cranelift-bforest"
-version = "0.60.0"
-source = "git+https://github.com/bytecodealliance/wasmtime?rev=5cfcbeb59d477e028c6fb312f1cf63aa711fcc3c#5cfcbeb59d477e028c6fb312f1cf63aa711fcc3c"
-dependencies = [
- "cranelift-entity 0.60.0",
+version = "0.62.0"
+source = "git+https://github.com/bytecodealliance/wasmtime?rev=6a68130d5b0296379fae0b8de5fbb8a1499b67a5#6a68130d5b0296379fae0b8de5fbb8a1499b67a5"
+dependencies = [
+ "cranelift-entity 0.62.0",
 ]
 
 [[package]]
 name = "cranelift-codegen"
-version = "0.60.0"
-source = "git+https://github.com/bytecodealliance/wasmtime?rev=5cfcbeb59d477e028c6fb312f1cf63aa711fcc3c#5cfcbeb59d477e028c6fb312f1cf63aa711fcc3c"
+version = "0.62.0"
+source = "git+https://github.com/bytecodealliance/wasmtime?rev=6a68130d5b0296379fae0b8de5fbb8a1499b67a5#6a68130d5b0296379fae0b8de5fbb8a1499b67a5"
 dependencies = [
  "byteorder",
  "cranelift-bforest",
  "cranelift-codegen-meta",
  "cranelift-codegen-shared",
- "cranelift-entity 0.60.0",
+ "cranelift-entity 0.62.0",
  "log",
  "smallvec 1.2.0",
  "target-lexicon 0.10.0",
  "thiserror",
 ]
 
 [[package]]
 name = "cranelift-codegen-meta"
-version = "0.60.0"
-source = "git+https://github.com/bytecodealliance/wasmtime?rev=5cfcbeb59d477e028c6fb312f1cf63aa711fcc3c#5cfcbeb59d477e028c6fb312f1cf63aa711fcc3c"
+version = "0.62.0"
+source = "git+https://github.com/bytecodealliance/wasmtime?rev=6a68130d5b0296379fae0b8de5fbb8a1499b67a5#6a68130d5b0296379fae0b8de5fbb8a1499b67a5"
 dependencies = [
  "cranelift-codegen-shared",
- "cranelift-entity 0.60.0",
+ "cranelift-entity 0.62.0",
 ]
 
 [[package]]
 name = "cranelift-codegen-shared"
-version = "0.60.0"
-source = "git+https://github.com/bytecodealliance/wasmtime?rev=5cfcbeb59d477e028c6fb312f1cf63aa711fcc3c#5cfcbeb59d477e028c6fb312f1cf63aa711fcc3c"
+version = "0.62.0"
+source = "git+https://github.com/bytecodealliance/wasmtime?rev=6a68130d5b0296379fae0b8de5fbb8a1499b67a5#6a68130d5b0296379fae0b8de5fbb8a1499b67a5"
 
 [[package]]
 name = "cranelift-entity"
 version = "0.41.0"
 source = "git+https://github.com/PLSysSec/lucet_sandbox_compiler?rev=5e870faf6f95d79d11efc813e56370ad124bbed5#5e870faf6f95d79d11efc813e56370ad124bbed5"
 
 [[package]]
 name = "cranelift-entity"
-version = "0.60.0"
-source = "git+https://github.com/bytecodealliance/wasmtime?rev=5cfcbeb59d477e028c6fb312f1cf63aa711fcc3c#5cfcbeb59d477e028c6fb312f1cf63aa711fcc3c"
+version = "0.62.0"
+source = "git+https://github.com/bytecodealliance/wasmtime?rev=6a68130d5b0296379fae0b8de5fbb8a1499b67a5#6a68130d5b0296379fae0b8de5fbb8a1499b67a5"
 
 [[package]]
 name = "cranelift-frontend"
-version = "0.60.0"
-source = "git+https://github.com/bytecodealliance/wasmtime?rev=5cfcbeb59d477e028c6fb312f1cf63aa711fcc3c#5cfcbeb59d477e028c6fb312f1cf63aa711fcc3c"
+version = "0.62.0"
+source = "git+https://github.com/bytecodealliance/wasmtime?rev=6a68130d5b0296379fae0b8de5fbb8a1499b67a5#6a68130d5b0296379fae0b8de5fbb8a1499b67a5"
 dependencies = [
  "cranelift-codegen",
  "log",
  "smallvec 1.2.0",
  "target-lexicon 0.10.0",
 ]
 
 [[package]]
 name = "cranelift-wasm"
-version = "0.60.0"
-source = "git+https://github.com/bytecodealliance/wasmtime?rev=5cfcbeb59d477e028c6fb312f1cf63aa711fcc3c#5cfcbeb59d477e028c6fb312f1cf63aa711fcc3c"
+version = "0.62.0"
+source = "git+https://github.com/bytecodealliance/wasmtime?rev=6a68130d5b0296379fae0b8de5fbb8a1499b67a5#6a68130d5b0296379fae0b8de5fbb8a1499b67a5"
 dependencies = [
  "cranelift-codegen",
- "cranelift-entity 0.60.0",
+ "cranelift-entity 0.62.0",
  "cranelift-frontend",
  "log",
  "thiserror",
  "wasmparser 0.51.4",
 ]
 
 [[package]]
 name = "crc32fast"
--- a/Cargo.toml
+++ b/Cargo.toml
@@ -71,13 +71,13 @@ rlbox_lucet_sandbox = { git = "https://g
 nix = { git = "https://github.com/shravanrn/nix/", branch = "r0.13.1", rev="4af6c367603869a30fddb5ffb0aba2b9477ba92e" }
 spirv_cross = { git = "https://github.com/kvark/spirv_cross", branch = "wgpu", rev = "9cb4de489bf80b2b23efffe5a79afb7db6247ba4" }
 # failure's backtrace feature might break our builds, see bug 1608157.
 failure = { git = "https://github.com/badboy/failure", rev = "64af847bc5fdcb6d2438bec8a6030812a80519a5" }
 failure_derive = { git = "https://github.com/badboy/failure", rev = "64af847bc5fdcb6d2438bec8a6030812a80519a5" }
 
 [patch.crates-io.cranelift-codegen]
 git = "https://github.com/bytecodealliance/wasmtime"
-rev = "5cfcbeb59d477e028c6fb312f1cf63aa711fcc3c"
+rev = "6a68130d5b0296379fae0b8de5fbb8a1499b67a5"
 
 [patch.crates-io.cranelift-wasm]
 git = "https://github.com/bytecodealliance/wasmtime"
-rev = "5cfcbeb59d477e028c6fb312f1cf63aa711fcc3c"
+rev = "6a68130d5b0296379fae0b8de5fbb8a1499b67a5"
--- a/js/src/wasm/cranelift/Cargo.toml
+++ b/js/src/wasm/cranelift/Cargo.toml
@@ -8,18 +8,18 @@ edition = "2018"
 crate-type = ["rlib"]
 name = "baldrdash"
 
 [dependencies]
 # The build system redirects the versions of cranelift-codegen and
 # cranelift-wasm to pinned commits. If you want to update Cranelift in Gecko,
 # you should update the following $TOP_LEVEL/Cargo.toml file: look for the
 # revision (rev) hashes of both cranelift dependencies (codegen and wasm).
-cranelift-codegen = { version = "0.60.0", default-features = false }
-cranelift-wasm = "0.60.0"
+cranelift-codegen = { version = "0.62.0", default-features = false }
+cranelift-wasm = "0.62.0"
 log = { version = "0.4.6", default-features = false, features = ["release_max_level_info"] }
 env_logger = "0.6"
 smallvec = "1.0"
 
 [build-dependencies]
 bindgen = {version = "0.53", default-features = false} # disable `logging` to reduce code size
 
 [features]
--- a/third_party/rust/cranelift-bforest/.cargo-checksum.json
+++ b/third_party/rust/cranelift-bforest/.cargo-checksum.json
@@ -1,1 +1,1 @@
-{"files":{"Cargo.toml":"0590650ee92ca1c67e40e0c18f6861f588bac5240e96049af89a290d28b6c774","LICENSE":"268872b9816f90fd8e85db5a28d33f8150ebb8dd016653fb39ef1f94f2686bc5","README.md":"af367c67340fa7f6fb9a35b0aa637dcf303957f7ae7427a5f4f6356801c8bb04","src/lib.rs":"23a5c42d477197a947122e662068e681bb9ed31041c0b668c3267c3fce15d39e","src/map.rs":"a3b7f64cae7ec9c2a8038def315bcf90e8751552b1bc1c20b62fbb8c763866c4","src/node.rs":"28f7edd979f7b9712bc4ab30b0d2a1b8ad5485a4b1e8c09f3dcaf501b9b5ccd1","src/path.rs":"a86ee1c882c173e8af96fd53a416a0fb485dd3f045ac590ef313a9d9ecf90f56","src/pool.rs":"f6337b5417f7772e6878a160c1a40629199ff09997bdff18eb2a0ba770158600","src/set.rs":"281eb8b5ead1ffd395946464d881f9bb0e7fb61092aed701d72d2314b5f80994"},"package":null}
\ No newline at end of file
+{"files":{"Cargo.toml":"2826e4035b7d2cffaeb4b093fc3e33475fdd80c2cfae57cbdf1513918808477b","LICENSE":"268872b9816f90fd8e85db5a28d33f8150ebb8dd016653fb39ef1f94f2686bc5","README.md":"af367c67340fa7f6fb9a35b0aa637dcf303957f7ae7427a5f4f6356801c8bb04","src/lib.rs":"23a5c42d477197a947122e662068e681bb9ed31041c0b668c3267c3fce15d39e","src/map.rs":"a3b7f64cae7ec9c2a8038def315bcf90e8751552b1bc1c20b62fbb8c763866c4","src/node.rs":"28f7edd979f7b9712bc4ab30b0d2a1b8ad5485a4b1e8c09f3dcaf501b9b5ccd1","src/path.rs":"a86ee1c882c173e8af96fd53a416a0fb485dd3f045ac590ef313a9d9ecf90f56","src/pool.rs":"f6337b5417f7772e6878a160c1a40629199ff09997bdff18eb2a0ba770158600","src/set.rs":"281eb8b5ead1ffd395946464d881f9bb0e7fb61092aed701d72d2314b5f80994"},"package":null}
\ No newline at end of file
--- a/third_party/rust/cranelift-bforest/Cargo.toml
+++ b/third_party/rust/cranelift-bforest/Cargo.toml
@@ -1,18 +1,18 @@
 [package]
 authors = ["The Cranelift Project Developers"]
 name = "cranelift-bforest"
-version = "0.60.0"
+version = "0.62.0"
 description = "A forest of B+-trees"
 license = "Apache-2.0 WITH LLVM-exception"
 documentation = "https://docs.rs/cranelift-bforest"
 repository = "https://github.com/bytecodealliance/wasmtime"
 categories = ["no-std"]
 readme = "README.md"
 keywords = ["btree", "forest", "set", "map"]
 edition = "2018"
 
 [dependencies]
-cranelift-entity = { path = "../entity", version = "0.60.0", default-features = false }
+cranelift-entity = { path = "../entity", version = "0.62.0", default-features = false }
 
 [badges]
 maintenance = { status = "experimental" }
--- a/third_party/rust/cranelift-codegen-meta/.cargo-checksum.json
+++ b/third_party/rust/cranelift-codegen-meta/.cargo-checksum.json
@@ -1,1 +1,1 @@
-{"files":{"Cargo.toml":"f4c0e8f821dc23fac1e439ff0505fbfb4dd02cf631b629f1d5552b2a9f6dd3a4","LICENSE":"268872b9816f90fd8e85db5a28d33f8150ebb8dd016653fb39ef1f94f2686bc5","README.md":"b123f056d0d458396679c5f7f2a16d2762af0258fcda4ac14b6655a95e5a0022","src/cdsl/ast.rs":"84a4b7e3301e3249716958a7aa4ea5ba8c6172e3c02f57ee3880504c4433ff19","src/cdsl/cpu_modes.rs":"996e45b374cfe85ac47c8c86c4459fe4c04b3158102b4c63b6ee434d5eed6a9e","src/cdsl/encodings.rs":"d884a564815a03c23369bcf31d13b122ae5ba84d0c80eda9312f0c0a829bf794","src/cdsl/formats.rs":"63e638305aa3ca6dd409ddf0e5e9605eeac1cc2631103e42fc6cbc87703d9b63","src/cdsl/instructions.rs":"41e1a230501de3f0da3960d8aa375c8bcd60ec62ede94ad61806816acbd8009a","src/cdsl/isa.rs":"ccabd6848b69eb069c10db61c7e7f86080777495714bb53d03e663c40541be94","src/cdsl/mod.rs":"0aa827923bf4c45e5ee2359573bd863e00f474acd532739f49dcd74a27553882","src/cdsl/operands.rs":"1c3411504de9c83112ff48e0ff1cfbb2e4ba5a9a15c1716f411ef31a4df59899","src/cdsl/recipes.rs":"80b7cd87332229b569e38086ceee8d557e679b9a32ad2e50bdb15c33337c3418","src/cdsl/regs.rs":"466a42a43355fc7623fe5d8e8d330622207a3af6a80cb9367bc0f06e224c9ee0","src/cdsl/settings.rs":"e6fd9a31925743b93b11f09c9c8271bab6aa2430aa053a2601957b4487df7d77","src/cdsl/type_inference.rs":"1efca8a095ffc899b7527bda6b9d9378c73d7283f8dceaa4819e8af599f8be21","src/cdsl/types.rs":"ff764c9e9c29a05677bff6164e7bc25a0c32655052d77ae580536abba8b1713b","src/cdsl/typevar.rs":"c7e80a3c52755f2d91fb5c3d18413b7c97777bd54d1aece8a17d1bbd9944c46a","src/cdsl/xform.rs":"55da0c3f2403147b535ab6ae5d69c623fbe839edecf2a3af1de84420cd58402d","src/default_map.rs":"101bb0282a124f9c921f6bd095f529e8753621450d783c3273b0b0394c2c5c03","src/error.rs":"e9b11b2feb2d867b94c8810fdc5a6c4e0d9131604a0bfa5340ff2639a55100b4","src/gen_binemit.rs":"515e243420b30d1e01f8ea630282d9b6d78a715e1951f3f20392e19a48164442","src/gen_encodings.rs":"f00cded6b68a9b48c9e3cd39a8b6f0ba136f4062c8f8666109158a72c62c3ed1","src/gen_inst.rs":"b275053977c0239211c1df35253154ba4dce2519f506088e71104de37d3db862","src/gen_legalizer.rs":"ea229ab9393cc5ba2242f626e74c624ea59314535e74b26602dafb8e96481a72","src/gen_registers.rs":"a904119ed803c9de24dedd15149a65337ffc168bb1d63df53d7fdebfb5f4b158","src/gen_settings.rs":"f3cc3d31f6cc898f30606caf084f0de220db2d3b1b5e5e4145fa7c9a9a1597e2","src/gen_types.rs":"f6c090e1646a43bf2fe81ae0a7029cc6f7dc6d43285368f56d86c35a21c469a6","src/isa/arm32/mod.rs":"8e09ec1b3caf2d22dce8517b37c356047bfce9a6dea712467d867ed05c4bedaf","src/isa/arm64/mod.rs":"b01f030925d3f2af37d7df1b4a800eb7f0d24f74a46e9154fd8b6752643eb2d5","src/isa/mod.rs":"136141f99f217ba42b9e3f7f47238ab19cc974bb3bef2e2df7f7b5a683989d46","src/isa/riscv/encodings.rs":"8abb1968d917588bc5fc5f5be6dd66bdec23ac456ba65f8138237c8e891e843c","src/isa/riscv/mod.rs":"a7b461a30bbfbc1e3b33645422ff40d5b1761c30cb5d4a8aa12e9a3b7f7aee51","src/isa/riscv/recipes.rs":"c9424cffed54cc4d328879a4613b9f6a2c2b7cde7e6e17b4fccd5f661aaf92f2","src/isa/x86/encodings.rs":"cbf3e7834c7d29de8f3faa4c70dad23167ae22d02fba5d7d518779b34535393d","src/isa/x86/instructions.rs":"3c1482583b031d2663b31ee8784f0cb61c8abef995afc7c8f8a6e7be010a2ba8","src/isa/x86/legalize.rs":"5b654c2410ab384cfb20815f1114af76a7967472a45b8d60232ddce9d9921682","src/isa/x86/mod.rs":"65953f998ff3fc3b333167e9979fc0f15f976b51ad75272ac19dcaad0981b371","src/isa/x86/opcodes.rs":"ddebd2f5a14d9d7e37be0a6dc7467d098a2df554ac1deb41c97e5d16273ed353","src/isa/x86/recipes.rs":"a90c48625cc0c60ae67436e333d330967d4ac67498685c62601b47c94c721e8d","src/isa/x86/registers.rs":"4be0a45d8acd465c31746b7976124025b06b453e3f6d587f93efb5af0e12b1a8","src/isa/x86/settings.rs":"49abb46533b3a5415cd033e0a98b5c9561e231f2dd9510d587dc69b204bb6706","src/lib.rs":"2491b0e74078914cb89d1778fa8174daf723fe76aaf7fed18741237d68f6df32","src/shared/entities.rs":"90f774a70e1c2a2e9a553c07a5e80e0fe54cf127434bd83e67274bba4e1a19ba","src/shared/formats.rs":"89ed4074f748637adf56b93ba952e398c45d43e6326d01676885939e3fe8bc4a","src/shared/immediates.rs":"e4a57657f6af9853794804eb41c01204a2c13a632f44f55d90e156a4b98c5f65","src/shared/instructions.rs":"4528650c9b26bd687458d407f46f3c6531cd6f31249024c94e4bf0b4205d7137","src/shared/legalize.rs":"bc9c3292446c1d338df1c4ce19f3ac5482cfe582a04a5a1e82fc9aaa6aef25ea","src/shared/mod.rs":"c219625990bf15507ac1077b349ce20e5312d4e4707426183676d469e78792b7","src/shared/settings.rs":"2e791624b4e85f9e8adcee7169fe445ca8bcdc97d1da92c92ae9576988ab0470","src/shared/types.rs":"4702df132f4b5d70cc9411ec5221ba0b1bd4479252274e0223ae57b6d0331247","src/srcgen.rs":"dcfc159c8599270f17e6a978c4be255abca51556b5ef0da497faec4a4a1e62ce","src/unique_table.rs":"31aa54330ca4786af772d32e8cb6158b6504b88fa93fe177bf0c6cbe545a8d35"},"package":null}
\ No newline at end of file
+{"files":{"Cargo.toml":"f5c824a81cf3c40bded1bfcc325c15e6109724c3efbbc822d4c5782dbefe9f12","LICENSE":"268872b9816f90fd8e85db5a28d33f8150ebb8dd016653fb39ef1f94f2686bc5","README.md":"b123f056d0d458396679c5f7f2a16d2762af0258fcda4ac14b6655a95e5a0022","src/cdsl/ast.rs":"84a4b7e3301e3249716958a7aa4ea5ba8c6172e3c02f57ee3880504c4433ff19","src/cdsl/cpu_modes.rs":"996e45b374cfe85ac47c8c86c4459fe4c04b3158102b4c63b6ee434d5eed6a9e","src/cdsl/encodings.rs":"d884a564815a03c23369bcf31d13b122ae5ba84d0c80eda9312f0c0a829bf794","src/cdsl/formats.rs":"63e638305aa3ca6dd409ddf0e5e9605eeac1cc2631103e42fc6cbc87703d9b63","src/cdsl/instructions.rs":"41e1a230501de3f0da3960d8aa375c8bcd60ec62ede94ad61806816acbd8009a","src/cdsl/isa.rs":"ccabd6848b69eb069c10db61c7e7f86080777495714bb53d03e663c40541be94","src/cdsl/mod.rs":"0aa827923bf4c45e5ee2359573bd863e00f474acd532739f49dcd74a27553882","src/cdsl/operands.rs":"1c3411504de9c83112ff48e0ff1cfbb2e4ba5a9a15c1716f411ef31a4df59899","src/cdsl/recipes.rs":"80b7cd87332229b569e38086ceee8d557e679b9a32ad2e50bdb15c33337c3418","src/cdsl/regs.rs":"466a42a43355fc7623fe5d8e8d330622207a3af6a80cb9367bc0f06e224c9ee0","src/cdsl/settings.rs":"e6fd9a31925743b93b11f09c9c8271bab6aa2430aa053a2601957b4487df7d77","src/cdsl/type_inference.rs":"1efca8a095ffc899b7527bda6b9d9378c73d7283f8dceaa4819e8af599f8be21","src/cdsl/types.rs":"ff764c9e9c29a05677bff6164e7bc25a0c32655052d77ae580536abba8b1713b","src/cdsl/typevar.rs":"c7e80a3c52755f2d91fb5c3d18413b7c97777bd54d1aece8a17d1bbd9944c46a","src/cdsl/xform.rs":"55da0c3f2403147b535ab6ae5d69c623fbe839edecf2a3af1de84420cd58402d","src/default_map.rs":"101bb0282a124f9c921f6bd095f529e8753621450d783c3273b0b0394c2c5c03","src/error.rs":"e9b11b2feb2d867b94c8810fdc5a6c4e0d9131604a0bfa5340ff2639a55100b4","src/gen_binemit.rs":"515e243420b30d1e01f8ea630282d9b6d78a715e1951f3f20392e19a48164442","src/gen_encodings.rs":"f00cded6b68a9b48c9e3cd39a8b6f0ba136f4062c8f8666109158a72c62c3ed1","src/gen_inst.rs":"b275053977c0239211c1df35253154ba4dce2519f506088e71104de37d3db862","src/gen_legalizer.rs":"ea229ab9393cc5ba2242f626e74c624ea59314535e74b26602dafb8e96481a72","src/gen_registers.rs":"a904119ed803c9de24dedd15149a65337ffc168bb1d63df53d7fdebfb5f4b158","src/gen_settings.rs":"f3cc3d31f6cc898f30606caf084f0de220db2d3b1b5e5e4145fa7c9a9a1597e2","src/gen_types.rs":"f6c090e1646a43bf2fe81ae0a7029cc6f7dc6d43285368f56d86c35a21c469a6","src/isa/arm32/mod.rs":"8e09ec1b3caf2d22dce8517b37c356047bfce9a6dea712467d867ed05c4bedaf","src/isa/arm64/mod.rs":"b01f030925d3f2af37d7df1b4a800eb7f0d24f74a46e9154fd8b6752643eb2d5","src/isa/mod.rs":"136141f99f217ba42b9e3f7f47238ab19cc974bb3bef2e2df7f7b5a683989d46","src/isa/riscv/encodings.rs":"8abb1968d917588bc5fc5f5be6dd66bdec23ac456ba65f8138237c8e891e843c","src/isa/riscv/mod.rs":"a7b461a30bbfbc1e3b33645422ff40d5b1761c30cb5d4a8aa12e9a3b7f7aee51","src/isa/riscv/recipes.rs":"fd5a7418fa0d47cdf1b823b31553f1549c03e160ffffac9e22d611185774367e","src/isa/x86/encodings.rs":"3ebb8e638df80db4deb554bf79f4d74f1bb581b55daa631f3cb419f0fa29b7f5","src/isa/x86/instructions.rs":"3c1482583b031d2663b31ee8784f0cb61c8abef995afc7c8f8a6e7be010a2ba8","src/isa/x86/legalize.rs":"5b654c2410ab384cfb20815f1114af76a7967472a45b8d60232ddce9d9921682","src/isa/x86/mod.rs":"65953f998ff3fc3b333167e9979fc0f15f976b51ad75272ac19dcaad0981b371","src/isa/x86/opcodes.rs":"b54d7cd8590ef8cd866b169d50c291fa8b33d4de7c69bcb237e1c879873d08e0","src/isa/x86/recipes.rs":"2621264954661fd474024fc6a8f01aed9cc800aaab8273aede3bd36657851c40","src/isa/x86/registers.rs":"4be0a45d8acd465c31746b7976124025b06b453e3f6d587f93efb5af0e12b1a8","src/isa/x86/settings.rs":"49abb46533b3a5415cd033e0a98b5c9561e231f2dd9510d587dc69b204bb6706","src/lib.rs":"2491b0e74078914cb89d1778fa8174daf723fe76aaf7fed18741237d68f6df32","src/shared/entities.rs":"90f774a70e1c2a2e9a553c07a5e80e0fe54cf127434bd83e67274bba4e1a19ba","src/shared/formats.rs":"89ed4074f748637adf56b93ba952e398c45d43e6326d01676885939e3fe8bc4a","src/shared/immediates.rs":"e4a57657f6af9853794804eb41c01204a2c13a632f44f55d90e156a4b98c5f65","src/shared/instructions.rs":"f2b15219f21087dbe30198d40dc426decbe64decadd7efd9bf9f5e26272c72ef","src/shared/legalize.rs":"bc9c3292446c1d338df1c4ce19f3ac5482cfe582a04a5a1e82fc9aaa6aef25ea","src/shared/mod.rs":"c219625990bf15507ac1077b349ce20e5312d4e4707426183676d469e78792b7","src/shared/settings.rs":"2e791624b4e85f9e8adcee7169fe445ca8bcdc97d1da92c92ae9576988ab0470","src/shared/types.rs":"4702df132f4b5d70cc9411ec5221ba0b1bd4479252274e0223ae57b6d0331247","src/srcgen.rs":"dcfc159c8599270f17e6a978c4be255abca51556b5ef0da497faec4a4a1e62ce","src/unique_table.rs":"31aa54330ca4786af772d32e8cb6158b6504b88fa93fe177bf0c6cbe545a8d35"},"package":null}
\ No newline at end of file
--- a/third_party/rust/cranelift-codegen-meta/Cargo.toml
+++ b/third_party/rust/cranelift-codegen-meta/Cargo.toml
@@ -1,19 +1,19 @@
 [package]
 name = "cranelift-codegen-meta"
 authors = ["The Cranelift Project Developers"]
-version = "0.60.0"
+version = "0.62.0"
 description = "Metaprogram for cranelift-codegen code generator library"
 license = "Apache-2.0 WITH LLVM-exception"
 repository = "https://github.com/bytecodealliance/wasmtime"
 readme = "README.md"
 edition = "2018"
 
 [dependencies]
-cranelift-codegen-shared = { path = "../shared", version = "0.60.0" }
-cranelift-entity = { path = "../../entity", version = "0.60.0" }
+cranelift-codegen-shared = { path = "../shared", version = "0.62.0" }
+cranelift-entity = { path = "../../entity", version = "0.62.0" }
 
 [badges]
 maintenance = { status = "experimental" }
 
 [package.metadata.docs.rs]
 rustdoc-args = [ "--document-private-items" ]
--- a/third_party/rust/cranelift-codegen-meta/src/isa/riscv/recipes.rs
+++ b/third_party/rust/cranelift-codegen-meta/src/isa/riscv/recipes.rs
@@ -200,17 +200,18 @@ pub(crate) fn define(shared_defs: &Share
                     let disp = dest - i64::from(sink.offset());
                     put_uj(bits, disp, 0, sink);
                 "#,
             ),
     );
 
     recipes.push(EncodingRecipeBuilder::new("UJcall", &formats.call, 4).emit(
         r#"
-                    sink.reloc_external(Reloc::RiscvCall,
+                    sink.reloc_external(func.srclocs[inst],
+                                        Reloc::RiscvCall,
                                         &func.dfg.ext_funcs[func_ref].name,
                                         0);
                     // rd=%x1 is the standard link register.
                     put_uj(bits, 0, 1, sink);
                 "#,
     ));
 
     // SB-type branch instructions.
--- a/third_party/rust/cranelift-codegen-meta/src/isa/x86/encodings.rs
+++ b/third_party/rust/cranelift-codegen-meta/src/isa/x86/encodings.rs
@@ -151,17 +151,17 @@ impl PerCpuModeEncodings {
 
         // I32 on x86: no REX prefix.
         self.enc32(inst.bind(I32), template.infer_rex());
 
         // I32 on x86_64: REX.W unset; REX.RXB determined at runtime from registers.
         self.enc64(inst.bind(I32), template.infer_rex());
 
         // I64 on x86_64: REX.W set; REX.RXB determined at runtime from registers.
-        self.enc64(inst.bind(I64), template.infer_rex().w());
+        self.enc64(inst.bind(I64), template.rex().w());
     }
 
     /// Adds I32/I64 encodings as appropriate for a typed instruction.
     /// All variants of REX prefix are explicitly emitted, not inferred.
     ///
     /// Add encodings for `inst.i32` to X86_32.
     /// Add encodings for `inst.i32` to X86_64 with and without REX.
     /// Add encodings for `inst.i64` to X86_64 with and without REX.
@@ -187,17 +187,17 @@ impl PerCpuModeEncodings {
 
         // B32 on x86: no REX prefix.
         self.enc32(inst.bind(B32), template.infer_rex());
 
         // B32 on x86_64: REX.W unset; REX.RXB determined at runtime from registers.
         self.enc64(inst.bind(B32), template.infer_rex());
 
         // B64 on x86_64: REX.W set; REX.RXB determined at runtime from registers.
-        self.enc64(inst.bind(B64), template.infer_rex().w());
+        self.enc64(inst.bind(B64), template.rex().w());
     }
 
     /// Add encodings for `inst.i32` to X86_32.
     /// Add encodings for `inst.i32` to X86_64 with a REX prefix.
     /// Add encodings for `inst.i64` to X86_64 with a REX.W prefix.
     fn enc_i32_i64_rex_only(&mut self, inst: impl Into<InstSpec>, template: Template) {
         let inst: InstSpec = inst.into();
         self.enc32(inst.bind(I32), template.nonrex());
@@ -308,29 +308,29 @@ impl PerCpuModeEncodings {
         template: Template,
         instp: InstructionPredicateNode,
     ) {
         self.enc32_instp(inst.clone(), template.clone(), instp.clone());
         self.enc_x86_64_instp(inst, template, instp);
     }
 
     /// Add two encodings for `inst`:
-    /// - X86_32, dynamically infer the REX prefix.
+    /// - X86_32, no REX prefix, since this is not valid in 32-bit mode.
     /// - X86_64, dynamically infer the REX prefix.
     fn enc_both_inferred(&mut self, inst: impl Clone + Into<InstSpec>, template: Template) {
-        self.enc32(inst.clone(), template.infer_rex());
+        self.enc32(inst.clone(), template.clone());
         self.enc64(inst, template.infer_rex());
     }
     fn enc_both_inferred_maybe_isap(
         &mut self,
         inst: impl Clone + Into<InstSpec>,
         template: Template,
         isap: Option<SettingPredicateNumber>,
     ) {
-        self.enc32_maybe_isap(inst.clone(), template.infer_rex(), isap);
+        self.enc32_maybe_isap(inst.clone(), template.clone(), isap);
         self.enc64_maybe_isap(inst, template.infer_rex(), isap);
     }
 
     /// Add two encodings for `inst`:
     /// - X86_32
     /// - X86_64 with the REX prefix.
     fn enc_both_rex_only(&mut self, inst: impl Clone + Into<InstSpec>, template: Template) {
         self.enc32(inst.clone(), template.clone());
@@ -1595,23 +1595,29 @@ fn define_simd(
     let load = shared.by_name("load");
     let load_complex = shared.by_name("load_complex");
     let raw_bitcast = shared.by_name("raw_bitcast");
     let regfill = shared.by_name("regfill");
     let regmove = shared.by_name("regmove");
     let regspill = shared.by_name("regspill");
     let sadd_sat = shared.by_name("sadd_sat");
     let scalar_to_vector = shared.by_name("scalar_to_vector");
+    let sload8x8 = shared.by_name("sload8x8");
+    let sload16x4 = shared.by_name("sload16x4");
+    let sload32x2 = shared.by_name("sload32x2");
     let spill = shared.by_name("spill");
     let sqrt = shared.by_name("sqrt");
     let sshr_imm = shared.by_name("sshr_imm");
     let ssub_sat = shared.by_name("ssub_sat");
     let store = shared.by_name("store");
     let store_complex = shared.by_name("store_complex");
     let uadd_sat = shared.by_name("uadd_sat");
+    let uload8x8 = shared.by_name("uload8x8");
+    let uload16x4 = shared.by_name("uload16x4");
+    let uload32x2 = shared.by_name("uload32x2");
     let ushr_imm = shared.by_name("ushr_imm");
     let usub_sat = shared.by_name("usub_sat");
     let vconst = shared.by_name("vconst");
     let x86_insertps = x86.by_name("x86_insertps");
     let x86_movlhps = x86.by_name("x86_movlhps");
     let x86_movsd = x86.by_name("x86_movsd");
     let x86_pextr = x86.by_name("x86_pextr");
     let x86_pinsr = x86.by_name("x86_pinsr");
@@ -1855,18 +1861,18 @@ fn define_simd(
     // MOVUPS and MOVAPS from SSE (TODO ideally all of these would either use MOVAPS when we have
     // alignment or type-specific encodings, see https://github.com/bytecodealliance/wasmtime/issues/1124).
     // Also, it would be ideal to infer REX prefixes for all of these instructions but for the
     // time being only instructions with common recipes have `infer_rex()` support.
     for ty in ValueType::all_lane_types().filter(allowed_simd_type) {
         // Store
         let bound_store = store.bind(vector(ty, sse_vector_size)).bind(Any);
         e.enc_both_inferred(bound_store.clone(), rec_fst.opcodes(&MOVUPS_STORE));
-        e.enc_both(bound_store.clone(), rec_fstDisp8.opcodes(&MOVUPS_STORE));
-        e.enc_both(bound_store, rec_fstDisp32.opcodes(&MOVUPS_STORE));
+        e.enc_both_inferred(bound_store.clone(), rec_fstDisp8.opcodes(&MOVUPS_STORE));
+        e.enc_both_inferred(bound_store, rec_fstDisp32.opcodes(&MOVUPS_STORE));
 
         // Store complex
         let bound_store_complex = store_complex.bind(vector(ty, sse_vector_size));
         e.enc_both(
             bound_store_complex.clone(),
             rec_fstWithIndex.opcodes(&MOVUPS_STORE),
         );
         e.enc_both(
@@ -1876,18 +1882,18 @@ fn define_simd(
         e.enc_both(
             bound_store_complex,
             rec_fstWithIndexDisp32.opcodes(&MOVUPS_STORE),
         );
 
         // Load
         let bound_load = load.bind(vector(ty, sse_vector_size)).bind(Any);
         e.enc_both_inferred(bound_load.clone(), rec_fld.opcodes(&MOVUPS_LOAD));
-        e.enc_both(bound_load.clone(), rec_fldDisp8.opcodes(&MOVUPS_LOAD));
-        e.enc_both(bound_load, rec_fldDisp32.opcodes(&MOVUPS_LOAD));
+        e.enc_both_inferred(bound_load.clone(), rec_fldDisp8.opcodes(&MOVUPS_LOAD));
+        e.enc_both_inferred(bound_load, rec_fldDisp32.opcodes(&MOVUPS_LOAD));
 
         // Load complex
         let bound_load_complex = load_complex.bind(vector(ty, sse_vector_size));
         e.enc_both(
             bound_load_complex.clone(),
             rec_fldWithIndex.opcodes(&MOVUPS_LOAD),
         );
         e.enc_both(
@@ -1921,16 +1927,34 @@ fn define_simd(
         let bound_copy = copy.bind(vector(ty, sse_vector_size));
         e.enc_both(bound_copy, rec_furm.opcodes(&MOVAPS_LOAD));
         let bound_copy_to_ssa = copy_to_ssa.bind(vector(ty, sse_vector_size));
         e.enc_both(bound_copy_to_ssa, rec_furm_reg_to_ssa.opcodes(&MOVAPS_LOAD));
         let bound_copy_nop = copy_nop.bind(vector(ty, sse_vector_size));
         e.enc_32_64_rec(bound_copy_nop, rec_stacknull, 0);
     }
 
+    // SIMD load extend
+    for (inst, opcodes) in &[
+        (uload8x8, &PMOVZXBW),
+        (uload16x4, &PMOVZXWD),
+        (uload32x2, &PMOVZXDQ),
+        (sload8x8, &PMOVSXBW),
+        (sload16x4, &PMOVSXWD),
+        (sload32x2, &PMOVSXDQ),
+    ] {
+        let isap = Some(use_sse41_simd);
+        for recipe in &[rec_fld, rec_fldDisp8, rec_fldDisp32] {
+            let inst = *inst;
+            let template = recipe.opcodes(*opcodes);
+            e.enc_both_inferred_maybe_isap(inst.clone().bind(I32), template.clone(), isap);
+            e.enc64_maybe_isap(inst.bind(I64), template.infer_rex(), isap);
+        }
+    }
+
     // SIMD integer addition
     for (ty, opcodes) in &[(I8, &PADDB), (I16, &PADDW), (I32, &PADDD), (I64, &PADDQ)] {
         let iadd = iadd.bind(vector(*ty, sse_vector_size));
         e.enc_both_inferred(iadd, rec_fa.opcodes(*opcodes));
     }
 
     // SIMD integer saturating addition
     e.enc_both_inferred(
--- a/third_party/rust/cranelift-codegen-meta/src/isa/x86/opcodes.rs
+++ b/third_party/rust/cranelift-codegen-meta/src/isa/x86/opcodes.rs
@@ -412,16 +412,40 @@ pub static PMINUB: [u8; 3] = [0x66, 0x0f
 /// Compare packed unsigned doubleword integers in xmm1 and xmm2/m128 and store packed minimum
 /// values in xmm1 (SSE4.1).
 pub static PMINUD: [u8; 4] = [0x66, 0x0f, 0x38, 0x3b];
 
 /// Compare packed unsigned word integers in xmm1 and xmm2/m128 and store packed minimum values in
 /// xmm1 (SSE4.1).
 pub static PMINUW: [u8; 4] = [0x66, 0x0f, 0x38, 0x3a];
 
+/// Sign extend 8 packed 8-bit integers in the low 8 bytes of xmm2/m64 to 8 packed 16-bit
+/// integers in xmm1 (SSE4.1).
+pub static PMOVSXBW: [u8; 4] = [0x66, 0x0f, 0x38, 0x20];
+
+/// Sign extend 4 packed 16-bit integers in the low 8 bytes of xmm2/m64 to 4 packed 32-bit
+/// integers in xmm1 (SSE4.1).
+pub static PMOVSXWD: [u8; 4] = [0x66, 0x0f, 0x38, 0x23];
+
+/// Sign extend 2 packed 32-bit integers in the low 8 bytes of xmm2/m64 to 2 packed 64-bit
+/// integers in xmm1.
+pub static PMOVSXDQ: [u8; 4] = [0x66, 0x0f, 0x38, 0x25];
+
+/// Zero extend 8 packed 8-bit integers in the low 8 bytes of xmm2/m64 to 8 packed 16-bit
+/// integers in xmm1 (SSE4.1).
+pub static PMOVZXBW: [u8; 4] = [0x66, 0x0f, 0x38, 0x30];
+
+/// Zero extend 4 packed 16-bit integers in the low 8 bytes of xmm2/m64 to 4 packed 32-bit
+/// integers in xmm1 (SSE4.1).
+pub static PMOVZXWD: [u8; 4] = [0x66, 0x0f, 0x38, 0x33];
+
+/// Zero extend 2 packed 32-bit integers in the low 8 bytes of xmm2/m64 to 2 packed 64-bit
+/// integers in xmm1.
+pub static PMOVZXDQ: [u8; 4] = [0x66, 0x0f, 0x38, 0x35];
+
 /// Multiply the packed signed word integers in xmm1 and xmm2/m128, and store the low 16 bits of
 /// the results in xmm1 (SSE2).
 pub static PMULLW: [u8; 3] = [0x66, 0x0f, 0xd5];
 
 /// Multiply the packed doubleword signed integers in xmm1 and xmm2/m128 and store the low 32
 /// bits of each product in xmm1 (SSE4.1).
 pub static PMULLD: [u8; 4] = [0x66, 0x0f, 0x38, 0x40];
 
--- a/third_party/rust/cranelift-codegen-meta/src/isa/x86/recipes.rs
+++ b/third_party/rust/cranelift-codegen-meta/src/isa/x86/recipes.rs
@@ -330,16 +330,17 @@ impl<'builder> Template<'builder> {
                     Some(replace_nonrex_constraints(self.regs, operands_out));
 
                 (opcode.into(), self.op_bytes.len() as u64)
             }
             RecipePrefixKind::AlwaysEmitRex => {
                 ("Rex".to_string() + opcode, self.op_bytes.len() as u64 + 1)
             }
             RecipePrefixKind::InferRex => {
+                assert_eq!(self.w_bit, 0, "A REX.W bit always requires a REX prefix; avoid using `infer_rex().w()` and use `rex().w()` instead.");
                 // Hook up the right function for inferred compute_size().
                 assert!(
                     self.inferred_rex_compute_size.is_some(),
                     "InferRex recipe '{}' needs an inferred_rex_compute_size function.",
                     &self.recipe.name
                 );
                 self.recipe.compute_size = self.inferred_rex_compute_size;
 
@@ -1003,17 +1004,17 @@ pub(crate) fn define<'shared>(
             EncodingRecipeBuilder::new("r_ib_unsigned_gpr", &formats.extract_lane, 2)
                 .operands_in(vec![fpr])
                 .operands_out(vec![gpr])
                 .inst_predicate(InstructionPredicate::new_is_unsigned_int(
                     &*formats.extract_lane, "lane", 8, 0,
                 ))
                 .emit(
                     r#"
-                    {{PUT_OP}}(bits, rex2(in_reg0, out_reg0), sink);
+                    {{PUT_OP}}(bits, rex2(out_reg0, in_reg0), sink);
                     modrm_rr(out_reg0, in_reg0, sink); // note the flipped register in the ModR/M byte
                     let imm:i64 = lane.into();
                     sink.put1(imm as u8);
                 "#,
                 ), "size_with_inferred_rex_for_inreg0_outreg0"
         );
     }
 
@@ -1252,63 +1253,67 @@ pub(crate) fn define<'shared>(
 
     // XX+rd id with Abs4 function relocation.
     recipes.add_template_recipe(
         EncodingRecipeBuilder::new("fnaddr4", &formats.func_addr, 4)
             .operands_out(vec![gpr])
             .emit(
                 r#"
                     {{PUT_OP}}(bits | (out_reg0 & 7), rex1(out_reg0), sink);
-                    sink.reloc_external(Reloc::Abs4,
+                    sink.reloc_external(func.srclocs[inst],
+                                        Reloc::Abs4,
                                         &func.dfg.ext_funcs[func_ref].name,
                                         0);
                     sink.put4(0);
                 "#,
             ),
     );
 
     // XX+rd iq with Abs8 function relocation.
     recipes.add_template_recipe(
         EncodingRecipeBuilder::new("fnaddr8", &formats.func_addr, 8)
             .operands_out(vec![gpr])
             .emit(
                 r#"
                     {{PUT_OP}}(bits | (out_reg0 & 7), rex1(out_reg0), sink);
-                    sink.reloc_external(Reloc::Abs8,
+                    sink.reloc_external(func.srclocs[inst],
+                                        Reloc::Abs8,
                                         &func.dfg.ext_funcs[func_ref].name,
                                         0);
                     sink.put8(0);
                 "#,
             ),
     );
 
     // Similar to fnaddr4, but writes !0 (this is used by BaldrMonkey).
     recipes.add_template_recipe(
         EncodingRecipeBuilder::new("allones_fnaddr4", &formats.func_addr, 4)
             .operands_out(vec![gpr])
             .emit(
                 r#"
                     {{PUT_OP}}(bits | (out_reg0 & 7), rex1(out_reg0), sink);
-                    sink.reloc_external(Reloc::Abs4,
+                    sink.reloc_external(func.srclocs[inst],
+                                        Reloc::Abs4,
                                         &func.dfg.ext_funcs[func_ref].name,
                                         0);
                     // Write the immediate as `!0` for the benefit of BaldrMonkey.
                     sink.put4(!0);
                 "#,
             ),
     );
 
     // Similar to fnaddr8, but writes !0 (this is used by BaldrMonkey).
     recipes.add_template_recipe(
         EncodingRecipeBuilder::new("allones_fnaddr8", &formats.func_addr, 8)
             .operands_out(vec![gpr])
             .emit(
                 r#"
                     {{PUT_OP}}(bits | (out_reg0 & 7), rex1(out_reg0), sink);
-                    sink.reloc_external(Reloc::Abs8,
+                    sink.reloc_external(func.srclocs[inst],
+                                        Reloc::Abs8,
                                         &func.dfg.ext_funcs[func_ref].name,
                                         0);
                     // Write the immediate as `!0` for the benefit of BaldrMonkey.
                     sink.put8(!0);
                 "#,
             ),
     );
 
@@ -1318,17 +1323,18 @@ pub(crate) fn define<'shared>(
             // rex2 gets passed 0 for r/m register because the upper bit of
             // r/m doesn't get decoded when in rip-relative addressing mode.
             .emit(
                 r#"
                     {{PUT_OP}}(bits, rex2(0, out_reg0), sink);
                     modrm_riprel(out_reg0, sink);
                     // The addend adjusts for the difference between the end of the
                     // instruction and the beginning of the immediate field.
-                    sink.reloc_external(Reloc::X86PCRel4,
+                    sink.reloc_external(func.srclocs[inst],
+                                        Reloc::X86PCRel4,
                                         &func.dfg.ext_funcs[func_ref].name,
                                         -4);
                     sink.put4(0);
                 "#,
             ),
     );
 
     recipes.add_template_recipe(
@@ -1337,47 +1343,50 @@ pub(crate) fn define<'shared>(
             // rex2 gets passed 0 for r/m register because the upper bit of
             // r/m doesn't get decoded when in rip-relative addressing mode.
             .emit(
                 r#"
                     {{PUT_OP}}(bits, rex2(0, out_reg0), sink);
                     modrm_riprel(out_reg0, sink);
                     // The addend adjusts for the difference between the end of the
                     // instruction and the beginning of the immediate field.
-                    sink.reloc_external(Reloc::X86GOTPCRel4,
+                    sink.reloc_external(func.srclocs[inst],
+                                        Reloc::X86GOTPCRel4,
                                         &func.dfg.ext_funcs[func_ref].name,
                                         -4);
                     sink.put4(0);
                 "#,
             ),
     );
 
     // XX+rd id with Abs4 globalsym relocation.
     recipes.add_template_recipe(
         EncodingRecipeBuilder::new("gvaddr4", &formats.unary_global_value, 4)
             .operands_out(vec![gpr])
             .emit(
                 r#"
                     {{PUT_OP}}(bits | (out_reg0 & 7), rex1(out_reg0), sink);
-                    sink.reloc_external(Reloc::Abs4,
+                    sink.reloc_external(func.srclocs[inst],
+                                        Reloc::Abs4,
                                         &func.global_values[global_value].symbol_name(),
                                         0);
                     sink.put4(0);
                 "#,
             ),
     );
 
     // XX+rd iq with Abs8 globalsym relocation.
     recipes.add_template_recipe(
         EncodingRecipeBuilder::new("gvaddr8", &formats.unary_global_value, 8)
             .operands_out(vec![gpr])
             .emit(
                 r#"
                     {{PUT_OP}}(bits | (out_reg0 & 7), rex1(out_reg0), sink);
-                    sink.reloc_external(Reloc::Abs8,
+                    sink.reloc_external(func.srclocs[inst],
+                                        Reloc::Abs8,
                                         &func.global_values[global_value].symbol_name(),
                                         0);
                     sink.put8(0);
                 "#,
             ),
     );
 
     // XX+rd iq with PCRel4 globalsym relocation.
@@ -1385,17 +1394,18 @@ pub(crate) fn define<'shared>(
         EncodingRecipeBuilder::new("pcrel_gvaddr8", &formats.unary_global_value, 5)
             .operands_out(vec![gpr])
             .emit(
                 r#"
                     {{PUT_OP}}(bits, rex2(0, out_reg0), sink);
                     modrm_rm(5, out_reg0, sink);
                     // The addend adjusts for the difference between the end of the
                     // instruction and the beginning of the immediate field.
-                    sink.reloc_external(Reloc::X86PCRel4,
+                    sink.reloc_external(func.srclocs[inst],
+                                        Reloc::X86PCRel4,
                                         &func.global_values[global_value].symbol_name(),
                                         -4);
                     sink.put4(0);
                 "#,
             ),
     );
 
     // XX+rd iq with Abs8 globalsym relocation.
@@ -1403,17 +1413,18 @@ pub(crate) fn define<'shared>(
         EncodingRecipeBuilder::new("got_gvaddr8", &formats.unary_global_value, 5)
             .operands_out(vec![gpr])
             .emit(
                 r#"
                     {{PUT_OP}}(bits, rex2(0, out_reg0), sink);
                     modrm_rm(5, out_reg0, sink);
                     // The addend adjusts for the difference between the end of the
                     // instruction and the beginning of the immediate field.
-                    sink.reloc_external(Reloc::X86GOTPCRel4,
+                    sink.reloc_external(func.srclocs[inst],
+                                        Reloc::X86GOTPCRel4,
                                         &func.global_values[global_value].symbol_name(),
                                         -4);
                     sink.put4(0);
                 "#,
             ),
     );
 
     // Stack addresses.
@@ -1599,17 +1610,17 @@ pub(crate) fn define<'shared>(
                     "#,
                     ),
                 regs,
             )
             .when_prefixed(st_disp8),
         );
 
         // XX /r register-indirect store with 8-bit offset of FPR.
-        recipes.add_template_recipe(
+        recipes.add_template_inferred(
             EncodingRecipeBuilder::new("fstDisp8", &formats.store, 2)
                 .operands_in(vec![fpr, gpr])
                 .inst_predicate(has_small_offset)
                 .clobbers_flags(false)
                 .compute_size("size_plus_maybe_sib_for_inreg_1")
                 .emit(
                     r#"
                         if !flags.notrap() {
@@ -1621,16 +1632,17 @@ pub(crate) fn define<'shared>(
                             sib_noindex(in_reg1, sink);
                         } else {
                             modrm_disp8(in_reg1, in_reg0, sink);
                         }
                         let offset: i32 = offset.into();
                         sink.put1(offset as u8);
                     "#,
                 ),
+            "size_plus_maybe_sib_inreg1_plus_rex_prefix_for_inreg0_inreg1",
         );
 
         // XX /r register-indirect store with 32-bit offset.
         let st_disp32 = recipes.add_template_recipe(
             EncodingRecipeBuilder::new("stDisp32", &formats.store, 5)
                 .operands_in(vec![gpr, gpr])
                 .clobbers_flags(false)
                 .compute_size("size_plus_maybe_sib_for_inreg_1")
@@ -1677,17 +1689,17 @@ pub(crate) fn define<'shared>(
                     "#,
                     ),
                 regs,
             )
             .when_prefixed(st_disp32),
         );
 
         // XX /r register-indirect store with 32-bit offset of FPR.
-        recipes.add_template_recipe(
+        recipes.add_template_inferred(
             EncodingRecipeBuilder::new("fstDisp32", &formats.store, 5)
                 .operands_in(vec![fpr, gpr])
                 .clobbers_flags(false)
                 .compute_size("size_plus_maybe_sib_for_inreg_1")
                 .emit(
                     r#"
                         if !flags.notrap() {
                             sink.trap(TrapCode::HeapOutOfBounds, func.srclocs[inst]);
@@ -1698,16 +1710,17 @@ pub(crate) fn define<'shared>(
                             sib_noindex(in_reg1, sink);
                         } else {
                             modrm_disp32(in_reg1, in_reg0, sink);
                         }
                         let offset: i32 = offset.into();
                         sink.put4(offset as u32);
                     "#,
                 ),
+            "size_plus_maybe_sib_inreg1_plus_rex_prefix_for_inreg0_inreg1",
         );
     }
 
     {
         // Complex stores.
 
         // A predicate asking if the offset is zero.
         let has_no_offset =
@@ -2082,17 +2095,17 @@ pub(crate) fn define<'shared>(
                         }
                         let offset: i32 = offset.into();
                         sink.put1(offset as u8);
                     "#,
                 ),
         );
 
         // XX /r float load with 8-bit offset.
-        recipes.add_template_recipe(
+        recipes.add_template_inferred(
             EncodingRecipeBuilder::new("fldDisp8", &formats.load, 2)
                 .operands_in(vec![gpr])
                 .operands_out(vec![fpr])
                 .inst_predicate(has_small_offset)
                 .clobbers_flags(false)
                 .compute_size("size_plus_maybe_sib_for_inreg_0")
                 .emit(
                     r#"
@@ -2105,16 +2118,17 @@ pub(crate) fn define<'shared>(
                             sib_noindex(in_reg0, sink);
                         } else {
                             modrm_disp8(in_reg0, out_reg0, sink);
                         }
                         let offset: i32 = offset.into();
                         sink.put1(offset as u8);
                     "#,
                 ),
+            "size_plus_maybe_sib_for_inreg_0_plus_rex_prefix_for_inreg0_outreg0",
         );
 
         let has_big_offset =
             InstructionPredicate::new_is_signed_int(&*formats.load, "offset", 32, 0);
 
         // XX /r load with 32-bit offset.
         recipes.add_template_recipe(
             EncodingRecipeBuilder::new("ldDisp32", &formats.load, 5)
@@ -2137,17 +2151,17 @@ pub(crate) fn define<'shared>(
                         }
                         let offset: i32 = offset.into();
                         sink.put4(offset as u32);
                     "#,
                 ),
         );
 
         // XX /r float load with 32-bit offset.
-        recipes.add_template_recipe(
+        recipes.add_template_inferred(
             EncodingRecipeBuilder::new("fldDisp32", &formats.load, 5)
                 .operands_in(vec![gpr])
                 .operands_out(vec![fpr])
                 .inst_predicate(has_big_offset)
                 .clobbers_flags(false)
                 .compute_size("size_plus_maybe_sib_for_inreg_0")
                 .emit(
                     r#"
@@ -2160,16 +2174,17 @@ pub(crate) fn define<'shared>(
                             sib_noindex(in_reg0, sink);
                         } else {
                             modrm_disp32(in_reg0, out_reg0, sink);
                         }
                         let offset: i32 = offset.into();
                         sink.put4(offset as u32);
                     "#,
                 ),
+            "size_plus_maybe_sib_for_inreg_0_plus_rex_prefix_for_inreg0_outreg0",
         );
     }
 
     {
         // Complex loads.
 
         // A predicate asking if the offset is zero.
         let has_no_offset =
@@ -2392,45 +2407,50 @@ pub(crate) fn define<'shared>(
 
     recipes.add_template_recipe(
         EncodingRecipeBuilder::new("call_id", &formats.call, 4).emit(
             r#"
             sink.trap(TrapCode::StackOverflow, func.srclocs[inst]);
             {{PUT_OP}}(bits, BASE_REX, sink);
             // The addend adjusts for the difference between the end of the
             // instruction and the beginning of the immediate field.
-            sink.reloc_external(Reloc::X86CallPCRel4,
+            sink.reloc_external(func.srclocs[inst],
+                                Reloc::X86CallPCRel4,
                                 &func.dfg.ext_funcs[func_ref].name,
                                 -4);
             sink.put4(0);
+            sink.add_call_site(opcode, func.srclocs[inst]);
         "#,
         ),
     );
 
     recipes.add_template_recipe(
         EncodingRecipeBuilder::new("call_plt_id", &formats.call, 4).emit(
             r#"
             sink.trap(TrapCode::StackOverflow, func.srclocs[inst]);
             {{PUT_OP}}(bits, BASE_REX, sink);
-            sink.reloc_external(Reloc::X86CallPLTRel4,
+            sink.reloc_external(func.srclocs[inst],
+                                Reloc::X86CallPLTRel4,
                                 &func.dfg.ext_funcs[func_ref].name,
                                 -4);
             sink.put4(0);
+            sink.add_call_site(opcode, func.srclocs[inst]);
         "#,
         ),
     );
 
     recipes.add_template_recipe(
         EncodingRecipeBuilder::new("call_r", &formats.call_indirect, 1)
             .operands_in(vec![gpr])
             .emit(
                 r#"
                     sink.trap(TrapCode::StackOverflow, func.srclocs[inst]);
                     {{PUT_OP}}(bits, rex1(in_reg0), sink);
                     modrm_r_bits(in_reg0, bits, sink);
+                    sink.add_call_site(opcode, func.srclocs[inst]);
                 "#,
             ),
     );
 
     recipes.add_template_recipe(
         EncodingRecipeBuilder::new("ret", &formats.multiary, 0)
             .emit("{{PUT_OP}}(bits, BASE_REX, sink);"),
     );
@@ -3310,27 +3330,29 @@ pub(crate) fn define<'shared>(
                     // Those data16 prefixes are necessary to pad to 16 bytes.
 
                     // data16 lea gv@tlsgd(%rip),%rdi
                     sink.put1(0x66); // data16
                     sink.put1(0b01001000); // rex.w
                     const LEA: u8 = 0x8d;
                     sink.put1(LEA); // lea
                     modrm_riprel(0b111/*out_reg0*/, sink); // 0x3d
-                    sink.reloc_external(Reloc::ElfX86_64TlsGd,
+                    sink.reloc_external(func.srclocs[inst],
+                                        Reloc::ElfX86_64TlsGd,
                                         &func.global_values[global_value].symbol_name(),
                                         -4);
                     sink.put4(0);
 
                     // data16 data16 callq __tls_get_addr-4
                     sink.put1(0x66); // data16
                     sink.put1(0x66); // data16
                     sink.put1(0b01001000); // rex.w
                     sink.put1(0xe8); // call
-                    sink.reloc_external(Reloc::X86CallPLTRel4,
+                    sink.reloc_external(func.srclocs[inst],
+                                        Reloc::X86CallPLTRel4,
                                         &ExternalName::LibCall(LibCall::ElfTlsGetAddr),
                                         -4);
                     sink.put4(0);
                 "#,
             ),
     );
 
     recipes.add_recipe(
@@ -3341,17 +3363,18 @@ pub(crate) fn define<'shared>(
                 r#"
                     // output %rax
                     // clobbers %rdi
 
                     // movq gv@tlv(%rip), %rdi
                     sink.put1(0x48); // rex
                     sink.put1(0x8b); // mov
                     modrm_riprel(0b111/*out_reg0*/, sink); // 0x3d
-                    sink.reloc_external(Reloc::MachOX86_64Tlv,
+                    sink.reloc_external(func.srclocs[inst],
+                                        Reloc::MachOX86_64Tlv,
                                         &func.global_values[global_value].symbol_name(),
                                         -4);
                     sink.put4(0);
 
                     // callq *(%rdi)
                     sink.put1(0xff);
                     sink.put1(0x17);
                 "#,
--- a/third_party/rust/cranelift-codegen-meta/src/shared/instructions.rs
+++ b/third_party/rust/cranelift-codegen-meta/src/shared/instructions.rs
@@ -1142,16 +1142,133 @@ pub(crate) fn define(
         This is equivalent to ``ireduce.i32`` followed by ``store.i32``.
         "#,
             &formats.store_complex,
         )
         .operands_in(vec![MemFlags, x, args, Offset])
         .can_store(true),
     );
 
+    let I16x8 = &TypeVar::new(
+        "I16x8",
+        "A SIMD vector with exactly 8 lanes of 16-bit values",
+        TypeSetBuilder::new()
+            .ints(16..16)
+            .simd_lanes(8..8)
+            .includes_scalars(false)
+            .build(),
+    );
+    let a = &Operand::new("a", I16x8).with_doc("Value loaded");
+
+    ig.push(
+        Inst::new(
+            "uload8x8",
+            r#"
+        Load an 8x8 vector (64 bits) from memory at ``p + Offset`` and zero-extend into an i16x8 
+        vector.
+        "#,
+            &formats.load,
+        )
+        .operands_in(vec![MemFlags, p, Offset])
+        .operands_out(vec![a])
+        .can_load(true),
+    );
+
+    ig.push(
+        Inst::new(
+            "sload8x8",
+            r#"
+        Load an 8x8 vector (64 bits) from memory at ``p + Offset`` and sign-extend into an i16x8 
+        vector.
+        "#,
+            &formats.load,
+        )
+        .operands_in(vec![MemFlags, p, Offset])
+        .operands_out(vec![a])
+        .can_load(true),
+    );
+
+    let I32x4 = &TypeVar::new(
+        "I32x4",
+        "A SIMD vector with exactly 4 lanes of 32-bit values",
+        TypeSetBuilder::new()
+            .ints(32..32)
+            .simd_lanes(4..4)
+            .includes_scalars(false)
+            .build(),
+    );
+    let a = &Operand::new("a", I32x4).with_doc("Value loaded");
+
+    ig.push(
+        Inst::new(
+            "uload16x4",
+            r#"
+        Load an 16x4 vector (64 bits) from memory at ``p + Offset`` and zero-extend into an i32x4 
+        vector.
+        "#,
+            &formats.load,
+        )
+        .operands_in(vec![MemFlags, p, Offset])
+        .operands_out(vec![a])
+        .can_load(true),
+    );
+
+    ig.push(
+        Inst::new(
+            "sload16x4",
+            r#"
+        Load a 16x4 vector (64 bits) from memory at ``p + Offset`` and sign-extend into an i32x4 
+        vector.
+        "#,
+            &formats.load,
+        )
+        .operands_in(vec![MemFlags, p, Offset])
+        .operands_out(vec![a])
+        .can_load(true),
+    );
+
+    let I64x2 = &TypeVar::new(
+        "I64x2",
+        "A SIMD vector with exactly 2 lanes of 64-bit values",
+        TypeSetBuilder::new()
+            .ints(64..64)
+            .simd_lanes(2..2)
+            .includes_scalars(false)
+            .build(),
+    );
+    let a = &Operand::new("a", I64x2).with_doc("Value loaded");
+
+    ig.push(
+        Inst::new(
+            "uload32x2",
+            r#"
+        Load an 32x2 vector (64 bits) from memory at ``p + Offset`` and zero-extend into an i64x2 
+        vector.
+        "#,
+            &formats.load,
+        )
+        .operands_in(vec![MemFlags, p, Offset])
+        .operands_out(vec![a])
+        .can_load(true),
+    );
+
+    ig.push(
+        Inst::new(
+            "sload32x2",
+            r#"
+        Load a 32x2 vector (64 bits) from memory at ``p + Offset`` and sign-extend into an i64x2 
+        vector.
+        "#,
+            &formats.load,
+        )
+        .operands_in(vec![MemFlags, p, Offset])
+        .operands_out(vec![a])
+        .can_load(true),
+    );
+
     let x = &Operand::new("x", Mem).with_doc("Value to be stored");
     let a = &Operand::new("a", Mem).with_doc("Value loaded");
     let Offset =
         &Operand::new("Offset", &imm.offset32).with_doc("In-bounds offset into stack slot");
 
     ig.push(
         Inst::new(
             "stack_load",
--- a/third_party/rust/cranelift-codegen-shared/.cargo-checksum.json
+++ b/third_party/rust/cranelift-codegen-shared/.cargo-checksum.json
@@ -1,1 +1,1 @@
-{"files":{"Cargo.toml":"9b4276e6dafee6a97061c404a8418bf6bd683dd6cf4ae1997eafa990d2f20d6b","LICENSE":"268872b9816f90fd8e85db5a28d33f8150ebb8dd016653fb39ef1f94f2686bc5","README.md":"a410bc2f5dcbde499c0cd299c2620bc8111e3c5b3fccdd9e2d85caf3c24fdab3","src/condcodes.rs":"b8d433b2217b86e172d25b6c65a3ce0cc8ca221062cad1b28b0c78d2159fbda9","src/constant_hash.rs":"ffc619f45aad62c6fdcb83553a05879691a72e9a0103375b2d6cc12d52cf72d0","src/constants.rs":"fed03a10a6316e06aa174091db6e7d1fbb5f73c82c31193012ec5ab52f1c603a","src/isa/mod.rs":"428a950eca14acbe783899ccb1aecf15027f8cbe205578308ebde203d10535f3","src/isa/x86/encoding_bits.rs":"7e013fb804b13f9f83a0d517c6f5105856938d08ad378cc44a6fe6a59adef270","src/isa/x86/mod.rs":"01ef4e4d7437f938badbe2137892183c1ac684da0f68a5bec7e06aad34f43b9b","src/lib.rs":"91f26f998f11fb9cb74d2ec171424e29badd417beef023674850ace57149c656"},"package":null}
\ No newline at end of file
+{"files":{"Cargo.toml":"35beecf644d966a002873be06c3f087756b39bb9d206aa465d957df96b6d4304","LICENSE":"268872b9816f90fd8e85db5a28d33f8150ebb8dd016653fb39ef1f94f2686bc5","README.md":"a410bc2f5dcbde499c0cd299c2620bc8111e3c5b3fccdd9e2d85caf3c24fdab3","src/condcodes.rs":"b8d433b2217b86e172d25b6c65a3ce0cc8ca221062cad1b28b0c78d2159fbda9","src/constant_hash.rs":"ffc619f45aad62c6fdcb83553a05879691a72e9a0103375b2d6cc12d52cf72d0","src/constants.rs":"fed03a10a6316e06aa174091db6e7d1fbb5f73c82c31193012ec5ab52f1c603a","src/isa/mod.rs":"428a950eca14acbe783899ccb1aecf15027f8cbe205578308ebde203d10535f3","src/isa/x86/encoding_bits.rs":"7e013fb804b13f9f83a0d517c6f5105856938d08ad378cc44a6fe6a59adef270","src/isa/x86/mod.rs":"01ef4e4d7437f938badbe2137892183c1ac684da0f68a5bec7e06aad34f43b9b","src/lib.rs":"91f26f998f11fb9cb74d2ec171424e29badd417beef023674850ace57149c656"},"package":null}
\ No newline at end of file
--- a/third_party/rust/cranelift-codegen-shared/Cargo.toml
+++ b/third_party/rust/cranelift-codegen-shared/Cargo.toml
@@ -1,11 +1,11 @@
 [package]
 authors = ["The Cranelift Project Developers"]
 name = "cranelift-codegen-shared"
-version = "0.60.0"
+version = "0.62.0"
 description = "For code shared between cranelift-codegen-meta and cranelift-codegen"
 license = "Apache-2.0 WITH LLVM-exception"
 repository = "https://github.com/bytecodealliance/wasmtime"
 readme = "README.md"
 edition = "2018"
 
 # Since this is a shared dependency of several packages, please strive to keep this dependency-free.
--- a/third_party/rust/cranelift-codegen/.cargo-checksum.json
+++ b/third_party/rust/cranelift-codegen/.cargo-checksum.json
@@ -1,1 +1,1 @@
-{"files":{"Cargo.toml":"2f70cb2138f4a85e2079ea7b7cbffe80ec53ef69d78b5f38f669c352cd45670d","LICENSE":"268872b9816f90fd8e85db5a28d33f8150ebb8dd016653fb39ef1f94f2686bc5","README.md":"e5127227a7db4a8aa92fa6613ed71801025790e696bb41b0323fb7f3c6f7495a","build.rs":"9fffedcfb42f2147f1a3f2b8d39af91e291768fe6f4e75ce19de1debfca7bfd8","src/abi.rs":"8e0d0c149007ec1bbc7128b806d184047a2b2aa8fc81ae73ac9d653e2650ff81","src/binemit/memorysink.rs":"8290a7f5bb1b8868b555d07353e767e8b49ef4ff7350f0a4f1a9729c951919bc","src/binemit/mod.rs":"b4bb649468c8781611ead0309474d0c19f155ddacb4084a7f7d101f1318f617d","src/binemit/relaxation.rs":"e40b254bc30d4aaf7d6390d15071ea31352fc82cd57eb67a6602d53ba4612b67","src/binemit/shrink.rs":"552d64dff3b044bca77f39891d0e39ee619f6ec0669bf9917132c97becea79b0","src/binemit/stackmap.rs":"3f141f4652ec5148fbcf2db88d0ac7881823158b528c989770eacd4165afa39b","src/bitset.rs":"c4fa43fff52a8f2d343e3edbeeb26d851c64ed811e3d3aa9e2af80358d43be14","src/cfg_printer.rs":"a4cd85ecb2c403b29dc3fc6c60ee7f97b6ed602e8ba88ec87accb988d009271e","src/constant_hash.rs":"8f53afb38891fbdab8553c7a89e61f0ce30947a22fb24ae84523c9a1ab025c3f","src/context.rs":"d47182f15327dbd775d9bbeae87439a108f8e12ac20515ee59934d059aaf5fb2","src/cursor.rs":"97d8beadadd45c27f26e7a569a6e5b1068d7d2e391633b891985379c71165259","src/dbg.rs":"1898d94cff0975815eb348651702e95c8f2f63886501d3b7043ee75668480472","src/dce.rs":"3af68cbbc6acfa4e4f2105d9343ae62d58f61dd5746e5d24fb49f38a02636081","src/divconst_magic_numbers.rs":"e7f8f46f3a25ed7155890e9d76c10f5dde9dc5bbcebb623c8166fa415abdd959","src/dominator_tree.rs":"b3a5c7837150390a78ade90807965dfcb8768a7e3ae9ee02f2e4a1ad8f3bafa9","src/flowgraph.rs":"71490e2f7a1ea905758a258b2bebe77f125302f446f9839dd60003fdafaef5fe","src/fx.rs":"8a5d07487906d8316a179e826fcd817a92a4860686256a6fd9d78ba47c63f330","src/ir/builder.rs":"3425957b118a0c40847ef7f473543baef5a24f0c7d8af198955180c8f297ee5a","src/ir/constant.rs":"6e9e9c82f2ded45d574d0a6029ce6cd3513b9de6329ed194ca5bab21ed1d1b9a","src/ir/dfg.rs":"106b8218512f6e684b14a45c448b8692bd2fe4384a366b79c54fe22e0a1a34b8","src/ir/entities.rs":"c5b3c1c15afaa694c25d5e887c3967c903879654bffcb81a978467ce7a8834f9","src/ir/extfunc.rs":"57ef6509acb504cdd292fc5a637486a1de15c78f8c9b2205ac820874592e54c4","src/ir/extname.rs":"977b2e380094e99cfdd080112bda709ca61a6d942e1e4c2015d39eaf3ea80f4c","src/ir/framelayout.rs":"2cfeb096e4cd06d924645cf9281dd609d35853f2248ba7fee547d8e7679fc330","src/ir/function.rs":"2dc8248b6f4cede4a3f2bec39261697dcf8081e6e5a2db119920e4f2f085ca82","src/ir/globalvalue.rs":"5d96fab89aa0932aaaa5128412aeb96a4ba8cc1315648f03b6553736f42f86a6","src/ir/heap.rs":"a59d3e5901412b53c0b53a8cdf10765ff5921de9c410ae9acea226c89827df3c","src/ir/immediates.rs":"323ff93cb36bb682374ad323f145e61ba554f01d7ffebebe058531cbc556b91a","src/ir/instructions.rs":"5eb1ef1e66f1d14fdf046a6aa6552bbc0ac74503026e5b6d0f52a3ec2d59a660","src/ir/jumptable.rs":"184fa640957e8b0e451dc594e4b348f9aff5fb5b54ab3d856ab19df25f4f3322","src/ir/layout.rs":"2956643a822e67a0c1196f8d3c81af11d0c0122b2d97427ce3ed0c57bb633cbf","src/ir/libcall.rs":"6e226a35bee1dfb867b55233da7f86b46c072645a20157947759b768caaa2c4a","src/ir/memflags.rs":"dbcf3798ab66dc764b73fb7f139a621c54cc6bcc683f1f70a33ed7e8c3486bfd","src/ir/mod.rs":"f35e2c11fc1750e0abf88cf442e2a8916932d4baf765050db894e53c7825c88e","src/ir/progpoint.rs":"a985a7fccde1e985ca24bf2344f16faa4cda7cffb30cb56bf27fabbb5727bc62","src/ir/sourceloc.rs":"67c66adace734645ddf311ecb22e975f20756e07c91e10f698a830cfc2cd08aa","src/ir/stackslot.rs":"5d489d21f17c9992d0862c38c661fab2a19e025a7f29a4417d0336d9bfc5f7f0","src/ir/table.rs":"dcc3b663a989b2b084402b08dc9a0e928dbd052e194a46a1886cc6f0cf1a5f2c","src/ir/trapcode.rs":"413090e632116d405ba69f3b0e6f4460e0a67c5dfb934e11c8eebde04d8e1af5","src/ir/types.rs":"ec261b6c3677f4113a2f7125da0df3fd66a1a666aebb19abd5cb49fcef372bc6","src/ir/valueloc.rs":"fc31e06b2b0f37333829c4658b7f6fa8a717e93e18a5c67a63947e5882bbe1a2","src/isa/arm32/abi.rs":"59abc42d75445f7f3335b035655083772e98e413ee58a72fc4e224620327b5ea","src/isa/arm32/binemit.rs":"eecd7296c27d2520db8e86dd462833ecf06afd33548b03ae676c02454cdd13c2","src/isa/arm32/enc_tables.rs":"e94b12af802de59484cab1124d2ac8a88d08433f6e1a476724ed0403f4b5967f","src/isa/arm32/mod.rs":"9ccd3a24afc921f35bb89f508d86fe5eb63e86e9c85d34132a01a131e19e2f61","src/isa/arm32/registers.rs":"100033c78e2a891ad90a2765137bd678f1d11ae4ba61974d1083106fa1324037","src/isa/arm32/settings.rs":"2314460f885c24f9571d640f9737a8e0b7d20ca02bcda1127f878fd3891c0529","src/isa/arm64/abi.rs":"c946f65b7731095734074e9c06964672cdf4c8352a54fe23f7411d874b27ec28","src/isa/arm64/binemit.rs":"3afbb78f6d9ae5614d908023f84b774c0493c8757ad86fd8301baf0928bb0104","src/isa/arm64/enc_tables.rs":"73fedf7da610a982e37c76e5211dbce880f77841b71c678b0dab2b9e7217cb7c","src/isa/arm64/mod.rs":"e89bbc1d0dcbce21378fd83ef5b73071cb51b2f5561092ae960aa229accc6f53","src/isa/arm64/registers.rs":"e8bc77f218c83cedec50e2b5b28b88e3301443bd02f7a80151748f2be4b31ea0","src/isa/arm64/settings.rs":"5405ce3560b7ba0705ef525c706eb9f1593e901e1767b837c012084397639042","src/isa/call_conv.rs":"e4782f3a45d292971ad64c7ca6c8f2f3ffe06003bd4bdc47cb3094979b8383bb","src/isa/constraints.rs":"296f473a95146a743ecb73d8d5908675be02e37607efd287f55322549dc25763","src/isa/enc_tables.rs":"382e714f9500afc292c563cb66d4c963d6787e58f197b1db242db7a099c22b9a","src/isa/encoding.rs":"22e21fdb8e15859c69e4f836bb61e1a82cd6838d093ce5fe641a90f16fb65c9e","src/isa/mod.rs":"5a299967fa47e2f0aa66bec0516e9cd96b8a16f38f32ba7b462a34158b66b3ea","src/isa/registers.rs":"61840d736b1943c3e54ac324db6f7de4f76170800f047dde267dcc9aa2d53e6a","src/isa/riscv/abi.rs":"aa60b701efcef417ee1262a95398343578dc1a30decc8e11044b74d41654ec51","src/isa/riscv/binemit.rs":"264d223da311d4482ebf2f55438b665c67b163058251bc78173c76ba983a31ef","src/isa/riscv/enc_tables.rs":"8491f2082b24c7dedeb7c36cfd913bf9aeaa0a4c8fc754166e9285f4ae002f40","src/isa/riscv/mod.rs":"fbbd48079ebd76d62a26550bd801878a0fe75a9fcca9a4cd951cf01ee74ec1ce","src/isa/riscv/registers.rs":"6275ec3ef19195d16556c1856cb23095f25a80c31d6b429eaa749d549515a6d3","src/isa/riscv/settings.rs":"e3c063add822ca366e845f5a19d25b56635e828b157a37d29aca5355650e6a66","src/isa/stack.rs":"c391216fb8ee6566e3b14aa4bd83ba85aef2bd23422a9dca2c8c6f47016372e2","src/isa/x86/abi.rs":"1fe47e753e1b79f2d7c67359f5b50958aa4137f4212415762441109c3cc3a2f9","src/isa/x86/binemit.rs":"1200819502de30f2f69b02978cfe3ed661d5c7c34ba854b757f6fe3e3adc7167","src/isa/x86/enc_tables.rs":"56ad027c0302913a254aabd88134ee1ade681de707016babedd5653e43dc9d7b","src/isa/x86/fde.rs":"78bc20ca10bfff6fcdd40c568271349bb82f7718b9030296d10c1f0fb3436fa2","src/isa/x86/mod.rs":"855e4f35af9ea0c86b0b035ff939fdce40bca51f7b7eba32299e7db8fc64f8a1","src/isa/x86/registers.rs":"1abbc1aa24c6fc4c7e610b6e840eab29046b821de08cf57fc05e2c2f665479c0","src/isa/x86/settings.rs":"d3e403db3507830f79bcc976c17340b57052cf1b50877fcf1a79549f2a054458","src/isa/x86/unwind.rs":"81da2df11f5010bfaed3832f316c2a51640e9bc296ac8735069ce72130865cff","src/iterators.rs":"d399a80bc65b97f7d650978e19086dcc1d280ac96d60628eac3d17eb363b0d71","src/legalizer/boundary.rs":"e111ebf8f806221ac4ad19acaac10d3a41ae617b62ba4ea412be291edfb2521f","src/legalizer/call.rs":"be6074c64c1a00e5e81159dd94c8401fef62205b22c15e07e0c56cf922554d00","src/legalizer/globalvalue.rs":"a5d09ee41a04ba991d7f5d2d8d8c30a209748d38501a005e0ea568df2663cbb5","src/legalizer/heap.rs":"8c6f4e59065593a2abacb21b94fc0c8e09860adaaf4429eba26ef67f0c404619","src/legalizer/libcall.rs":"859662cfc49a479a0b0ebad401f806eb067bddbc4be01994131302c2a89a8183","src/legalizer/mod.rs":"f9c30c33bdb80d6f68d06b8e7e524f35ad25458e38b9c223beb02f5d93f8b52d","src/legalizer/split.rs":"697f08886dbf35fcc69eccc7b597986a58cc73ca7d3cf5d581fffc658a0dad33","src/legalizer/table.rs":"c36d03525312e3191aba8ee00c26a87c1ea200f9a9a0370f0cc84eeacff71786","src/lib.rs":"c306a7aedcc183fda2c72c87129fe73829d49b80a0ed909c22732f0fd7bf1546","src/licm.rs":"75e94228c37a7d32cc9b0d51644439f9b1837768df67fd3de08ee43b8cdf8123","src/loop_analysis.rs":"4f23c08df9bc95195d68e9721a3a040c6192276ad33894c1225647034f01b23d","src/nan_canonicalization.rs":"dd853d0b1c1b5274513e9fb24b8beb8db877aca8fdfea5ceccbd1a80309c8842","src/partition_slice.rs":"861e778f887ea5d0841d730963565690fd8c298edddf08848d0d215ae5125eba","src/postopt.rs":"3a4f348dd529f5c948a4d9da3959ae30808af46d25b2bb6e3542044cf2e90c53","src/predicates.rs":"d4fa993d8b3036ac9e19d1c1d8880ab5b33030fff0a38d65e2a24b9f9d3956c9","src/print_errors.rs":"075b74520f47070b839b43714f55a46a7cc2697b9b0f24a7162d481b7e46b7d2","src/redundant_reload_remover.rs":"17e64c2f253743e9d111bd48709f763a2746cc8cb6a95d2bdd9d7bca605b0621","src/regalloc/affinity.rs":"ec5d688c24043a8aa72efcfbfddc14497cd9bab288c9d339e5c0150cdade2b1d","src/regalloc/branch_splitting.rs":"32e34197f84e30cff758f4db611a9c70dd587dd8d094729c34aa00303538c0d0","src/regalloc/coalescing.rs":"154842e7f380f2626c698283dbc5e0d5e7f0cc5d22b938e90312d17b71a8bb72","src/regalloc/coloring.rs":"ded1d8e531c38412fb19fe746fed65a6b6598819a29cd76c9b4bd5c4d0d6011a","src/regalloc/context.rs":"d85f86a8a79e7c939c0e696d30632ae3856001de75411828fc57c0b5b93e63ef","src/regalloc/diversion.rs":"2e474940b0c38610ca231faba7c7c3cfadf401a2f24247b6f3730ac862fce21f","src/regalloc/live_value_tracker.rs":"845dc3f43cc6b795fea51bf293e7c6ab4961d59ab6ca2670fcab7a2a9bd996be","src/regalloc/liveness.rs":"0b027b8e4444a715af1b93d594a293d2fd430ad06940da05b06a4750535e9652","src/regalloc/liverange.rs":"2e98802e90868051b53ddc8555db0ea98aabc77df7789df2a92627650a43227e","src/regalloc/mod.rs":"50399d6569687a87bf1481304aca42506d946e34465e38ca8093e06485ab5fb6","src/regalloc/pressure.rs":"8408213afe07d4532da699f6604aff111c7061d71b585a84c5ec8db31582314c","src/regalloc/register_set.rs":"c740d10a061c4b8527ce319842b519d743e93e64db53851360f9ca2c099fd652","src/regalloc/reload.rs":"2132bd4cf45ce60b7799277d36bda35c05064ee1c60798388b8f55a0668fca47","src/regalloc/safepoint.rs":"6db80500584ef4a90b60c0f3fec82eaa15bfa26fb8ab5d929bc262d9f9b1ba38","src/regalloc/solver.rs":"5ad745ce9075ae8ca742602411f260036df4598695a4f5f0905bd91efe2c69c9","src/regalloc/spilling.rs":"3b75be8be6568a091dd8a1fd174b099859c6e9969c03bd765b5fb50f52fcccb5","src/regalloc/virtregs.rs":"a01b5d3cb1753e344c6663dd73de00dd452d442990f89477610b22c86c9afdfd","src/result.rs":"a0f2f2356668a0d8c89b5ba25647f39af970509aabc0061c7f9e6b3474a93fad","src/scoped_hash_map.rs":"c8d0071ce7e19438e9995b5fca1ea0fca81234811943b06b344331f9742c3718","src/settings.rs":"52cf2107c870fae9f8bb06c1a1b1ce54b84ec84774fb4ab252e2473aa6147c3b","src/simple_gvn.rs":"1de1d0c0e028833350eda7186243f255c9db97fe04f0e6fa688b8a710caa78be","src/simple_preopt.rs":"3d58e4d1c2a5cd608477ca62ee97e919bab935471b93967c00afb93c0df2701c","src/stack_layout.rs":"a2a7118ce32053501357a2f56c506ff4c19937c09856e459ee9d361d74a23d9e","src/timing.rs":"231683891065f71a54c9c7616f7f9c5e2a7798b6d21b930cf9dbe703ad4784ed","src/topo_order.rs":"c092ee7a44e5f14962501eafd4478dfb855ce66af15d9c94a9b244ea30d6e991","src/unreachable_code.rs":"baea08a55b1e7eb2379fa2c4bb5ed4f5a536a35eafcb377f8ab79dc41d14d3d4","src/value_label.rs":"f0e430760d6489e4ee68d653def5b8cf8f9079176eea94f4e774bc69b3368e1b","src/verifier/cssa.rs":"2590b0ecbc134bbedac50915ed9c9e054c89f81e455c7bc0f37d4ddf57a38d05","src/verifier/flags.rs":"4c790104e98c6c3a5d167fa7575551f5bf20ea8ade5c7e1f92d4d5412d8df97e","src/verifier/liveness.rs":"b6ab6dfb1390cea8091b71a6f2fd629ee356987b6a0714e8773d7b0eb7fa889f","src/verifier/locations.rs":"2b4e62e1bb79551725414b5a77425c00e9ad56ad766d6293db1eb261b64f51f9","src/verifier/mod.rs":"6cc4fd9c0869d8b2f801adab1bee31a444f4b4df2348f92ada109d93269b80d1","src/write.rs":"9fe25abef4e1d60c755125e526d8f5e1a39e1e32b758520b3934b27446739faa"},"package":null}
\ No newline at end of file
+{"files":{"Cargo.toml":"216e29ba55f3134362a4fe8d48809111ab003cf88d690843ac77c8bb331d915e","LICENSE":"268872b9816f90fd8e85db5a28d33f8150ebb8dd016653fb39ef1f94f2686bc5","README.md":"e5127227a7db4a8aa92fa6613ed71801025790e696bb41b0323fb7f3c6f7495a","build.rs":"9fffedcfb42f2147f1a3f2b8d39af91e291768fe6f4e75ce19de1debfca7bfd8","src/abi.rs":"8e0d0c149007ec1bbc7128b806d184047a2b2aa8fc81ae73ac9d653e2650ff81","src/binemit/memorysink.rs":"7b04e31b9fc048709594b970f6ec775f15845e141ec1fab75df942593d4f8454","src/binemit/mod.rs":"3c41c48b77dace3cab4511726f4fca7148e2bff9f4a062c003799e1da9ba69a2","src/binemit/relaxation.rs":"e40b254bc30d4aaf7d6390d15071ea31352fc82cd57eb67a6602d53ba4612b67","src/binemit/shrink.rs":"552d64dff3b044bca77f39891d0e39ee619f6ec0669bf9917132c97becea79b0","src/binemit/stackmap.rs":"3f141f4652ec5148fbcf2db88d0ac7881823158b528c989770eacd4165afa39b","src/bitset.rs":"c4fa43fff52a8f2d343e3edbeeb26d851c64ed811e3d3aa9e2af80358d43be14","src/cfg_printer.rs":"a4cd85ecb2c403b29dc3fc6c60ee7f97b6ed602e8ba88ec87accb988d009271e","src/constant_hash.rs":"8f53afb38891fbdab8553c7a89e61f0ce30947a22fb24ae84523c9a1ab025c3f","src/context.rs":"d47182f15327dbd775d9bbeae87439a108f8e12ac20515ee59934d059aaf5fb2","src/cursor.rs":"97d8beadadd45c27f26e7a569a6e5b1068d7d2e391633b891985379c71165259","src/dbg.rs":"1898d94cff0975815eb348651702e95c8f2f63886501d3b7043ee75668480472","src/dce.rs":"3af68cbbc6acfa4e4f2105d9343ae62d58f61dd5746e5d24fb49f38a02636081","src/divconst_magic_numbers.rs":"e7f8f46f3a25ed7155890e9d76c10f5dde9dc5bbcebb623c8166fa415abdd959","src/dominator_tree.rs":"b3a5c7837150390a78ade90807965dfcb8768a7e3ae9ee02f2e4a1ad8f3bafa9","src/flowgraph.rs":"71490e2f7a1ea905758a258b2bebe77f125302f446f9839dd60003fdafaef5fe","src/fx.rs":"8a5d07487906d8316a179e826fcd817a92a4860686256a6fd9d78ba47c63f330","src/ir/builder.rs":"3425957b118a0c40847ef7f473543baef5a24f0c7d8af198955180c8f297ee5a","src/ir/constant.rs":"6e9e9c82f2ded45d574d0a6029ce6cd3513b9de6329ed194ca5bab21ed1d1b9a","src/ir/dfg.rs":"106b8218512f6e684b14a45c448b8692bd2fe4384a366b79c54fe22e0a1a34b8","src/ir/entities.rs":"c5b3c1c15afaa694c25d5e887c3967c903879654bffcb81a978467ce7a8834f9","src/ir/extfunc.rs":"57ef6509acb504cdd292fc5a637486a1de15c78f8c9b2205ac820874592e54c4","src/ir/extname.rs":"977b2e380094e99cfdd080112bda709ca61a6d942e1e4c2015d39eaf3ea80f4c","src/ir/framelayout.rs":"2cfeb096e4cd06d924645cf9281dd609d35853f2248ba7fee547d8e7679fc330","src/ir/function.rs":"2dc8248b6f4cede4a3f2bec39261697dcf8081e6e5a2db119920e4f2f085ca82","src/ir/globalvalue.rs":"5d96fab89aa0932aaaa5128412aeb96a4ba8cc1315648f03b6553736f42f86a6","src/ir/heap.rs":"a59d3e5901412b53c0b53a8cdf10765ff5921de9c410ae9acea226c89827df3c","src/ir/immediates.rs":"323ff93cb36bb682374ad323f145e61ba554f01d7ffebebe058531cbc556b91a","src/ir/instructions.rs":"5eb1ef1e66f1d14fdf046a6aa6552bbc0ac74503026e5b6d0f52a3ec2d59a660","src/ir/jumptable.rs":"184fa640957e8b0e451dc594e4b348f9aff5fb5b54ab3d856ab19df25f4f3322","src/ir/layout.rs":"2956643a822e67a0c1196f8d3c81af11d0c0122b2d97427ce3ed0c57bb633cbf","src/ir/libcall.rs":"6e226a35bee1dfb867b55233da7f86b46c072645a20157947759b768caaa2c4a","src/ir/memflags.rs":"dbcf3798ab66dc764b73fb7f139a621c54cc6bcc683f1f70a33ed7e8c3486bfd","src/ir/mod.rs":"f35e2c11fc1750e0abf88cf442e2a8916932d4baf765050db894e53c7825c88e","src/ir/progpoint.rs":"a985a7fccde1e985ca24bf2344f16faa4cda7cffb30cb56bf27fabbb5727bc62","src/ir/sourceloc.rs":"67c66adace734645ddf311ecb22e975f20756e07c91e10f698a830cfc2cd08aa","src/ir/stackslot.rs":"5d489d21f17c9992d0862c38c661fab2a19e025a7f29a4417d0336d9bfc5f7f0","src/ir/table.rs":"dcc3b663a989b2b084402b08dc9a0e928dbd052e194a46a1886cc6f0cf1a5f2c","src/ir/trapcode.rs":"413090e632116d405ba69f3b0e6f4460e0a67c5dfb934e11c8eebde04d8e1af5","src/ir/types.rs":"ec261b6c3677f4113a2f7125da0df3fd66a1a666aebb19abd5cb49fcef372bc6","src/ir/valueloc.rs":"fc31e06b2b0f37333829c4658b7f6fa8a717e93e18a5c67a63947e5882bbe1a2","src/isa/arm32/abi.rs":"59abc42d75445f7f3335b035655083772e98e413ee58a72fc4e224620327b5ea","src/isa/arm32/binemit.rs":"eecd7296c27d2520db8e86dd462833ecf06afd33548b03ae676c02454cdd13c2","src/isa/arm32/enc_tables.rs":"e94b12af802de59484cab1124d2ac8a88d08433f6e1a476724ed0403f4b5967f","src/isa/arm32/mod.rs":"9ccd3a24afc921f35bb89f508d86fe5eb63e86e9c85d34132a01a131e19e2f61","src/isa/arm32/registers.rs":"100033c78e2a891ad90a2765137bd678f1d11ae4ba61974d1083106fa1324037","src/isa/arm32/settings.rs":"2314460f885c24f9571d640f9737a8e0b7d20ca02bcda1127f878fd3891c0529","src/isa/arm64/abi.rs":"c946f65b7731095734074e9c06964672cdf4c8352a54fe23f7411d874b27ec28","src/isa/arm64/binemit.rs":"3afbb78f6d9ae5614d908023f84b774c0493c8757ad86fd8301baf0928bb0104","src/isa/arm64/enc_tables.rs":"73fedf7da610a982e37c76e5211dbce880f77841b71c678b0dab2b9e7217cb7c","src/isa/arm64/mod.rs":"e89bbc1d0dcbce21378fd83ef5b73071cb51b2f5561092ae960aa229accc6f53","src/isa/arm64/registers.rs":"e8bc77f218c83cedec50e2b5b28b88e3301443bd02f7a80151748f2be4b31ea0","src/isa/arm64/settings.rs":"5405ce3560b7ba0705ef525c706eb9f1593e901e1767b837c012084397639042","src/isa/call_conv.rs":"e4782f3a45d292971ad64c7ca6c8f2f3ffe06003bd4bdc47cb3094979b8383bb","src/isa/constraints.rs":"296f473a95146a743ecb73d8d5908675be02e37607efd287f55322549dc25763","src/isa/enc_tables.rs":"382e714f9500afc292c563cb66d4c963d6787e58f197b1db242db7a099c22b9a","src/isa/encoding.rs":"22e21fdb8e15859c69e4f836bb61e1a82cd6838d093ce5fe641a90f16fb65c9e","src/isa/mod.rs":"565c7965d0d098ad9a1cc0e69cc2c91a3b348279a9fceeb546f609696ea92000","src/isa/registers.rs":"61840d736b1943c3e54ac324db6f7de4f76170800f047dde267dcc9aa2d53e6a","src/isa/riscv/abi.rs":"aa60b701efcef417ee1262a95398343578dc1a30decc8e11044b74d41654ec51","src/isa/riscv/binemit.rs":"264d223da311d4482ebf2f55438b665c67b163058251bc78173c76ba983a31ef","src/isa/riscv/enc_tables.rs":"8491f2082b24c7dedeb7c36cfd913bf9aeaa0a4c8fc754166e9285f4ae002f40","src/isa/riscv/mod.rs":"fbbd48079ebd76d62a26550bd801878a0fe75a9fcca9a4cd951cf01ee74ec1ce","src/isa/riscv/registers.rs":"6275ec3ef19195d16556c1856cb23095f25a80c31d6b429eaa749d549515a6d3","src/isa/riscv/settings.rs":"e3c063add822ca366e845f5a19d25b56635e828b157a37d29aca5355650e6a66","src/isa/stack.rs":"c391216fb8ee6566e3b14aa4bd83ba85aef2bd23422a9dca2c8c6f47016372e2","src/isa/x86/abi.rs":"1fe47e753e1b79f2d7c67359f5b50958aa4137f4212415762441109c3cc3a2f9","src/isa/x86/binemit.rs":"fb5051471cd9c860455a0c1d74aec7d919d4c7229ada10222631c3694f9a091f","src/isa/x86/enc_tables.rs":"bf7d0d49d86bd7bf662c71d91553d1401ff4dbd2ec6641bd8e8bdb3bfdf91a17","src/isa/x86/fde.rs":"3cd20684b82cad2878a87237719808a84628cff3a36d356232a27ed74782f09b","src/isa/x86/mod.rs":"027ed2842e36ea46a7b526386567b1b23384638aad29a902b717425d5ed2311e","src/isa/x86/registers.rs":"1abbc1aa24c6fc4c7e610b6e840eab29046b821de08cf57fc05e2c2f665479c0","src/isa/x86/settings.rs":"d3e403db3507830f79bcc976c17340b57052cf1b50877fcf1a79549f2a054458","src/isa/x86/unwind.rs":"81da2df11f5010bfaed3832f316c2a51640e9bc296ac8735069ce72130865cff","src/iterators.rs":"d399a80bc65b97f7d650978e19086dcc1d280ac96d60628eac3d17eb363b0d71","src/legalizer/boundary.rs":"e111ebf8f806221ac4ad19acaac10d3a41ae617b62ba4ea412be291edfb2521f","src/legalizer/call.rs":"be6074c64c1a00e5e81159dd94c8401fef62205b22c15e07e0c56cf922554d00","src/legalizer/globalvalue.rs":"a5d09ee41a04ba991d7f5d2d8d8c30a209748d38501a005e0ea568df2663cbb5","src/legalizer/heap.rs":"8c6f4e59065593a2abacb21b94fc0c8e09860adaaf4429eba26ef67f0c404619","src/legalizer/libcall.rs":"859662cfc49a479a0b0ebad401f806eb067bddbc4be01994131302c2a89a8183","src/legalizer/mod.rs":"f9c30c33bdb80d6f68d06b8e7e524f35ad25458e38b9c223beb02f5d93f8b52d","src/legalizer/split.rs":"697f08886dbf35fcc69eccc7b597986a58cc73ca7d3cf5d581fffc658a0dad33","src/legalizer/table.rs":"c36d03525312e3191aba8ee00c26a87c1ea200f9a9a0370f0cc84eeacff71786","src/lib.rs":"c306a7aedcc183fda2c72c87129fe73829d49b80a0ed909c22732f0fd7bf1546","src/licm.rs":"75e94228c37a7d32cc9b0d51644439f9b1837768df67fd3de08ee43b8cdf8123","src/loop_analysis.rs":"4f23c08df9bc95195d68e9721a3a040c6192276ad33894c1225647034f01b23d","src/nan_canonicalization.rs":"dd853d0b1c1b5274513e9fb24b8beb8db877aca8fdfea5ceccbd1a80309c8842","src/partition_slice.rs":"861e778f887ea5d0841d730963565690fd8c298edddf08848d0d215ae5125eba","src/postopt.rs":"3a4f348dd529f5c948a4d9da3959ae30808af46d25b2bb6e3542044cf2e90c53","src/predicates.rs":"d4fa993d8b3036ac9e19d1c1d8880ab5b33030fff0a38d65e2a24b9f9d3956c9","src/print_errors.rs":"075b74520f47070b839b43714f55a46a7cc2697b9b0f24a7162d481b7e46b7d2","src/redundant_reload_remover.rs":"17e64c2f253743e9d111bd48709f763a2746cc8cb6a95d2bdd9d7bca605b0621","src/regalloc/affinity.rs":"ec5d688c24043a8aa72efcfbfddc14497cd9bab288c9d339e5c0150cdade2b1d","src/regalloc/branch_splitting.rs":"32e34197f84e30cff758f4db611a9c70dd587dd8d094729c34aa00303538c0d0","src/regalloc/coalescing.rs":"154842e7f380f2626c698283dbc5e0d5e7f0cc5d22b938e90312d17b71a8bb72","src/regalloc/coloring.rs":"ded1d8e531c38412fb19fe746fed65a6b6598819a29cd76c9b4bd5c4d0d6011a","src/regalloc/context.rs":"d85f86a8a79e7c939c0e696d30632ae3856001de75411828fc57c0b5b93e63ef","src/regalloc/diversion.rs":"2e474940b0c38610ca231faba7c7c3cfadf401a2f24247b6f3730ac862fce21f","src/regalloc/live_value_tracker.rs":"845dc3f43cc6b795fea51bf293e7c6ab4961d59ab6ca2670fcab7a2a9bd996be","src/regalloc/liveness.rs":"0b027b8e4444a715af1b93d594a293d2fd430ad06940da05b06a4750535e9652","src/regalloc/liverange.rs":"2e98802e90868051b53ddc8555db0ea98aabc77df7789df2a92627650a43227e","src/regalloc/mod.rs":"50399d6569687a87bf1481304aca42506d946e34465e38ca8093e06485ab5fb6","src/regalloc/pressure.rs":"8408213afe07d4532da699f6604aff111c7061d71b585a84c5ec8db31582314c","src/regalloc/register_set.rs":"c740d10a061c4b8527ce319842b519d743e93e64db53851360f9ca2c099fd652","src/regalloc/reload.rs":"2132bd4cf45ce60b7799277d36bda35c05064ee1c60798388b8f55a0668fca47","src/regalloc/safepoint.rs":"6db80500584ef4a90b60c0f3fec82eaa15bfa26fb8ab5d929bc262d9f9b1ba38","src/regalloc/solver.rs":"5ad745ce9075ae8ca742602411f260036df4598695a4f5f0905bd91efe2c69c9","src/regalloc/spilling.rs":"3b75be8be6568a091dd8a1fd174b099859c6e9969c03bd765b5fb50f52fcccb5","src/regalloc/virtregs.rs":"a01b5d3cb1753e344c6663dd73de00dd452d442990f89477610b22c86c9afdfd","src/result.rs":"a0f2f2356668a0d8c89b5ba25647f39af970509aabc0061c7f9e6b3474a93fad","src/scoped_hash_map.rs":"c8d0071ce7e19438e9995b5fca1ea0fca81234811943b06b344331f9742c3718","src/settings.rs":"52cf2107c870fae9f8bb06c1a1b1ce54b84ec84774fb4ab252e2473aa6147c3b","src/simple_gvn.rs":"1de1d0c0e028833350eda7186243f255c9db97fe04f0e6fa688b8a710caa78be","src/simple_preopt.rs":"b7c0891d85b4ce8644407ac9a44939f3eec61b03a9a142b76f98b7b5cf928299","src/stack_layout.rs":"a2a7118ce32053501357a2f56c506ff4c19937c09856e459ee9d361d74a23d9e","src/timing.rs":"231683891065f71a54c9c7616f7f9c5e2a7798b6d21b930cf9dbe703ad4784ed","src/topo_order.rs":"c092ee7a44e5f14962501eafd4478dfb855ce66af15d9c94a9b244ea30d6e991","src/unreachable_code.rs":"baea08a55b1e7eb2379fa2c4bb5ed4f5a536a35eafcb377f8ab79dc41d14d3d4","src/value_label.rs":"f0e430760d6489e4ee68d653def5b8cf8f9079176eea94f4e774bc69b3368e1b","src/verifier/cssa.rs":"2590b0ecbc134bbedac50915ed9c9e054c89f81e455c7bc0f37d4ddf57a38d05","src/verifier/flags.rs":"4c790104e98c6c3a5d167fa7575551f5bf20ea8ade5c7e1f92d4d5412d8df97e","src/verifier/liveness.rs":"b6ab6dfb1390cea8091b71a6f2fd629ee356987b6a0714e8773d7b0eb7fa889f","src/verifier/locations.rs":"2b4e62e1bb79551725414b5a77425c00e9ad56ad766d6293db1eb261b64f51f9","src/verifier/mod.rs":"6cc4fd9c0869d8b2f801adab1bee31a444f4b4df2348f92ada109d93269b80d1","src/write.rs":"9fe25abef4e1d60c755125e526d8f5e1a39e1e32b758520b3934b27446739faa"},"package":null}
\ No newline at end of file
--- a/third_party/rust/cranelift-codegen/Cargo.toml
+++ b/third_party/rust/cranelift-codegen/Cargo.toml
@@ -1,41 +1,41 @@
 [package]
 authors = ["The Cranelift Project Developers"]
 name = "cranelift-codegen"
-version = "0.60.0"
+version = "0.62.0"
 description = "Low-level code generator library"
 license = "Apache-2.0 WITH LLVM-exception"
 documentation = "https://docs.rs/cranelift-codegen"
 repository = "https://github.com/bytecodealliance/wasmtime"
 categories = ["no-std"]
 readme = "README.md"
 keywords = ["compile", "compiler", "jit"]
 build = "build.rs"
 edition = "2018"
 
 [dependencies]
-cranelift-codegen-shared = { path = "./shared", version = "0.60.0" }
-cranelift-entity = { path = "../entity", version = "0.60.0" }
-cranelift-bforest = { path = "../bforest", version = "0.60.0" }
+cranelift-codegen-shared = { path = "./shared", version = "0.62.0" }
+cranelift-entity = { path = "../entity", version = "0.62.0" }
+cranelift-bforest = { path = "../bforest", version = "0.62.0" }
 hashbrown = { version = "0.7", optional = true }
 target-lexicon = "0.10"
 log = { version = "0.4.6", default-features = false }
 serde = { version = "1.0.94", features = ["derive"], optional = true }
 gimli = { version = "0.20.0", default-features = false, features = ["write"], optional = true }
 smallvec = { version = "1.0.0" }
 thiserror = "1.0.4"
 byteorder = { version = "1.3.2", default-features = false }
 # It is a goal of the cranelift-codegen crate to have minimal external dependencies.
 # Please don't add any unless they are essential to the task of creating binary
 # machine code. Integration tests that need external dependencies can be
 # accomodated in `tests`.
 
 [build-dependencies]
-cranelift-codegen-meta = { path = "meta", version = "0.60.0" }
+cranelift-codegen-meta = { path = "meta", version = "0.62.0" }
 
 [features]
 default = ["std", "unwind"]
 
 # The "std" feature enables use of libstd. The "core" feature enables use
 # of some minimal std-like replacement libraries. At least one of these two
 # features need to be enabled.
 std = []
--- a/third_party/rust/cranelift-codegen/src/binemit/memorysink.rs
+++ b/third_party/rust/cranelift-codegen/src/binemit/memorysink.rs
@@ -11,17 +11,17 @@
 //! The `MemoryCodeSink` type fixes the performance problem because it is a type known to
 //! `TargetIsa` so it can specialize its machine code generation for the type. The trade-off is
 //! that a `MemoryCodeSink` will always write binary machine code to raw memory. It forwards any
 //! relocations to a `RelocSink` trait object. Relocations are less frequent than the
 //! `CodeSink::put*` methods, so the performance impact of the virtual callbacks is less severe.
 use super::{Addend, CodeInfo, CodeOffset, CodeSink, Reloc};
 use crate::binemit::stackmap::Stackmap;
 use crate::ir::entities::Value;
-use crate::ir::{ConstantOffset, ExternalName, Function, JumpTable, SourceLoc, TrapCode};
+use crate::ir::{ConstantOffset, ExternalName, Function, JumpTable, Opcode, SourceLoc, TrapCode};
 use crate::isa::TargetIsa;
 use core::ptr::write_unaligned;
 
 /// A `CodeSink` that writes binary machine code directly into memory.
 ///
 /// A `MemoryCodeSink` object should be used when emitting a Cranelift IR function into executable
 /// memory. It writes machine code directly to a raw pointer without any bounds checking, so make
 /// sure to allocate enough memory for the whole function. The number of bytes required is returned
@@ -73,23 +73,34 @@ impl<'a> MemoryCodeSink<'a> {
 }
 
 /// A trait for receiving relocations for code that is emitted directly into memory.
 pub trait RelocSink {
     /// Add a relocation referencing a block at the current offset.
     fn reloc_block(&mut self, _: CodeOffset, _: Reloc, _: CodeOffset);
 
     /// Add a relocation referencing an external symbol at the current offset.
-    fn reloc_external(&mut self, _: CodeOffset, _: Reloc, _: &ExternalName, _: Addend);
+    fn reloc_external(
+        &mut self,
+        _: CodeOffset,
+        _: SourceLoc,
+        _: Reloc,
+        _: &ExternalName,
+        _: Addend,
+    );
 
     /// Add a relocation referencing a constant.
     fn reloc_constant(&mut self, _: CodeOffset, _: Reloc, _: ConstantOffset);
 
     /// Add a relocation referencing a jump table.
     fn reloc_jt(&mut self, _: CodeOffset, _: Reloc, _: JumpTable);
+
+    /// Track a call site whose return address is the given CodeOffset, for the given opcode. Does
+    /// nothing in general, only useful for certain embedders (SpiderMonkey).
+    fn add_call_site(&mut self, _: Opcode, _: CodeOffset, _: SourceLoc) {}
 }
 
 /// A trait for receiving trap codes and offsets.
 ///
 /// If you don't need information about possible traps, you can use the
 /// [`NullTrapSink`](NullTrapSink) implementation.
 pub trait TrapSink {
     /// Add trap information for a specific offset.
@@ -127,19 +138,25 @@ impl<'a> CodeSink for MemoryCodeSink<'a>
         self.write(x);
     }
 
     fn reloc_block(&mut self, rel: Reloc, block_offset: CodeOffset) {
         let ofs = self.offset();
         self.relocs.reloc_block(ofs, rel, block_offset);
     }
 
-    fn reloc_external(&mut self, rel: Reloc, name: &ExternalName, addend: Addend) {
+    fn reloc_external(
+        &mut self,
+        srcloc: SourceLoc,
+        rel: Reloc,
+        name: &ExternalName,
+        addend: Addend,
+    ) {
         let ofs = self.offset();
-        self.relocs.reloc_external(ofs, rel, name, addend);
+        self.relocs.reloc_external(ofs, srcloc, rel, name, addend);
     }
 
     fn reloc_constant(&mut self, rel: Reloc, constant_offset: ConstantOffset) {
         let ofs = self.offset();
         self.relocs.reloc_constant(ofs, rel, constant_offset);
     }
 
     fn reloc_jt(&mut self, rel: Reloc, jt: JumpTable) {
@@ -165,27 +182,44 @@ impl<'a> CodeSink for MemoryCodeSink<'a>
         self.info.total_size = self.offset();
     }
 
     fn add_stackmap(&mut self, val_list: &[Value], func: &Function, isa: &dyn TargetIsa) {
         let ofs = self.offset();
         let stackmap = Stackmap::from_values(&val_list, func, isa);
         self.stackmaps.add_stackmap(ofs, stackmap);
     }
+
+    fn add_call_site(&mut self, opcode: Opcode, loc: SourceLoc) {
+        debug_assert!(
+            opcode.is_call(),
+            "adding call site info for a non-call instruction."
+        );
+        let ret_addr = self.offset();
+        self.relocs.add_call_site(opcode, ret_addr, loc);
+    }
 }
 
 /// A `RelocSink` implementation that does nothing, which is convenient when
 /// compiling code that does not relocate anything.
 pub struct NullRelocSink {}
 
 impl RelocSink for NullRelocSink {
-    fn reloc_block(&mut self, _: u32, _: Reloc, _: u32) {}
-    fn reloc_external(&mut self, _: u32, _: Reloc, _: &ExternalName, _: i64) {}
+    fn reloc_block(&mut self, _: CodeOffset, _: Reloc, _: CodeOffset) {}
+    fn reloc_external(
+        &mut self,
+        _: CodeOffset,
+        _: SourceLoc,
+        _: Reloc,
+        _: &ExternalName,
+        _: Addend,
+    ) {
+    }
     fn reloc_constant(&mut self, _: CodeOffset, _: Reloc, _: ConstantOffset) {}
-    fn reloc_jt(&mut self, _: u32, _: Reloc, _: JumpTable) {}
+    fn reloc_jt(&mut self, _: CodeOffset, _: Reloc, _: JumpTable) {}
 }
 
 /// A `TrapSink` implementation that does nothing, which is convenient when
 /// compiling code that does not rely on trapping semantics.
 pub struct NullTrapSink {}
 
 impl TrapSink for NullTrapSink {
     fn trap(&mut self, _offset: CodeOffset, _srcloc: SourceLoc, _code: TrapCode) {}
--- a/third_party/rust/cranelift-codegen/src/binemit/mod.rs
+++ b/third_party/rust/cranelift-codegen/src/binemit/mod.rs
@@ -11,17 +11,19 @@ mod stackmap;
 pub use self::memorysink::{
     MemoryCodeSink, NullRelocSink, NullStackmapSink, NullTrapSink, RelocSink, StackmapSink,
     TrapSink,
 };
 pub use self::relaxation::relax_branches;
 pub use self::shrink::shrink_instructions;
 pub use self::stackmap::Stackmap;
 use crate::ir::entities::Value;
-use crate::ir::{ConstantOffset, ExternalName, Function, Inst, JumpTable, SourceLoc, TrapCode};
+use crate::ir::{
+    ConstantOffset, ExternalName, Function, Inst, JumpTable, Opcode, SourceLoc, TrapCode,
+};
 use crate::isa::TargetIsa;
 pub use crate::regalloc::RegDiversions;
 use core::fmt;
 #[cfg(feature = "enable-serde")]
 use serde::{Deserialize, Serialize};
 
 /// Offset in bytes from the beginning of the function.
 ///
@@ -135,17 +137,17 @@ pub trait CodeSink {
 
     /// Add 8 bytes to the code section.
     fn put8(&mut self, _: u64);
 
     /// Add a relocation referencing a block at the current offset.
     fn reloc_block(&mut self, _: Reloc, _: CodeOffset);
 
     /// Add a relocation referencing an external symbol plus the addend at the current offset.
-    fn reloc_external(&mut self, _: Reloc, _: &ExternalName, _: Addend);
+    fn reloc_external(&mut self, _: SourceLoc, _: Reloc, _: &ExternalName, _: Addend);
 
     /// Add a relocation referencing a constant.
     fn reloc_constant(&mut self, _: Reloc, _: ConstantOffset);
 
     /// Add a relocation referencing a jump table.
     fn reloc_jt(&mut self, _: Reloc, _: JumpTable);
 
     /// Add trap information for the current offset.
@@ -157,16 +159,21 @@ pub trait CodeSink {
     /// Jump table output is complete, raw read-only data may follow.
     fn begin_rodata(&mut self);
 
     /// Read-only data output is complete, we're done.
     fn end_codegen(&mut self);
 
     /// Add a stackmap at the current code offset.
     fn add_stackmap(&mut self, _: &[Value], _: &Function, _: &dyn TargetIsa);
+
+    /// Add a call site for a call with the given opcode, returning at the current offset.
+    fn add_call_site(&mut self, _: Opcode, _: SourceLoc) {
+        // Default implementation doesn't need to do anything.
+    }
 }
 
 /// Type of the frame unwind information.
 #[derive(Debug, Copy, Clone, PartialEq, Eq)]
 pub enum FrameUnwindKind {
     /// Windows fastcall unwinding (as in .pdata).
     Fastcall,
     /// FDE entry for libunwind (similar to .eh_frame format).
--- a/third_party/rust/cranelift-codegen/src/isa/mod.rs
+++ b/third_party/rust/cranelift-codegen/src/isa/mod.rs
@@ -69,16 +69,22 @@ use target_lexicon::{triple, Architectur
 use thiserror::Error;
 
 #[cfg(feature = "riscv")]
 mod riscv;
 
 #[cfg(feature = "x86")]
 mod x86;
 
+#[cfg(all(feature = "x86", feature = "unwind"))]
+/// Expose the register-mapping functionality necessary for exception handling, debug, etc.
+pub mod fde {
+    pub use super::x86::map_reg;
+}
+
 #[cfg(feature = "arm32")]
 mod arm32;
 
 #[cfg(feature = "arm64")]
 mod arm64;
 
 mod call_conv;
 mod constraints;
--- a/third_party/rust/cranelift-codegen/src/isa/x86/binemit.rs
+++ b/third_party/rust/cranelift-codegen/src/isa/x86/binemit.rs
@@ -69,20 +69,25 @@ fn rex3(rm: RegUnit, reg: RegUnit, index
 fn evex2(rm: RegUnit, reg: RegUnit) -> u8 {
     let b = (!(rm >> 3) & 1) as u8;
     let x = (!(rm >> 4) & 1) as u8;
     let r = (!(reg >> 3) & 1) as u8;
     let r_ = (!(reg >> 4) & 1) as u8;
     0x00 | r_ | (b << 1) | (x << 2) | (r << 3)
 }
 
-/// Determines whether a REX prefix should be emitted.
+/// Determines whether a REX prefix should be emitted. A REX byte always has 0100 in bits 7:4; bits
+/// 3:0 correspond to WRXB. W allows certain instructions to declare a 64-bit operand size; because
+/// [needs_rex] is only used by [infer_rex] and we prevent [infer_rex] from using [w] in
+/// [Template::build], we do not need to check again whether [w] forces an inferred REX prefix--it
+/// always does and should be encoded like `.rex().w()`. The RXB are extension of ModR/M or SIB
+/// fields; see section 2.2.1.2 in the Intel Software Development Manual.
 #[inline]
-fn needs_rex(bits: u16, rex: u8) -> bool {
-    rex != BASE_REX || EncodingBits::from(bits).rex_w() == 1
+fn needs_rex(rex: u8) -> bool {
+    rex != BASE_REX
 }
 
 // Emit a REX prefix.
 //
 // The R, X, and B bits are computed from registers using the functions above. The W bit is
 // extracted from `bits`.
 fn rex_prefix<CS: CodeSink + ?Sized>(bits: u16, rex: u8, sink: &mut CS) {
     debug_assert_eq!(rex & 0xf8, BASE_REX);
@@ -102,17 +107,17 @@ fn put_rexop1<CS: CodeSink + ?Sized>(bit
     debug_assert_eq!(bits & 0x0f00, 0, "Invalid encoding bits for RexOp1*");
     rex_prefix(bits, rex, sink);
     sink.put1(bits as u8);
 }
 
 /// Emit a single-byte opcode with inferred REX prefix.
 fn put_dynrexop1<CS: CodeSink + ?Sized>(bits: u16, rex: u8, sink: &mut CS) {
     debug_assert_eq!(bits & 0x0f00, 0, "Invalid encoding bits for DynRexOp1*");
-    if needs_rex(bits, rex) {
+    if needs_rex(rex) {
         rex_prefix(bits, rex, sink);
     }
     sink.put1(bits as u8);
 }
 
 // Emit two-byte opcode: 0F XX
 fn put_op2<CS: CodeSink + ?Sized>(bits: u16, rex: u8, sink: &mut CS) {
     debug_assert_eq!(bits & 0x8f00, 0x0400, "Invalid encoding bits for Op2*");
@@ -131,17 +136,17 @@ fn put_rexop2<CS: CodeSink + ?Sized>(bit
 
 /// Emit two-byte opcode: 0F XX with inferred REX prefix.
 fn put_dynrexop2<CS: CodeSink + ?Sized>(bits: u16, rex: u8, sink: &mut CS) {
     debug_assert_eq!(
         bits & 0x0f00,
         0x0400,
         "Invalid encoding bits for DynRexOp2*"
     );
-    if needs_rex(bits, rex) {
+    if needs_rex(rex) {
         rex_prefix(bits, rex, sink);
     }
     sink.put1(0x0f);
     sink.put1(bits as u8);
 }
 
 // Emit single-byte opcode with mandatory prefix.
 fn put_mp1<CS: CodeSink + ?Sized>(bits: u16, rex: u8, sink: &mut CS) {
@@ -185,17 +190,17 @@ fn put_rexmp2<CS: CodeSink + ?Sized>(bit
 fn put_dynrexmp2<CS: CodeSink + ?Sized>(bits: u16, rex: u8, sink: &mut CS) {
     debug_assert_eq!(
         bits & 0x0c00,
         0x0400,
         "Invalid encoding bits for DynRexMp2*"
     );
     let enc = EncodingBits::from(bits);
     sink.put1(PREFIX[(enc.pp() - 1) as usize]);
-    if needs_rex(bits, rex) {
+    if needs_rex(rex) {
         rex_prefix(bits, rex, sink);
     }
     sink.put1(0x0f);
     sink.put1(bits as u8);
 }
 
 /// Emit three-byte opcode (0F 3[8A] XX) with mandatory prefix.
 fn put_mp3<CS: CodeSink + ?Sized>(bits: u16, rex: u8, sink: &mut CS) {
@@ -223,17 +228,17 @@ fn put_rexmp3<CS: CodeSink + ?Sized>(bit
 fn put_dynrexmp3<CS: CodeSink + ?Sized>(bits: u16, rex: u8, sink: &mut CS) {
     debug_assert_eq!(
         bits & 0x0800,
         0x0800,
         "Invalid encoding bits for DynRexMp3*"
     );
     let enc = EncodingBits::from(bits);
     sink.put1(PREFIX[(enc.pp() - 1) as usize]);
-    if needs_rex(bits, rex) {
+    if needs_rex(rex) {
         rex_prefix(bits, rex, sink);
     }
     sink.put1(0x0f);
     sink.put1(OP3_BYTE2[(enc.mm() - 2) as usize]);
     sink.put1(bits as u8);
 }
 
 /// Defines the EVEX context for the `L'`, `L`, and `b` bits (bits 6:4 of EVEX P2 byte). Table 2-36 in
--- a/third_party/rust/cranelift-codegen/src/isa/x86/enc_tables.rs
+++ b/third_party/rust/cranelift-codegen/src/isa/x86/enc_tables.rs
@@ -11,18 +11,16 @@ use crate::isa::constraints::*;
 use crate::isa::enc_tables::*;
 use crate::isa::encoding::base_size;
 use crate::isa::encoding::{Encoding, RecipeSizing};
 use crate::isa::RegUnit;
 use crate::isa::{self, TargetIsa};
 use crate::predicates;
 use crate::regalloc::RegDiversions;
 
-use cranelift_codegen_shared::isa::x86::EncodingBits;
-
 include!(concat!(env!("OUT_DIR"), "/encoding-x86.rs"));
 include!(concat!(env!("OUT_DIR"), "/legalize-x86.rs"));
 
 /// Whether the REX prefix is needed for encoding extended registers (via REX.RXB).
 ///
 /// Normal x86 instructions have only 3 bits for encoding a register.
 /// The REX prefix adds REX.R, REX,X, and REX.B bits, interpreted as fourth bits.
 pub fn is_extended_reg(reg: RegUnit) -> bool {
@@ -127,141 +125,172 @@ fn size_plus_maybe_sib_or_offset_for_inr
 /// require a dynamic REX prefix and if the second input register (inreg1) requires a SIB or offset.
 fn size_plus_maybe_sib_or_offset_inreg1_plus_rex_prefix_for_inreg0_inreg1(
     sizing: &RecipeSizing,
     enc: Encoding,
     inst: Inst,
     divert: &RegDiversions,
     func: &Function,
 ) -> u8 {
-    let needs_rex = (EncodingBits::from(enc.bits()).rex_w() != 0)
-        || test_input(0, inst, divert, func, is_extended_reg)
+    // No need to check for REX.W in `needs_rex` because `infer_rex().w()` is not allowed.
+    let needs_rex = test_input(0, inst, divert, func, is_extended_reg)
         || test_input(1, inst, divert, func, is_extended_reg);
     size_plus_maybe_sib_or_offset_for_inreg_1(sizing, enc, inst, divert, func)
         + if needs_rex { 1 } else { 0 }
 }
 
+/// Calculates the size while inferring if the first and second input registers (inreg0, inreg1)
+/// require a dynamic REX prefix and if the second input register (inreg1) requires a SIB.
+fn size_plus_maybe_sib_inreg1_plus_rex_prefix_for_inreg0_inreg1(
+    sizing: &RecipeSizing,
+    enc: Encoding,
+    inst: Inst,
+    divert: &RegDiversions,
+    func: &Function,
+) -> u8 {
+    // No need to check for REX.W in `needs_rex` because `infer_rex().w()` is not allowed.
+    let needs_rex = test_input(0, inst, divert, func, is_extended_reg)
+        || test_input(1, inst, divert, func, is_extended_reg);
+    size_plus_maybe_sib_for_inreg_1(sizing, enc, inst, divert, func) + if needs_rex { 1 } else { 0 }
+}
+
 /// Calculates the size while inferring if the first input register (inreg0) and first output
 /// register (outreg0) require a dynamic REX and if the first input register (inreg0) requires a
 /// SIB or offset.
 fn size_plus_maybe_sib_or_offset_for_inreg_0_plus_rex_prefix_for_inreg0_outreg0(
     sizing: &RecipeSizing,
     enc: Encoding,
     inst: Inst,
     divert: &RegDiversions,
     func: &Function,
 ) -> u8 {
-    let needs_rex = (EncodingBits::from(enc.bits()).rex_w() != 0)
-        || test_input(0, inst, divert, func, is_extended_reg)
+    // No need to check for REX.W in `needs_rex` because `infer_rex().w()` is not allowed.
+    let needs_rex = test_input(0, inst, divert, func, is_extended_reg)
         || test_result(0, inst, divert, func, is_extended_reg);
     size_plus_maybe_sib_or_offset_for_inreg_0(sizing, enc, inst, divert, func)
         + if needs_rex { 1 } else { 0 }
 }
 
+/// Calculates the size while inferring if the first input register (inreg0) and first output
+/// register (outreg0) require a dynamic REX and if the first input register (inreg0) requires a
+/// SIB.
+fn size_plus_maybe_sib_for_inreg_0_plus_rex_prefix_for_inreg0_outreg0(
+    sizing: &RecipeSizing,
+    enc: Encoding,
+    inst: Inst,
+    divert: &RegDiversions,
+    func: &Function,
+) -> u8 {
+    // No need to check for REX.W in `needs_rex` because `infer_rex().w()` is not allowed.
+    let needs_rex = test_input(0, inst, divert, func, is_extended_reg)
+        || test_result(0, inst, divert, func, is_extended_reg);
+    size_plus_maybe_sib_for_inreg_0(sizing, enc, inst, divert, func) + if needs_rex { 1 } else { 0 }
+}
+
 /// Infers whether a dynamic REX prefix will be emitted, for use with one input reg.
 ///
 /// A REX prefix is known to be emitted if either:
 ///  1. The EncodingBits specify that REX.W is to be set.
 ///  2. Registers are used that require REX.R or REX.B bits for encoding.
 fn size_with_inferred_rex_for_inreg0(
     sizing: &RecipeSizing,
-    enc: Encoding,
+    _enc: Encoding,
     inst: Inst,
     divert: &RegDiversions,
     func: &Function,
 ) -> u8 {
-    let needs_rex = (EncodingBits::from(enc.bits()).rex_w() != 0)
-        || test_input(0, inst, divert, func, is_extended_reg);
+    // No need to check for REX.W in `needs_rex` because `infer_rex().w()` is not allowed.
+    let needs_rex = test_input(0, inst, divert, func, is_extended_reg);
     sizing.base_size + if needs_rex { 1 } else { 0 }
 }
 
 /// Infers whether a dynamic REX prefix will be emitted, based on the second operand.
 fn size_with_inferred_rex_for_inreg1(
     sizing: &RecipeSizing,
-    enc: Encoding,
+    _enc: Encoding,
     inst: Inst,
     divert: &RegDiversions,
     func: &Function,
 ) -> u8 {
-    let needs_rex = (EncodingBits::from(enc.bits()).rex_w() != 0)
-        || test_input(1, inst, divert, func, is_extended_reg);
+    // No need to check for REX.W in `needs_rex` because `infer_rex().w()` is not allowed.
+    let needs_rex = test_input(1, inst, divert, func, is_extended_reg);
     sizing.base_size + if needs_rex { 1 } else { 0 }
 }
 
 /// Infers whether a dynamic REX prefix will be emitted, based on the third operand.
 fn size_with_inferred_rex_for_inreg2(
     sizing: &RecipeSizing,
-    enc: Encoding,
+    _: Encoding,
     inst: Inst,
     divert: &RegDiversions,
     func: &Function,
 ) -> u8 {
-    let needs_rex = (EncodingBits::from(enc.bits()).rex_w() != 0)
-        || test_input(2, inst, divert, func, is_extended_reg);
+    // No need to check for REX.W in `needs_rex` because `infer_rex().w()` is not allowed.
+    let needs_rex = test_input(2, inst, divert, func, is_extended_reg);
     sizing.base_size + if needs_rex { 1 } else { 0 }
 }
 
 /// Infers whether a dynamic REX prefix will be emitted, for use with two input registers.
 ///
 /// A REX prefix is known to be emitted if either:
 ///  1. The EncodingBits specify that REX.W is to be set.
 ///  2. Registers are used that require REX.R or REX.B bits for encoding.
 fn size_with_inferred_rex_for_inreg0_inreg1(
     sizing: &RecipeSizing,
-    enc: Encoding,
+    _enc: Encoding,
     inst: Inst,
     divert: &RegDiversions,
     func: &Function,
 ) -> u8 {
-    let needs_rex = (EncodingBits::from(enc.bits()).rex_w() != 0)
-        || test_input(0, inst, divert, func, is_extended_reg)
+    // No need to check for REX.W in `needs_rex` because `infer_rex().w()` is not allowed.
+    let needs_rex = test_input(0, inst, divert, func, is_extended_reg)
         || test_input(1, inst, divert, func, is_extended_reg);
     sizing.base_size + if needs_rex { 1 } else { 0 }
 }
 
 /// Infers whether a dynamic REX prefix will be emitted, based on a single
 /// input register and a single output register.
 fn size_with_inferred_rex_for_inreg0_outreg0(
     sizing: &RecipeSizing,
-    enc: Encoding,
+    _enc: Encoding,
     inst: Inst,
     divert: &RegDiversions,
     func: &Function,
 ) -> u8 {
-    let needs_rex = (EncodingBits::from(enc.bits()).rex_w() != 0)
-        || test_input(0, inst, divert, func, is_extended_reg)
+    // No need to check for REX.W in `needs_rex` because `infer_rex().w()` is not allowed.
+    let needs_rex = test_input(0, inst, divert, func, is_extended_reg)
         || test_result(0, inst, divert, func, is_extended_reg);
     sizing.base_size + if needs_rex { 1 } else { 0 }
 }
 
 /// Infers whether a dynamic REX prefix will be emitted, based on a single output register.
 fn size_with_inferred_rex_for_outreg0(
     sizing: &RecipeSizing,
-    enc: Encoding,
+    _enc: Encoding,
     inst: Inst,
     divert: &RegDiversions,
     func: &Function,
 ) -> u8 {
-    let needs_rex = (EncodingBits::from(enc.bits()).rex_w() != 0)
-        || test_result(0, inst, divert, func, is_extended_reg);
+    // No need to check for REX.W in `needs_rex` because `infer_rex().w()` is not allowed.
+    let needs_rex = test_result(0, inst, divert, func, is_extended_reg);
     sizing.base_size + if needs_rex { 1 } else { 0 }
 }
 
 /// Infers whether a dynamic REX prefix will be emitted, for use with CMOV.
 ///
 /// CMOV uses 3 inputs, with the REX is inferred from reg1 and reg2.
 fn size_with_inferred_rex_for_cmov(
     sizing: &RecipeSizing,
-    enc: Encoding,
+    _enc: Encoding,
     inst: Inst,
     divert: &RegDiversions,
     func: &Function,
 ) -> u8 {
-    let needs_rex = (EncodingBits::from(enc.bits()).rex_w() != 0)
-        || test_input(1, inst, divert, func, is_extended_reg)
+    // No need to check for REX.W in `needs_rex` because `infer_rex().w()` is not allowed.
+    let needs_rex = test_input(1, inst, divert, func, is_extended_reg)
         || test_input(2, inst, divert, func, is_extended_reg);
     sizing.base_size + if needs_rex { 1 } else { 0 }
 }
 
 /// If the value's definition is a constant immediate, returns its unpacked value, or None
 /// otherwise.
 fn maybe_iconst_imm(pos: &FuncCursor, value: ir::Value) -> Option<i64> {
     if let ir::ValueDef::Result(inst, _) = &pos.func.dfg.value_def(value) {
--- a/third_party/rust/cranelift-codegen/src/isa/x86/fde.rs
+++ b/third_party/rust/cranelift-codegen/src/isa/x86/fde.rs
@@ -5,16 +5,17 @@ use crate::ir::{FrameLayoutChange, Funct
 use crate::isa::{CallConv, RegUnit, TargetIsa};
 use alloc::vec::Vec;
 use core::convert::TryInto;
 use gimli::write::{
     Address, CallFrameInstruction, CommonInformationEntry, EhFrame, EndianVec,
     FrameDescriptionEntry, FrameTable, Result, Writer,
 };
 use gimli::{Encoding, Format, LittleEndian, Register, X86_64};
+use thiserror::Error;
 
 pub type FDERelocEntry = (FrameUnwindOffset, Reloc);
 
 const FUNCTION_ENTRY_ADDRESS: Address = Address::Symbol {
     symbol: 0,
     addend: 0,
 };
 
@@ -69,18 +70,25 @@ impl Writer for FDEWriter {
     }
 }
 
 fn return_address_reg(isa: &dyn TargetIsa) -> Register {
     assert!(isa.name() == "x86" && isa.pointer_bits() == 64);
     X86_64::RA
 }
 
-fn map_reg(isa: &dyn TargetIsa, reg: RegUnit) -> Register {
-    assert!(isa.name() == "x86" && isa.pointer_bits() == 64);
+/// Map Cranelift registers to their corresponding Gimli registers.
+pub fn map_reg(
+    isa: &dyn TargetIsa,
+    reg: RegUnit,
+) -> core::result::Result<Register, RegisterMappingError> {
+    if isa.name() != "x86" || isa.pointer_bits() != 64 {
+        return Err(RegisterMappingError::UnsupportedArchitecture);
+    }
+
     // Mapping from https://github.com/bytecodealliance/cranelift/pull/902 by @iximeow
     const X86_GP_REG_MAP: [gimli::Register; 16] = [
         X86_64::RAX,
         X86_64::RCX,
         X86_64::RDX,
         X86_64::RBX,
         X86_64::RSP,
         X86_64::RBP,
@@ -108,40 +116,51 @@ fn map_reg(isa: &dyn TargetIsa, reg: Reg
         X86_64::XMM9,
         X86_64::XMM10,
         X86_64::XMM11,
         X86_64::XMM12,
         X86_64::XMM13,
         X86_64::XMM14,
         X86_64::XMM15,
     ];
+
     let reg_info = isa.register_info();
-    let bank = reg_info.bank_containing_regunit(reg).unwrap();
+    let bank = reg_info
+        .bank_containing_regunit(reg)
+        .ok_or_else(|| RegisterMappingError::MissingBank)?;
     match bank.name {
         "IntRegs" => {
             // x86 GP registers have a weird mapping to DWARF registers, so we use a
             // lookup table.
-            X86_GP_REG_MAP[(reg - bank.first_unit) as usize]
+            Ok(X86_GP_REG_MAP[(reg - bank.first_unit) as usize])
         }
-        "FloatRegs" => X86_XMM_REG_MAP[(reg - bank.first_unit) as usize],
-        _ => {
-            panic!("unsupported register bank: {}", bank.name);
-        }
+        "FloatRegs" => Ok(X86_XMM_REG_MAP[(reg - bank.first_unit) as usize]),
+        _ => Err(RegisterMappingError::UnsupportedRegisterBank(bank.name)),
     }
 }
 
+#[derive(Error, Debug)]
+pub enum RegisterMappingError {
+    #[error("unable to find bank for register info")]
+    MissingBank,
+    #[error("register mapping is currently only implemented for x86_64")]
+    UnsupportedArchitecture,
+    #[error("unsupported register bank: {0}")]
+    UnsupportedRegisterBank(&'static str),
+}
+
 fn to_cfi(
     isa: &dyn TargetIsa,
     change: &FrameLayoutChange,
     cfa_def_reg: &mut Register,
     cfa_def_offset: &mut i32,
 ) -> Option<CallFrameInstruction> {
     Some(match change {
         FrameLayoutChange::CallFrameAddressAt { reg, offset } => {
-            let mapped = map_reg(isa, *reg);
+            let mapped = map_reg(isa, *reg).expect("a register mapping from cranelift to gimli");
             let offset = (*offset) as i32;
             if mapped != *cfa_def_reg && offset != *cfa_def_offset {
                 *cfa_def_reg = mapped;
                 *cfa_def_offset = offset;
                 CallFrameInstruction::Cfa(mapped, offset)
             } else if offset != *cfa_def_offset {
                 *cfa_def_offset = offset;
                 CallFrameInstruction::CfaOffset(offset)
@@ -150,17 +169,17 @@ fn to_cfi(
                 CallFrameInstruction::CfaRegister(mapped)
             } else {
                 return None;
             }
         }
         FrameLayoutChange::RegAt { reg, cfa_offset } => {
             assert!(cfa_offset % -8 == 0);
             let cfa_offset = *cfa_offset as i32;
-            let mapped = map_reg(isa, *reg);
+            let mapped = map_reg(isa, *reg).expect("a register mapping from cranelift to gimli");
             CallFrameInstruction::Offset(mapped, cfa_offset)
         }
         FrameLayoutChange::ReturnAddressAt { cfa_offset } => {
             assert!(cfa_offset % -8 == 0);
             let cfa_offset = *cfa_offset as i32;
             CallFrameInstruction::Offset(X86_64::RA, cfa_offset)
         }
         FrameLayoutChange::Preserve => CallFrameInstruction::RememberState,
--- a/third_party/rust/cranelift-codegen/src/isa/x86/mod.rs
+++ b/third_party/rust/cranelift-codegen/src/isa/x86/mod.rs
@@ -5,16 +5,19 @@ mod binemit;
 mod enc_tables;
 #[cfg(feature = "unwind")]
 mod fde;
 mod registers;
 pub mod settings;
 #[cfg(feature = "unwind")]
 mod unwind;
 
+#[cfg(feature = "unwind")]
+pub use fde::map_reg;
+
 use super::super::settings as shared_settings;
 #[cfg(feature = "testing_hooks")]
 use crate::binemit::CodeSink;
 use crate::binemit::{emit_function, MemoryCodeSink};
 #[cfg(feature = "unwind")]
 use crate::binemit::{FrameUnwindKind, FrameUnwindSink};
 use crate::ir;
 use crate::isa::enc_tables::{self as shared_enc_tables, lookup_enclist, Encodings};
--- a/third_party/rust/cranelift-codegen/src/simple_preopt.rs
+++ b/third_party/rust/cranelift-codegen/src/simple_preopt.rs
@@ -897,18 +897,18 @@ fn branch_order(pos: &mut FuncCursor, cf
                     }
                     _ => return,
                 }
             }
 
             _ => return,
         };
 
-    let cond_args = { cond_inst_args.as_slice(&pos.func.dfg.value_lists).to_vec() };
-    let term_args = { term_inst_args.as_slice(&pos.func.dfg.value_lists).to_vec() };
+    let cond_args = cond_inst_args.as_slice(&pos.func.dfg.value_lists).to_vec();
+    let term_args = term_inst_args.as_slice(&pos.func.dfg.value_lists).to_vec();
 
     match kind {
         BranchOrderKind::BrnzToBrz(cond_arg) => {
             pos.func
                 .dfg
                 .replace(term_inst)
                 .jump(cond_dest, &cond_args[1..]);
             pos.func
--- a/third_party/rust/cranelift-entity/.cargo-checksum.json
+++ b/third_party/rust/cranelift-entity/.cargo-checksum.json
@@ -1,1 +1,1 @@
-{"files":{"Cargo.toml":"0a7762f80abf6e2dbe73b7020fdbea138e6dab10809b15dc6a08249d58c3c422","LICENSE":"268872b9816f90fd8e85db5a28d33f8150ebb8dd016653fb39ef1f94f2686bc5","README.md":"96ceffbfd88fb06e3b41aa4d3087cffbbf8441d04eba7ab09662a72ab600a321","src/boxed_slice.rs":"69d539b72460c0aba1d30e0b72efb0c29d61558574d751c784794e14abf41352","src/iter.rs":"4a4d3309fe9aad14fd7702f02459f4277b4ddb50dba700e58dcc75665ffebfb3","src/keys.rs":"b8c2fba26dee15bf3d1880bb2b41e8d66fe1428d242ee6d9fd30ee94bbd0407d","src/lib.rs":"f6d738a46f1dca8b0c82a5910d86cd572a3585ab7ef9f73dac96962529069190","src/list.rs":"4bf609eb7cc7c000c18da746596d5fcc67eece3f919ee2d76e19f6ac371640d1","src/map.rs":"546b36be4cbbd2423bacbed69cbe114c63538c3f635e15284ab8e4223e717705","src/packed_option.rs":"dccb3dd6fc87eba0101de56417f21cab67a4394831df9fa41e3bbddb70cdf694","src/primary.rs":"30d5e2ab8427fd2b2c29da395812766049e3c40845cc887af3ee233dba91a063","src/set.rs":"b040054b8baa0599e64df9ee841640688e2a73b6eabbdc5a4f15334412db052a","src/sparse.rs":"536e31fdcf64450526f5e5b85e97406c26b998bc7e0d8161b6b449c24265449f"},"package":null}
\ No newline at end of file
+{"files":{"Cargo.toml":"b598da46e55aafd9d05c0d90bda8819edcb593141d1992c21b44639910d12981","LICENSE":"268872b9816f90fd8e85db5a28d33f8150ebb8dd016653fb39ef1f94f2686bc5","README.md":"96ceffbfd88fb06e3b41aa4d3087cffbbf8441d04eba7ab09662a72ab600a321","src/boxed_slice.rs":"69d539b72460c0aba1d30e0b72efb0c29d61558574d751c784794e14abf41352","src/iter.rs":"4a4d3309fe9aad14fd7702f02459f4277b4ddb50dba700e58dcc75665ffebfb3","src/keys.rs":"b8c2fba26dee15bf3d1880bb2b41e8d66fe1428d242ee6d9fd30ee94bbd0407d","src/lib.rs":"f6d738a46f1dca8b0c82a5910d86cd572a3585ab7ef9f73dac96962529069190","src/list.rs":"4bf609eb7cc7c000c18da746596d5fcc67eece3f919ee2d76e19f6ac371640d1","src/map.rs":"546b36be4cbbd2423bacbed69cbe114c63538c3f635e15284ab8e4223e717705","src/packed_option.rs":"dccb3dd6fc87eba0101de56417f21cab67a4394831df9fa41e3bbddb70cdf694","src/primary.rs":"30d5e2ab8427fd2b2c29da395812766049e3c40845cc887af3ee233dba91a063","src/set.rs":"b040054b8baa0599e64df9ee841640688e2a73b6eabbdc5a4f15334412db052a","src/sparse.rs":"536e31fdcf64450526f5e5b85e97406c26b998bc7e0d8161b6b449c24265449f"},"package":null}
\ No newline at end of file
--- a/third_party/rust/cranelift-entity/Cargo.toml
+++ b/third_party/rust/cranelift-entity/Cargo.toml
@@ -1,12 +1,12 @@
 [package]
 authors = ["The Cranelift Project Developers"]
 name = "cranelift-entity"
-version = "0.60.0"
+version = "0.62.0"
 description = "Data structures using entity references as mapping keys"
 license = "Apache-2.0 WITH LLVM-exception"
 documentation = "https://docs.rs/cranelift-entity"
 repository = "https://github.com/bytecodealliance/wasmtime"
 categories = ["no-std"]
 readme = "README.md"
 keywords = ["entity", "set", "map"]
 edition = "2018"
--- a/third_party/rust/cranelift-frontend/.cargo-checksum.json
+++ b/third_party/rust/cranelift-frontend/.cargo-checksum.json
@@ -1,1 +1,1 @@
-{"files":{"Cargo.toml":"569136ca3728e465c6ea2d3e5d40226a6518566e17293d2e6f6194593ae3d783","LICENSE":"268872b9816f90fd8e85db5a28d33f8150ebb8dd016653fb39ef1f94f2686bc5","README.md":"dea43e8044284df50f8b8772e9b48ba8b109b45c74111ff73619775d57ad8d67","src/frontend.rs":"af0955c23a5462cc6d4a94c61ac1af5b7546a3d560e91d448452fe5c454d5da6","src/lib.rs":"5197f467d1625ee2b117a168f4b1886b4b69d4250faea6618360a5adc70b4e0c","src/ssa.rs":"339421ee9427ee7017939ca53b7b357f82af79c8a929aeb26fb6165b95f47e93","src/switch.rs":"6b7f97799e251f2b4ae6a9892fb911375e2dc9faa5d53ff93ba08988141f1f5b","src/variable.rs":"399437bd7d2ac11a7a748bad7dd1f6dac58824d374ec318f36367a9d077cc225"},"package":null}
\ No newline at end of file
+{"files":{"Cargo.toml":"0773fd1bf0dd78967f755538d2c62279eae3ce4bc442e2a21b953d9ab039d0b9","LICENSE":"268872b9816f90fd8e85db5a28d33f8150ebb8dd016653fb39ef1f94f2686bc5","README.md":"dea43e8044284df50f8b8772e9b48ba8b109b45c74111ff73619775d57ad8d67","src/frontend.rs":"579d9821aec76570b774c572e2ae0c1b8bc78f112ef2a83027051217f6bb31e4","src/lib.rs":"5197f467d1625ee2b117a168f4b1886b4b69d4250faea6618360a5adc70b4e0c","src/ssa.rs":"0cd620e4d9fbc5e249b782d8d22e8d112a70c0700b5dd312c92ef47a5c5280da","src/switch.rs":"6b7f97799e251f2b4ae6a9892fb911375e2dc9faa5d53ff93ba08988141f1f5b","src/variable.rs":"399437bd7d2ac11a7a748bad7dd1f6dac58824d374ec318f36367a9d077cc225"},"package":null}
\ No newline at end of file
--- a/third_party/rust/cranelift-frontend/Cargo.toml
+++ b/third_party/rust/cranelift-frontend/Cargo.toml
@@ -1,22 +1,22 @@
 [package]
 authors = ["The Cranelift Project Developers"]
 name = "cranelift-frontend"
-version = "0.60.0"
+version = "0.62.0"
 description = "Cranelift IR builder helper"
 license = "Apache-2.0 WITH LLVM-exception"
 documentation = "https://docs.rs/cranelift-frontend"
 categories = ["no-std"]
 repository = "https://github.com/bytecodealliance/wasmtime"
 readme = "README.md"
 edition = "2018"
 
 [dependencies]
-cranelift-codegen = { path = "../codegen", version = "0.60.0", default-features = false }
+cranelift-codegen = { path = "../codegen", version = "0.62.0", default-features = false }
 target-lexicon = "0.10"
 log = { version = "0.4.6", default-features = false }
 hashbrown = { version = "0.7", optional = true }
 smallvec = { version = "1.0.0" }
 
 [features]
 default = ["std"]
 std = ["cranelift-codegen/std"]
--- a/third_party/rust/cranelift-frontend/src/frontend.rs
+++ b/third_party/rust/cranelift-frontend/src/frontend.rs
@@ -1225,15 +1225,62 @@ block0:
     call fn0(v0, v3, v2)
     return v0
 }
 "
         );
     }
 
     #[test]
+    fn undef_vector_vars() {
+        let mut sig = Signature::new(CallConv::SystemV);
+        sig.returns.push(AbiParam::new(I8X16));
+        sig.returns.push(AbiParam::new(B8X16));
+        sig.returns.push(AbiParam::new(F32X4));
+
+        let mut fn_ctx = FunctionBuilderContext::new();
+        let mut func = Function::with_name_signature(ExternalName::testcase("sample"), sig);
+        {
+            let mut builder = FunctionBuilder::new(&mut func, &mut fn_ctx);
+
+            let block0 = builder.create_block();
+            let a = Variable::new(0);
+            let b = Variable::new(1);
+            let c = Variable::new(2);
+            builder.declare_var(a, I8X16);
+            builder.declare_var(b, B8X16);
+            builder.declare_var(c, F32X4);
+            builder.switch_to_block(block0);
+
+            let a = builder.use_var(a);
+            let b = builder.use_var(b);
+            let c = builder.use_var(c);
+            builder.ins().return_(&[a, b, c]);
+
+            builder.seal_all_blocks();
+            builder.finalize();
+        }
+
+        assert_eq!(
+            func.display(None).to_string(),
+            "function %sample() -> i8x16, b8x16, f32x4 system_v {
+block0:
+    v5 = f32const 0.0
+    v6 = splat.f32x4 v5
+    v2 -> v6
+    v4 = vconst.b8x16 0x00
+    v1 -> v4
+    v3 = vconst.i8x16 0x00
+    v0 -> v3
+    return v0, v1, v2
+}
+"
+        );
+    }
+
+    #[test]
     fn test_greatest_divisible_power_of_two() {
         assert_eq!(64, greatest_divisible_power_of_two(64));
         assert_eq!(16, greatest_divisible_power_of_two(48));
         assert_eq!(8, greatest_divisible_power_of_two(24));
         assert_eq!(1, greatest_divisible_power_of_two(25));
     }
 }
--- a/third_party/rust/cranelift-frontend/src/ssa.rs
+++ b/third_party/rust/cranelift-frontend/src/ssa.rs
@@ -4,16 +4,17 @@
 //! Zwinkau A. (2013) Simple and Efficient Construction of Static Single Assignment Form.
 //! In: Jhala R., De Bosschere K. (eds) Compiler Construction. CC 2013.
 //! Lecture Notes in Computer Science, vol 7791. Springer, Berlin, Heidelberg
 //!
 //! https://link.springer.com/content/pdf/10.1007/978-3-642-37051-9_6.pdf
 
 use crate::Variable;
 use alloc::vec::Vec;
+use core::convert::TryInto;
 use core::mem;
 use cranelift_codegen::cursor::{Cursor, FuncCursor};
 use cranelift_codegen::entity::SecondaryMap;
 use cranelift_codegen::ir::immediates::{Ieee32, Ieee64};
 use cranelift_codegen::ir::instructions::BranchInfo;
 use cranelift_codegen::ir::types::{F32, F64};
 use cranelift_codegen::ir::{Block, Function, Inst, InstBuilder, InstructionData, Type, Value};
 use cranelift_codegen::packed_option::PackedOption;
@@ -180,20 +181,23 @@ fn emit_zero(ty: Type, mut cur: FuncCurs
     } else if ty == F32 {
         cur.ins().f32const(Ieee32::with_bits(0))
     } else if ty == F64 {
         cur.ins().f64const(Ieee64::with_bits(0))
     } else if ty.is_ref() {
         cur.ins().null(ty)
     } else if ty.is_vector() {
         let scalar_ty = ty.lane_type();
-        if scalar_ty.is_int() {
-            cur.ins().iconst(ty, 0)
-        } else if scalar_ty.is_bool() {
-            cur.ins().bconst(ty, false)
+        if scalar_ty.is_int() || scalar_ty.is_bool() {
+            let zero = cur.func.dfg.constants.insert(
+                core::iter::repeat(0)
+                    .take(ty.bytes().try_into().unwrap())
+                    .collect(),
+            );
+            cur.ins().vconst(ty, zero)
         } else if scalar_ty == F32 {
             let scalar = cur.ins().f32const(Ieee32::with_bits(0));
             cur.ins().splat(ty, scalar)
         } else if scalar_ty == F64 {
             let scalar = cur.ins().f64const(Ieee64::with_bits(0));
             cur.ins().splat(ty, scalar)
         } else {
             panic!("unimplemented scalar type: {:?}", ty)
--- a/third_party/rust/cranelift-wasm/.cargo-checksum.json
+++ b/third_party/rust/cranelift-wasm/.cargo-checksum.json
@@ -1,1 +1,1 @@
-{"files":{"Cargo.toml":"fbabc7ff07bf6a0c7c4ea8b723ae2eb86ee78ce51aa37c41201b98d0064b7db2","LICENSE":"268872b9816f90fd8e85db5a28d33f8150ebb8dd016653fb39ef1f94f2686bc5","README.md":"cce724251d4abc08c6492e1e25c138ab5a0d11e9ac90bc573652b18e034f56ed","src/code_translator.rs":"984f937da07895b5a34106d78762c937879174c9c88105addbc68799211f6a34","src/environ/dummy.rs":"49bce7a8eb9f21a61c12db537b51ab6bdb3d0e1eb6253084268256d96cae68a5","src/environ/mod.rs":"b6f33f619090ff497b4e22150d77a290f259716374ac2e377b73c47cd1dafe85","src/environ/spec.rs":"3a1543f99bff340c7f6bbe3f7cb8e8ec829e4139957f3c578d5b03e29df50f9e","src/func_translator.rs":"a165063eafedbb8e6b632996f747eeb49a3d6f8a70cab6d741abfc4fd9af892d","src/lib.rs":"05b9994c062faf2065046d1e4d7caffb26823816f367d77ede6918e24fcfa6b0","src/module_translator.rs":"bcdf5a84226b726a73f4be0acb0318ca89c82584460101378e73021d85bd4485","src/sections_translator.rs":"8c4c24308332c63d16fcf19693a7ecff2239e73b4752b0d3830b273fabcee9f1","src/state/func_state.rs":"b114522784984a7cc26a3549c7c17f842885e1232254de81d938f9d155f95aa6","src/state/mod.rs":"20014cb93615467b4d20321b52f67f66040417efcaa739a4804093bb559eed19","src/state/module_state.rs":"2f299b043deb806b48583fe54bbb46708f7d8a1454b7be0eb285568064e5a7f9","src/translation_utils.rs":"cd3ab5f994e02d49baa47148b66599d37f8156cd657b61ae68aefefa32a9d806","tests/wasm_testsuite.rs":"730304f139371e5ef3fd913ec271fc4db181869b447c6ed26c54313b5c31495c"},"package":null}
\ No newline at end of file
+{"files":{"Cargo.toml":"e927f5353af12ad52c5eb349db2a62c275ec49616c7109553258d367d8118ee1","LICENSE":"268872b9816f90fd8e85db5a28d33f8150ebb8dd016653fb39ef1f94f2686bc5","README.md":"cce724251d4abc08c6492e1e25c138ab5a0d11e9ac90bc573652b18e034f56ed","src/code_translator.rs":"575fe0fe427dcc5405faf449924fe457cd8a938f86d6fd853e1536427a096dfd","src/environ/dummy.rs":"49bce7a8eb9f21a61c12db537b51ab6bdb3d0e1eb6253084268256d96cae68a5","src/environ/mod.rs":"b6f33f619090ff497b4e22150d77a290f259716374ac2e377b73c47cd1dafe85","src/environ/spec.rs":"3a1543f99bff340c7f6bbe3f7cb8e8ec829e4139957f3c578d5b03e29df50f9e","src/func_translator.rs":"a165063eafedbb8e6b632996f747eeb49a3d6f8a70cab6d741abfc4fd9af892d","src/lib.rs":"05b9994c062faf2065046d1e4d7caffb26823816f367d77ede6918e24fcfa6b0","src/module_translator.rs":"bcdf5a84226b726a73f4be0acb0318ca89c82584460101378e73021d85bd4485","src/sections_translator.rs":"8c4c24308332c63d16fcf19693a7ecff2239e73b4752b0d3830b273fabcee9f1","src/state/func_state.rs":"b114522784984a7cc26a3549c7c17f842885e1232254de81d938f9d155f95aa6","src/state/mod.rs":"20014cb93615467b4d20321b52f67f66040417efcaa739a4804093bb559eed19","src/state/module_state.rs":"2f299b043deb806b48583fe54bbb46708f7d8a1454b7be0eb285568064e5a7f9","src/translation_utils.rs":"cd3ab5f994e02d49baa47148b66599d37f8156cd657b61ae68aefefa32a9d806","tests/wasm_testsuite.rs":"730304f139371e5ef3fd913ec271fc4db181869b447c6ed26c54313b5c31495c"},"package":null}
\ No newline at end of file
--- a/third_party/rust/cranelift-wasm/Cargo.toml
+++ b/third_party/rust/cranelift-wasm/Cargo.toml
@@ -1,25 +1,26 @@
 [package]
 name = "cranelift-wasm"
-version = "0.60.0"
+version = "0.62.0"
 authors = ["The Cranelift Project Developers"]
 description = "Translator from WebAssembly to Cranelift IR"
+documentation = "https://docs.rs/cranelift-wasm"
 repository = "https://github.com/bytecodealliance/wasmtime"
 license = "Apache-2.0 WITH LLVM-exception"
 categories = ["no-std", "wasm"]
 readme = "README.md"
 keywords = ["webassembly", "wasm"]
 edition = "2018"
 
 [dependencies]
 wasmparser = { version = "0.51.0", default-features = false }
-cranelift-codegen = { path = "../codegen", version = "0.60.0", default-features = false }
-cranelift-entity = { path = "../entity", version = "0.60.0" }
-cranelift-frontend = { path = "../frontend", version = "0.60.0", default-features = false }
+cranelift-codegen = { path = "../codegen", version = "0.62.0", default-features = false }
+cranelift-entity = { path = "../entity", version = "0.62.0" }
+cranelift-frontend = { path = "../frontend", version = "0.62.0", default-features = false }
 hashbrown = { version = "0.7", optional = true }
 log = { version = "0.4.6", default-features = false }
 serde = { version = "1.0.94", features = ["derive"], optional = true }
 thiserror = "1.0.4"
 
 [dev-dependencies]
 wat = "1.0.9"
 target-lexicon = "0.10"
--- a/third_party/rust/cranelift-wasm/src/code_translator.rs
+++ b/third_party/rust/cranelift-wasm/src/code_translator.rs
@@ -27,16 +27,17 @@ use crate::environ::{FuncEnvironment, Gl
 use crate::state::{ControlStackFrame, ElseData, FuncTranslationState, ModuleTranslationState};
 use crate::translation_utils::{
     block_with_params, blocktype_params_results, f32_translation, f64_translation,
 };
 use crate::translation_utils::{FuncIndex, GlobalIndex, MemoryIndex, SignatureIndex, TableIndex};
 use crate::wasm_unsupported;
 use core::{i32, u32};
 use cranelift_codegen::ir::condcodes::{FloatCC, IntCC};
+use cranelift_codegen::ir::immediates::Offset32;
 use cranelift_codegen::ir::types::*;
 use cranelift_codegen::ir::{
     self, ConstantData, InstBuilder, JumpTableData, MemFlags, Value, ValueLabel,
 };
 use cranelift_codegen::packed_option::ReservedValue;
 use cranelift_frontend::{FunctionBuilder, Variable};
 use std::vec::Vec;
 use wasmparser::{MemoryImmediate, Operator};
@@ -646,16 +647,58 @@ pub fn translate_operator<FE: FuncEnviro
         } => {
             translate_load(*offset, ir::Opcode::Load, F64, builder, state, environ)?;
         }
         Operator::V128Load {
             memarg: MemoryImmediate { flags: _, offset },
         } => {
             translate_load(*offset, ir::Opcode::Load, I8X16, builder, state, environ)?;
         }
+        Operator::I16x8Load8x8S {
+            memarg: MemoryImmediate { flags: _, offset },
+        } => {
+            let (flags, base, offset) = prepare_load(*offset, builder, state, environ)?;
+            let loaded = builder.ins().sload8x8(flags, base, offset);
+            state.push1(loaded);
+        }
+        Operator::I16x8Load8x8U {
+            memarg: MemoryImmediate { flags: _, offset },
+        } => {
+            let (flags, base, offset) = prepare_load(*offset, builder, state, environ)?;
+            let loaded = builder.ins().uload8x8(flags, base, offset);
+            state.push1(loaded);
+        }
+        Operator::I32x4Load16x4S {
+            memarg: MemoryImmediate { flags: _, offset },
+        } => {
+            let (flags, base, offset) = prepare_load(*offset, builder, state, environ)?;
+            let loaded = builder.ins().sload16x4(flags, base, offset);
+            state.push1(loaded);
+        }
+        Operator::I32x4Load16x4U {
+            memarg: MemoryImmediate { flags: _, offset },
+        } => {
+            let (flags, base, offset) = prepare_load(*offset, builder, state, environ)?;
+            let loaded = builder.ins().uload16x4(flags, base, offset);
+            state.push1(loaded);
+        }
+        Operator::I64x2Load32x2S {
+            memarg: MemoryImmediate { flags: _, offset },
+        } => {
+            let (flags, base, offset) = prepare_load(*offset, builder, state, environ)?;
+            let loaded = builder.ins().sload32x2(flags, base, offset);
+            state.push1(loaded);
+        }
+        Operator::I64x2Load32x2U {
+            memarg: MemoryImmediate { flags: _, offset },
+        } => {
+            let (flags, base, offset) = prepare_load(*offset, builder, state, environ)?;
+            let loaded = builder.ins().uload32x2(flags, base, offset);
+            state.push1(loaded);
+        }
         /****************************** Store instructions ***********************************
          * Wasm specifies an integer alignment flag but we drop it in Cranelift.
          * The memory base address is provided by the environment.
          ************************************************************************************/
         Operator::I32Store {
             memarg: MemoryImmediate { flags: _, offset },
         }
         | Operator::I64Store {
@@ -1513,23 +1556,17 @@ pub fn translate_operator<FE: FuncEnviro
         | Operator::I16x8NarrowI32x4U { .. }
         | Operator::I16x8WidenLowI8x16S { .. }
         | Operator::I16x8WidenHighI8x16S { .. }
         | Operator::I16x8WidenLowI8x16U { .. }
         | Operator::I16x8WidenHighI8x16U { .. }
         | Operator::I32x4WidenLowI16x8S { .. }
         | Operator::I32x4WidenHighI16x8S { .. }
         | Operator::I32x4WidenLowI16x8U { .. }
-        | Operator::I32x4WidenHighI16x8U { .. }
-        | Operator::I16x8Load8x8S { .. }
-        | Operator::I16x8Load8x8U { .. }
-        | Operator::I32x4Load16x4S { .. }
-        | Operator::I32x4Load16x4U { .. }
-        | Operator::I64x2Load32x2S { .. }
-        | Operator::I64x2Load32x2U { .. } => {
+        | Operator::I32x4WidenHighI16x8U { .. } => {
             return Err(wasm_unsupported!("proposed SIMD operator {:?}", op));
         }
     };
     Ok(())
 }
 
 // Clippy warns us of some fields we are deliberately ignoring
 #[cfg_attr(feature = "cargo-clippy", allow(clippy::unneeded_field_pattern))]
@@ -1691,36 +1728,48 @@ fn get_heap_addr(
         // Offset doesn't fit in the load/store instruction.
         let adj = builder.ins().iadd_imm(base, i64::from(i32::MAX) + 1);
         (adj, (offset - (i32::MAX as u32 + 1)) as i32)
     } else {
         (base, offset as i32)
     }
 }
 
+/// Prepare for a load; factors out common functionality between load and load_extend operations.
+fn prepare_load<FE: FuncEnvironment + ?Sized>(
+    offset: u32,
+    builder: &mut FunctionBuilder,
+    state: &mut FuncTranslationState,
+    environ: &mut FE,
+) -> WasmResult<(MemFlags, Value, Offset32)> {
+    let addr32 = state.pop1();
+
+    // We don't yet support multiple linear memories.
+    let heap = state.get_heap(builder.func, 0, environ)?;
+    let (base, offset) = get_heap_addr(heap, addr32, offset, environ.pointer_type(), builder);
+
+    // Note that we don't set `is_aligned` here, even if the load instruction's
+    // alignment immediate says it's aligned, because WebAssembly's immediate
+    // field is just a hint, while Cranelift's aligned flag needs a guarantee.
+    let flags = MemFlags::new();
+
+    Ok((flags, base, offset.into()))
+}
+
 /// Translate a load instruction.
 fn translate_load<FE: FuncEnvironment + ?Sized>(
     offset: u32,
     opcode: ir::Opcode,
     result_ty: Type,
     builder: &mut FunctionBuilder,
     state: &mut FuncTranslationState,
     environ: &mut FE,
 ) -> WasmResult<()> {
-    let addr32 = state.pop1();
-    // We don't yet support multiple linear memories.
-    let heap = state.get_heap(builder.func, 0, environ)?;
-    let (base, offset) = get_heap_addr(heap, addr32, offset, environ.pointer_type(), builder);
-    // Note that we don't set `is_aligned` here, even if the load instruction's
-    // alignment immediate says it's aligned, because WebAssembly's immediate
-    // field is just a hint, while Cranelift's aligned flag needs a guarantee.
-    let flags = MemFlags::new();
-    let (load, dfg) = builder
-        .ins()
-        .Load(opcode, result_ty, flags, offset.into(), base);
+    let (flags, base, offset) = prepare_load(offset, builder, state, environ)?;
+    let (load, dfg) = builder.ins().Load(opcode, result_ty, flags, offset, base);
     state.push1(dfg.first_result(load));
     Ok(())
 }
 
 /// Translate a store instruction.
 fn translate_store<FE: FuncEnvironment + ?Sized>(
     offset: u32,
     opcode: ir::Opcode,